CN112448568B - Overvoltage clamping circuit - Google Patents
Overvoltage clamping circuit Download PDFInfo
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- CN112448568B CN112448568B CN201910818327.2A CN201910818327A CN112448568B CN 112448568 B CN112448568 B CN 112448568B CN 201910818327 A CN201910818327 A CN 201910818327A CN 112448568 B CN112448568 B CN 112448568B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Abstract
An overvoltage clamping circuit capable of changing an original bipolar point clamping loop into a unipolar point loop system so as to be beneficial to more simply and more easily realizing frequency compensation of the clamping loop, the overvoltage clamping circuit is characterized by comprising an input voltage end and an output voltage end, wherein the input voltage end is connected with a grounding end through an output capacitor, a grid electrode of an NMOS power tube is connected with a grid electrode of a first current sampling NMOS tube and then respectively connected with an output end of a charge pump and an output end of a first operational amplifier, an input end of the charge pump and a drain electrode of the first current sampling NMOS tube are both connected with the input voltage end, the first current sampling NMOS tube is respectively connected with a positive input end of the first operational amplifier and one end of a second voltage-dividing resistor through a first voltage-dividing resistor, and the other end of the second voltage-dividing resistor is connected with the grounding end, and the negative input end of the first operational amplifier is connected with a reference voltage end.
Description
Technical Field
The invention relates to a clamping technology of load working voltage at the downstream of a load switch, in particular to an overvoltage clamping circuit, which is characterized in that a new loop formed by a first current sampling NMOS tube, a divider resistor and a first operational amplifier is introduced, so that an NMOS power tube and an output end pole thereof are all excluded from the new loop, and the original bipolar point clamping loop can be changed into a unipolar point loop system, thereby being beneficial to realizing the frequency compensation of the clamping loop more simply and more easily, sampling the output current, adjusting the grid source voltage of the current sampling NMOS tube, and further reducing the load adjustment rate of the output clamping voltage.
Background
The load switch is widely applied to various power management systems, is an important component in power and system monitoring products, and has a protection function on both a power supply and a load. Since the loads downstream of the load switch are required to operate within a safe voltage range, and the overvoltage may break down the load circuit to damage it, the overvoltage clamp becomes particularly important to clamp the downstream load source to within the safe voltage range. As shown in fig. 1, the overvoltage clamping circuit in the prior art includes two poles, namely a first pole0 and a second pole1, the first pole0 is located at the output end of the Charge pump, the second pole1 is located at the output voltage terminal VOUT, the output voltage terminal VOUT is respectively connected to one end of an output capacitor COUT, one end of a first voltage-dividing resistor R0 and the source of the NMOS Power transistor Power, the other end of the output capacitor COUT is connected to a ground terminal GND, the other end of the first voltage-dividing resistor R0 is respectively connected to a positive input terminal (+) of a first operational amplifier OP and one end of a second voltage-dividing resistor R1, the other end of the second voltage-dividing resistor R1 is connected to the ground terminal GND, a negative input terminal (-) of the first operational amplifier is connected to a reference voltage terminal Vref, the reference voltage terminal is connected to the ground terminal through a voltage source, the output terminal of the first operational amplifier OP is respectively connected to the output end of the Charge pump and the gate of the NMOS Power transistor Power, and the drain electrode of the NMOS Power device and the input end of the Charge pump are both connected with an input voltage end VIN. In fig. 1, there are two poles 0 and 1, and the parasitic capacitance is also large due to the large area of the NMOS Power transistor Power device, resulting in the first pole0 being relatively low frequency. The second pole1 is affected by both the output capacitor COUT and the output current IOUT. If the range of variation of COUT and IOUT is large, the variation of the second pole1 is large, so that the frequency compensation of the structure becomes difficult, and the range of COUT and IOUT is usually limited, so that the application range of the circuit is limited. The inventor believes that if a new loop formed by introducing the first current sampling NMOS transistor Sense device, the voltage dividing resistors (the first voltage dividing resistor R0 and the second voltage dividing resistor R1) and the first operational amplifier OP enables the NMOS Power device and the output terminal pole (the second pole1) thereof to be excluded from the new loop, the original bipolar point (pole0 and pole1) clamp loop can be changed into a unipolar point (pole0) loop system, and the frequency compensation of the clamp loop can be realized more simply and more easily. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides an overvoltage clamping circuit, which is characterized in that a new loop formed by a first current sampling NMOS tube, a divider resistor and a first operational amplifier is introduced, so that an NMOS power tube and an output end pole of the NMOS power tube are all excluded from the new loop, and the original bipolar point clamping loop can be changed into a unipolar point loop system, thereby being beneficial to realizing the frequency compensation of the clamping loop more simply and more easily, sampling the output current, adjusting the grid source voltage of the current sampling NMOS tube and further reducing the load adjustment rate of the output clamping voltage.
The technical scheme of the invention is as follows:
the overvoltage clamping circuit is characterized by comprising an input voltage end and an output voltage end, wherein the input voltage end is connected with a drain electrode of an NMOS power tube, the output voltage end is connected with a grounding end through an output capacitor, a grid electrode of the NMOS power tube is connected with a grid electrode of a first current sampling NMOS tube and then is respectively connected with an output end of a charge pump and an output end of a first operational amplifier, the input end of the charge pump and the drain electrode of the first current sampling NMOS tube are both connected with the input voltage end, the first current sampling NMOS tube is respectively connected with a positive input end of the first operational amplifier and one end of a second voltage dividing resistor through a first voltage dividing resistor, the other end of the second voltage dividing resistor is connected with the grounding end, and a negative input end of the first operational amplifier is connected with a reference voltage end.
The area ratio of the first current sampling NMOS tube to the NMOS power tube is 1: n, n is an integer greater than 1.
The reference voltage end is connected with the grounding end through a voltage source.
The output voltage end is connected with the input end of a first compensation current source and the sampling tube output node of the first current sampling NMOS tube through a second compensation resistor respectively, the source electrode of the first current sampling NMOS tube is connected with the first divider resistor through a first compensation resistor, the sampling tube output node is located between the first divider resistor and the first compensation resistor, and the output end of the first compensation current source is connected with the grounding end.
The output voltage end is connected with the positive input end of a second operational amplifier, the negative input end of the second operational amplifier is respectively connected with the source electrode of a second current sampling NMOS tube and the source electrode of a first PMOS tube, the drain electrode of the second current sampling NMOS tube is connected with the input voltage end, the grid electrode of the second current sampling NMOS tube is connected with the grid electrode of an NMOS power tube, and the grid electrode of the first PMOS tube is connected with the output end of the second operational amplifier.
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the grounding terminal, the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube after being interconnected with the grid electrode, the source electrode of the second NMOS tube is connected with the grounding terminal, and the drain electrode of the second NMOS tube is connected with the source electrode of the first current sampling NMOS tube.
The area ratio of the first current sampling NMOS tube to the second current sampling NMOS tube is 1: 1.
The area ratio of the first NMOS tube to the second NMOS tube is 1: 1.
The invention has the following technical effects: the invention relates to an overvoltage clamping circuit, which is characterized in that a new loop formed by a first current sampling NMOS (N-channel metal oxide semiconductor) transistor device, a divider resistor (a first divider resistor R0 and a second divider resistor R1) and a first operational amplifier OP is introduced, so that the NMOS Power transistor Power device and an output end pole (a second pole1) thereof are excluded from the new loop, and the original bipolar point (pole0 and pole1) clamping loop is changed into a unipolar point (pole0) loop system, so that the frequency compensation of the clamping loop is realized more simply and more easily. Although a first current sampling NMOS transistor Sense device source output end pole is generated in the new loop, the pole belongs to a high-frequency pole which does not influence the frequency compensation of the new loop. Because the output end pole of the NMOS Power device does not belong to a new loop, the influence of the output end pole on the frequency compensation of the new loop is small or has no influence, the output current is sampled, the grid source voltage of the current sampling NMOS tube is adjusted, and the load adjustment rate of the output clamping voltage is further reduced. Therefore, the invention is an overvoltage clamping circuit with high stability and low load regulation rate.
Drawings
Fig. 1 is a schematic diagram of a prior art overvoltage clamp circuit.
Fig. 2 is a schematic diagram of an overvoltage clamping circuit embodying the present invention. Compared with the prior art, the first current sampling NMOS transistor Sense device (sampling current IS), the first compensation resistor Rc0, the second compensation resistor Rc1 and the first compensation current source Ic0 are added in fig. 2.
Fig. 3 is another schematic diagram of an overvoltage clamp embodying the invention. In fig. 3, a first current sampling NMOS transistor Sense device (sampling current IS0) IS added compared to the prior art.
Fig. 4 is a waveform diagram of the voltage nodes Vg, Vs, VOUT0, VOUT, Vgs0, Vgs1 of fig. 2 as a function of the output current IOUT. The ordinate of fig. 4 is the voltage V and the abscissa is the current (IOUT). The voltage node waveforms in fig. 3 are also similar to fig. 4.
Fig. 5 is a schematic diagram of a third example of an overvoltage clamping circuit embodying the invention. Compared with the prior art, the first current sampling NMOS tube Sense device, the second current sampling NMOS tube Sense device0, the second operational amplifier OP1, the first PMOS tube Mp0, the first NMOS tube Mn0 and the second NMOS tube Mn1 are added in FIG. 5.
The reference numbers are listed below: VIN-input voltage or input voltage terminal; GND-ground; VOUT-output voltage or output voltage terminal; power device-NMOS Power tube; sense device-first current sampling NMOS tube; sense device 0-second current sampling NMOS tube; IOUT-output current; ic0 — first compensation current or first compensation current source; IS-sampling current; IS 0-sample current; COUT-output capacitance; charge pump-Charge pump; vref-reference voltage or reference voltage terminal or bias voltage (from voltage source); VFB — feedback voltage; vg-gate node or gate node voltage; vs-sample tube source voltage; vgs 0-sample tube gate-source voltage; vgs 1-power tube gate-source voltage; VOUT 0-sampling tube output node; pole0 — first pole; pole1 — the second pole (which is located inside the loop in fig. 1 and outside the loop at this point, VOUT, in fig. 2, 3, and 5); OP-a first operational amplifier; OP 1-second operational amplifier; r0-first resistor or first divider resistor; r1-a second resistor or second divider resistor; rc0 — first compensation resistance; rc1 — second compensation resistor; mp 0-first PMOS transistor; mn 0-first NMOS tube; mn 1-second NMOS tube; 1: n-represents the area ratio of the sampling tube to the power tube (n is an integer greater than 1); 1: 1-represents the area ratio of the first current sampling NMOS transistor Sense device to the second current sampling NMOS transistor Sense device0, or the area ratio of the first NMOS transistor Mn0 to the second NMOS transistor Mn1 (Mn0 and Mn1 are 1:1 current mirrors, so IS0 IS).
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 2-5).
Fig. 2 is a schematic diagram of an overvoltage clamping circuit embodying the present invention. Fig. 3 is another schematic diagram of an overvoltage clamp embodying the invention. Fig. 4 is a waveform diagram of the voltage nodes Vg, Vs, VOUT0, VOUT, Vgs0, Vgs1 of fig. 3 as a function of the output current IOUT. Fig. 5 is a schematic diagram of a third example of an overvoltage clamping circuit embodying the invention. As shown in fig. 2 to 5, an overvoltage clamping circuit includes an input voltage terminal VIN connected to a drain of an NMOS Power transistor Power device and an output voltage terminal VOUT connected to a source of the NMOS Power transistor Power device, where the output voltage terminal VOUT is connected to a ground terminal GND through an output capacitor COUT, a gate of the NMOS Power transistor Power device is interconnected with a gate of a first current sampling NMOS transistor Sense and then respectively connected to an output terminal of a Charge pump and an output terminal of a first operational amplifier OP, an input terminal of the Charge pump and a drain of the first current sampling NMOS transistor Sense are both connected to the input voltage terminal VIN, a positive input terminal (+) of the first operational amplifier OP and one end of a second voltage dividing resistor R1 of the first current sampling NMOS transistor Sense are respectively connected through a first voltage dividing resistor R0, and the other end of the second voltage dividing resistor R1 is connected to the ground terminal GND, the negative input (-) of the first operational amplifier OP is connected to the reference voltage terminal Vref. The area ratio of the Sense device of the first current sampling NMOS tube to the Power device of the NMOS Power tube is 1: n, n is an integer greater than 1. The reference voltage terminal Vref is connected to the ground terminal GND through a voltage source.
The output voltage terminal VOUT is respectively connected to an input terminal of a first compensation current source Ic0 and a sampling tube output node VOUT0 of the first current sampling NMOS tube Sense device through a second compensation resistor Rc1, a source of the first current sampling NMOS tube Sense device is connected to the first voltage dividing resistor R0 through a first compensation resistor Rc0, the sampling tube output node VOUT0 is located between the first voltage dividing resistor R0 and the first compensation resistor Rc0, and an output terminal of the first compensation current source Ic0 is connected to a ground terminal GND.
The output voltage end VOUT is connected with a positive input end (+) of a second operational amplifier OP1, a negative input end (-) of the second operational amplifier OP1 is respectively connected with a source electrode of a second current sampling NMOS tube Sense device0 and a source electrode of a first PMOS tube Mp0, a drain electrode of the second current sampling NMOS tube is connected with the input voltage end, a grid electrode of the second current sampling NMOS tube Sense device0 is connected with a grid electrode of an NMOS Power device, and a grid electrode of the first PMOS tube Mp0 is connected with an output end of the second operational amplifier OP 1. The drain electrode of the first PMOS tube Mp0 is connected with the drain electrode of a first NMOS tube Mn0, the source electrode of the first NMOS tube Mn0 is connected with a ground terminal GND, the drain electrode and the grid electrode of the first NMOS tube Mn0 are connected with the grid electrode of a second NMOS tube Mn1 after being interconnected, the source electrode of the second NMOS tube Mn1 is connected with the ground terminal GND, and the drain electrode of the second NMOS tube Mn1 is connected with the source electrode of the first current sampling NMOS tube Sense device. The area ratio of the first current sampling NMOS tube Sense device to the second current sampling NMOS tube Sense device0 is 1: 1. The area ratio of the first NMOS transistor Mn0 to the second NMOS transistor Mn1 is 1: 1.
Fig. 2 shows the overvoltage clamping circuit of the present invention, which adds a sampling tube Sense device, compensation resistors Rc0 and Rc1, and compensation current Ic0, compared with the prior art. Since the wide variation range of the pole1 in fig. 1 makes the frequency compensation of the loop difficult, and also limits the application range of the circuit, it is desirable to exclude the pole1 from the loop, so that the loop becomes a single-pole system, and thus the frequency compensation becomes simple, and the COUT and IOUT are not limited at all. Therefore, the first current sampling NMOS transistor Sense device is introduced to form a main loop together with the voltage dividing resistors R0 and R1 and the operational amplifier OP, so that the NMOS Power transistor Power device is outside the loop, and the VOUT voltage is indirectly controlled by controlling the grid potential of the first current sampling NMOS transistor Sense device. Fig. 3 shows a circuit structure of only introducing the first current sampling NMOS, where VOUT is 0+ Vgs0-Vgs1, VOUT0 is a constant value, Vgs0 is a gate-source voltage of the first current sampling NMOS, and is also a constant value, however, when the IOUT variation range is large, the gate-source voltage Vgs1 of Power device changes greatly, so VOUT may significantly decrease with an increase of the output current IOUT, so as shown in fig. 2, the first compensation resistor Rc0 and the second compensation resistor Rc1 are introduced as compensation to decrease the load regulation rate, and due to the introduction of the second compensation resistor Rc1, the second pole1 affects the loop, so the first compensation current Ic0 is introduced, and the effect of the second pole1 on the loop is decreased.
As shown in fig. 2, when the circuit operates in the clamped state, OP operates in a negative feedback loop so that the feedback voltage VFB is equal to the bias voltage Vref, i.e.
VFB＝Vref (1)
VOUT0＝(RO+R1)/R1*VFB (2)
Bringing formula (1) into formula (2) to obtain formula (3),
VOUT0＝(RO+R1)/R1*Vref (3)
Vg＝IS*Rc0+VOUT0+Vgs0 (4)
wherein IS IS the sampling current of the sampling tube, Rc0 IS the load regulation rate compensation resistance, and Vgs0 IS the gate-source voltage of the sampling tube.
VOUT＝Vg-Vgs1 (5)
Where Vgs1 is the gate-source voltage of the power transistor.
Bringing formula (3) and (4) into formula (5) or formula (6)
VOUT＝(RO+R1)/R1*Vref+IS*Rc0+Vgs0-Vgs1 (6)
Fig. 4 IS a waveform diagram of the voltage of the main node in the circuit varying with the output current IOUT, where VOUT0 IS equal to (RO + R1)/R1 Vref, which IS a constant value and does not vary with the change of IOUT, Vgs1 and Vgs0 increase with the increase of IOUT, but since the source end of the sampling tube has compensation resistors Rc0 and Rc1, the increase of Vgs0 IS not as large as Vgs1, but IS increases with the increase of IOUT, so VS ═ Rc0+ VOUT0 increases with the increase of IOUT, and therefore the increase of Vg with the increase of IOUT compensates the magnitude of IS Rc0 in the magnitude of Vgs0, therefore VOUT ═ Vg-1 varies little with the change of IOUT, and the load regulation rate becomes low after being compensated by IS Rc 0.
Fig. 5 is another topology of the overvoltage clamp of the present invention. In fig. 5, a current sampling circuit IS arranged in a dashed line frame, a source end of the NMOS Power device and a source end of the second current sampling NMOS transistor Sense device0 are clamped by an operational amplifier OP1, Vgs voltages of the two are equal, a current IOUT of the NMOS Power device IS sampled, a sampling current IS0 IS 1/n IOUT, and a first NMOS transistor Mn0 and a second NMOS transistor Mn1 are 1:1, IS0 ═ IS. Since the first current sampling NMOS transistor Sense device and the second current sampling NMOS transistor Sense device0 are the same transistor, when the currents flowing from the first current sampling NMOS transistor Sense device and the second current sampling NMOS transistor Sense device are equal, the Vgs voltages thereof are also equal, and therefore,
Vgs0＝Vgs1 (7)
Vg＝VOUT0+Vgs0＝(RO+R1)/R1*Vref+Vgs0 (8)
VOUT＝Vg-Vgs1＝(RO+R1)/R1*Vref (9)
since R0, R1, and Vref are all constant values, the VOUT clamping voltage is constant and does not vary with IOUT, and therefore an extremely low load regulation rate can be obtained. While the clamp loop can be viewed as a single pole system with only one pole0, frequency compensation becomes very easy.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalent, modified and/or simplified implementations as described above, e.g., implementations using other oscillator regulation circuits, etc., without departing from the spirit of the present invention, are intended to fall within the scope of the present invention.
Claims (7)
1. An overvoltage clamping circuit is characterized by comprising an input voltage end and an output voltage end, wherein the input voltage end is connected with a drain electrode of an NMOS power tube, the output voltage end is connected with a grounding end through an output capacitor, a grid electrode of the NMOS power tube is connected with a grid electrode of a first current sampling NMOS tube and then is respectively connected with an output end of a charge pump and an output end of a first operational amplifier, the input end of the charge pump and the drain electrode of the first current sampling NMOS tube are both connected with the input voltage end, the first current sampling NMOS tube is respectively connected with a positive input end of the first operational amplifier and one end of a second voltage dividing resistor through a first voltage dividing resistor, the other end of the second voltage dividing resistor is connected with the grounding end, and a negative input end of the first operational amplifier is connected with a reference voltage end;
the output voltage end is connected with the input end of a first compensation current source and the sampling tube output node of the first current sampling NMOS tube through a second compensation resistor respectively, the source electrode of the first current sampling NMOS tube is connected with the first divider resistor through a first compensation resistor, the sampling tube output node is located between the first divider resistor and the first compensation resistor, and the output end of the first compensation current source is connected with the grounding end.
2. The overvoltage clamp circuit of claim 1, wherein an area ratio of the first current sampling NMOS transistor to the NMOS power transistor is 1: n, n is an integer greater than 1.
3. The overvoltage clamp circuit of claim 1, wherein the reference voltage terminal is connected to ground through a voltage source.
4. The over-voltage clamp circuit of claim 1, wherein the output voltage terminal is connected to a positive input terminal of a second operational amplifier, a negative input terminal of the second operational amplifier is respectively connected to a source of a second current sampling NMOS transistor and a source of a first PMOS transistor, a drain of the second current sampling NMOS transistor is connected to the input voltage terminal, a gate of the second current sampling NMOS transistor is connected to a gate of the NMOS power transistor, and a gate of the first PMOS transistor is connected to an output terminal of the second operational amplifier.
5. The overvoltage clamping circuit of claim 4, wherein a drain of the first PMOS transistor is connected to a drain of a first NMOS transistor, a source of the first NMOS transistor is connected to ground, a drain and a gate of the first NMOS transistor are interconnected and then connected to a gate of a second NMOS transistor, a source of the second NMOS transistor is connected to ground, and a drain of the second NMOS transistor is connected to a source of the first current sampling NMOS transistor.
6. The overvoltage clamp circuit of claim 4, wherein an area ratio of the first current sampling NMOS transistor to the second current sampling NMOS transistor is 1: 1.
7. The overvoltage clamp circuit of claim 5, wherein an area ratio of the first NMOS transistor to the second NMOS transistor is 1: 1.
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| CN113917972B (en) * | 2021-10-29 | 2023-04-07 | 成都思瑞浦微电子科技有限公司 | Voltage stabilizer and chip for floating negative voltage domain |
| CN114337197B (en) * | 2021-12-31 | 2024-02-27 | 上海艾为微电子技术有限公司 | Sampling control circuit, power supply protection chip and equipment of power tube |
| CN115065246B (en) * | 2022-08-05 | 2022-11-04 | 苏州锴威特半导体股份有限公司 | Current compensation circuit for power management chip |
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