CN115065246B - Current compensation circuit for power management chip - Google Patents

Current compensation circuit for power management chip Download PDF

Info

Publication number
CN115065246B
CN115065246B CN202210935209.1A CN202210935209A CN115065246B CN 115065246 B CN115065246 B CN 115065246B CN 202210935209 A CN202210935209 A CN 202210935209A CN 115065246 B CN115065246 B CN 115065246B
Authority
CN
China
Prior art keywords
current mirror
mos transistor
mirror unit
mos
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210935209.1A
Other languages
Chinese (zh)
Other versions
CN115065246A (en
Inventor
罗寅
陈朝勇
谭在超
丁国华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Covette Semiconductor Co ltd
Original Assignee
Suzhou Covette Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Covette Semiconductor Co ltd filed Critical Suzhou Covette Semiconductor Co ltd
Priority to CN202210935209.1A priority Critical patent/CN115065246B/en
Publication of CN115065246A publication Critical patent/CN115065246A/en
Application granted granted Critical
Publication of CN115065246B publication Critical patent/CN115065246B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention relates to the technical field of power management chips, and discloses a current compensation circuit for a power management chip, which comprises an MOS tube N4, an MOS tube P6, a voltage clamping unit, a resistor R1, a first current mirror unit, a second current mirror unit, a third current mirror unit, a fourth current mirror unit and a capacitor C2, wherein when the power management chip is actually used, the voltage clamping unit controls the MOS tube N4 to be conducted or controls the MOS tube P6 to be conducted when the resistor R1 is grounded or is connected with a power supply, so that the first current mirror unit or the second current mirror unit generates current, and the current is finally mirrored by the fourth current mirror unit and then is input into the capacitor C2 to generate compensation current, therefore, the compensation circuit can be generated when the resistor R1 is grounded in a pull-down mode and is connected with the power supply in a pull-up mode, and the applicability is strong.

Description

Current compensation circuit for power management chip
Technical Field
The invention relates to the technical field of power management chips, in particular to a current compensation circuit for a power management chip.
Background
The power management chip is a chip which plays roles of conversion, distribution, detection and other electric energy management of electric energy in an electronic equipment system, and is mainly responsible for identifying the power supply amplitude of a CPU (central processing unit), generating corresponding short moment waves and pushing a rear-stage circuit to output power.
The existing power management chip needs to be externally connected with a compensation resistor for current compensation in actual use, the resistance value of the compensation resistor determines the magnitude of compensation current, one end of the compensation resistor, which is not electrically connected with the power management chip, can only be connected with a power supply in a pull-down grounding or pull-up grounding mode, and the two ends cannot be compatible with each other, so that a current compensation circuit capable of meeting the requirements of the pull-down grounding and pull-up power supply of the compensation resistor is lacked.
Disclosure of Invention
In view of the defects of the background art, the invention provides a current compensation circuit for a power management chip, and aims to solve the technical problem that the existing current compensation circuit cannot support the pull-down grounding or pull-up power connection of a compensation resistor at the same time and has poor applicability.
In order to solve the technical problems, the invention provides the following technical scheme: the current compensation circuit for the power management chip comprises an MOS tube N4, an MOS tube P6, a voltage clamping unit, a resistor R1, a first current mirror unit and a second current mirror unit; the voltage clamping unit comprises a voltage input end, a first voltage output end and a second voltage output end;
the grid electrode of the MOS tube N4 and the grid electrode of the MOS tube P6 are respectively and electrically connected with the second voltage output end; the drain electrode of the MOS tube N4 is electrically connected with the main current mirror unit of the first current mirror unit; the source electrode of the MOS tube N4 is respectively and electrically connected with the source electrode of the MOS tube P6 and the first voltage output end, and the drain electrode of the MOS tube P6 is electrically connected with the main current mirror unit of the second current mirror unit;
the first voltage output end is electrically connected with one end of the resistor R1; the voltage input end of the voltage clamping unit is configured to input a reference voltage, and the voltage clamping unit clamps the voltage of the first voltage output end to the reference voltage; when the other end of the resistor R1 is grounded, the voltage clamping unit clamps the voltage of the second voltage output end to a second voltage, and the second voltage is greater than the reference voltage; when the other end of the resistor R1 is connected with a power supply, the voltage clamping unit clamps the voltage of the second voltage output end to a third voltage, and the third voltage is smaller than the reference voltage.
In a certain embodiment, the voltage clamping unit includes a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor P4, a MOS transistor P5, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3, a resistor R2, and a capacitor C1;
the source electrode of the MOS tube P1 is respectively and electrically connected with the source electrode of the MOS tube P2 and the source electrode of the MOS tube P3;
the drain electrode of the MOS tube P1 is electrically connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2 and the grid electrode of the MOS tube P3 respectively;
the drain electrode of the MOS tube P2 is respectively and electrically connected with the source electrode of the MOS tube P4 and the source electrode of the MOS tube P5; the grid electrode of the MOS tube P4 is a first voltage output end and is electrically connected with one end of the resistor R1; the drain electrode of the MOS tube P4 is respectively and electrically connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 is respectively and electrically connected with the source electrode of the MOS tube N2 and the source electrode of the MOS tube N3;
the grid of MOS pipe P5 is the voltage input end, and the drain electrode of MOS pipe P5 is connected with the drain electrode of MOS pipe N2, resistance R2 one end and the grid electricity of MOS pipe N3 respectively, and the resistance R2 other end is connected with electric capacity C1 one end electricity, and the electric capacity C1 other end is second voltage output end, is connected with the drain electrode of MOS pipe P3 and the drain electrode electricity of MOS pipe N3 respectively.
In one embodiment, the present invention further comprises a third current mirror unit, a fourth current mirror unit, and a capacitor C2, the slave current mirror unit of the first current mirror unit being electrically connected to the master current mirror unit of the third current mirror unit; the slave current mirror unit of the third current mirror unit and the slave current mirror unit of the second current mirror unit are electrically connected to the master current mirror unit of the fourth current mirror unit, respectively, and the slave current mirror unit of the fourth current mirror unit is electrically connected to one end of the capacitor C2.
In one embodiment, the master current mirror unit of the first current mirror unit comprises MOS transistor P7, and the slave current mirror unit of the first current mirror unit comprises MOS transistor P9; the source electrode of the MOS transistor P7 is electrically connected with the source electrode of the MOS transistor P9, the drain electrode of the MOS transistor P7 is respectively electrically connected with the drain electrode of the MOS transistor N4, the grid electrode of the MOS transistor P7 and the grid electrode of the MOS transistor P9, and the drain electrode of the MOS transistor P9 is electrically connected with the main current mirror unit of the third current mirror unit;
the main current mirror unit of the second current mirror unit comprises an MOS transistor N5, and the slave current mirror unit of the second current mirror unit comprises an MOS transistor N7; the drain electrode of the MOS transistor N5 is respectively and electrically connected with the drain electrode of the MOS transistor P6, the grid electrode of the MOS transistor N5 and the grid electrode of the MOS transistor N7, the source electrode of the MOS transistor N5 is electrically connected with the source electrode of the MOS transistor N7, and the drain electrode of the MOS transistor N7 is electrically connected with the main current mirror unit of the fourth current mirror unit.
In a certain embodiment, the slave current mirror unit of the first current mirror unit further includes a MOS transistor P8, and the slave current mirror unit of the second current mirror unit further includes a MOS transistor N6;
the source electrode of the MOS tube P8 is electrically connected with the source electrode of the MOS tube P7, the grid electrode of the MOS tube P8 is electrically connected with the grid electrode of the MOS tube P7, and the drain electrode of the MOS tube P8 is respectively electrically connected with the input end of the phase inverter X1 and the drain electrode of the MOS tube N6; the grid electrode of the MOS transistor N6 is electrically connected with the grid electrode of the MOS transistor N5, and the source electrode of the MOS transistor N6 is electrically connected with the source electrode of the MOS transistor N5.
In one embodiment, the master current mirror unit of the third current mirror unit comprises MOS transistor N8, and the slave current mirror unit of the third current mirror unit comprises MOS transistor N9;
the drain electrode of the MOS tube N8 is respectively and electrically connected with the drain electrode of the MOS tube P9, the grid electrode of the MOS tube N8 and the grid electrode of the MOS tube N9; the source electrode of the MOS tube N8 is electrically connected with the source electrode of the MOS tube N9; the drain electrode of the MOS transistor N9 is electrically connected with the main current mirror unit of the fourth current mirror unit.
In a certain embodiment, the master current mirror unit of the fourth current mirror unit includes a MOS transistor P10 and a MOS transistor P11, and the slave current mirror unit of the fourth current mirror unit includes a MOS transistor P12 and a MOS transistor P13;
the source electrode of the MOS tube P10 is electrically connected with the source electrode of the MOS tube P12; the drain electrode of the MOS tube P10 is electrically connected with the source electrode of the MOS tube P11, the grid electrode of the MOS tube P10 and the grid electrode of the MOS tube P12 respectively, and the drain electrode of the MOS tube P12 is electrically connected with the source electrode of the MOS tube P13; the drain electrode of the MOS transistor P11 is electrically connected with the drain electrode of the MOS transistor N9, the drain electrode of the MOS transistor N7, the grid electrode of the MOS transistor P11 and the grid electrode of the MOS transistor P13 respectively, and the drain electrode of the MOS transistor P13 is electrically connected with one end of the capacitor C2.
Compared with the prior art, the invention has the beneficial effects that: in practical use, when the other end of the resistor R1 is grounded, since the second voltage is greater than the reference voltage, the MOS transistor N4 is turned on, the MOS transistor P6 is turned off, the main current mirror unit of the first current mirror unit generates a current I1, assuming that the reference voltage is Vbias, and the current I1 is Vbias/R1;
when the other end of the resistor R1 is connected with a power supply, the MOS transistor N4 is turned off, the MOS transistor P6 is turned on, the second current mirror unit generates a current I2, and the magnitude of the current I2 is (VDD-Vbias)/R1 on the assumption that the voltage magnitude of the power supply is VDD, so that the compensation current can be generated when the compensation resistor, namely the resistor R1 is pulled down to the ground or pulled up to the power supply, and the applicability is strong;
in addition, as the current I1 is mirrored by the secondary current mirror unit, the third current mirror unit and the fourth current mirror unit of the first current mirror unit and then is input to one end of the capacitor C2, the other end of the capacitor C2 outputs the compensation current, the current I2 is mirrored by the secondary current mirror unit and the fourth current mirror unit of the second current mirror unit and then is input to one end of the capacitor C2, and the other end of the capacitor C2 outputs the compensation current; therefore, no matter the resistor R1 is pulled down to be grounded or pulled up to be connected with a power supply, the third current mirror unit and the fourth current mirror unit can finally output one path of compensation current.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a circuit diagram of the connection between the voltage clamping unit and the resistor R1;
fig. 3 is a first circuit diagram of the MOS transistor N4, the MOS transistor P6 and four current mirror units;
fig. 4 is a second circuit diagram of MOS transistor N4, MOS transistor P6, and four current mirror units.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic views illustrating only the basic structure of the present invention in a schematic manner, and thus show only the constitution related to the present invention.
As shown in fig. 1, the current compensation circuit for a power management chip includes an MOS transistor N4, an MOS transistor P6, a voltage clamping unit 5, a resistor R1, a first current mirror unit 1, a second current mirror unit 2, a third current mirror unit 3, a fourth current mirror unit 4, and a capacitor C2; the voltage clamping unit 5 comprises a voltage input end VIN, a first voltage output end Vo1 and a second voltage output end Vo2;
the grid electrode of the MOS transistor N4 and the grid electrode of the MOS transistor P6 are respectively and electrically connected with the second voltage output end Vo2; the drain electrode of the MOS tube N4 is electrically connected with the main current mirror unit of the first current mirror unit 1; the source electrode of the MOS transistor N4 is electrically connected with the source electrode of the MOS transistor P6 and the first voltage output end Vo1 respectively, and the drain electrode of the MOS transistor P6 is electrically connected with the main current mirror unit of the second current mirror unit 2;
the slave current mirror unit of the first current mirror unit 1 is electrically connected to the master current mirror unit of the third current mirror unit 3; the slave current mirror unit of the third current mirror unit 3 and the slave current mirror unit of the second current mirror unit 2 are electrically connected with the master current mirror unit of the fourth current mirror unit 4, respectively, and the slave current mirror unit of the fourth current mirror unit 4 is electrically connected with one end of the capacitor C2;
the first voltage output end Vo1 is electrically connected with one end of the resistor R1; the voltage input end VIN of the voltage clamping unit 5 is configured to input a reference voltage, and the voltage clamping unit 5 clamps the voltage of the first voltage output end Vo1 to the reference voltage; when the other end of the resistor R1 is grounded, the voltage clamping unit 5 clamps the voltage of the second voltage output terminal Vo2 to a second voltage, which is greater than the reference voltage; when the other end of the resistor R1 is connected to a power supply, the voltage clamping unit 5 clamps the voltage of the second voltage output end Vo2 to a third voltage, and the third voltage is smaller than the reference voltage.
The difference value between the second voltage and the reference voltage is not less than the gate-source threshold of the MOS transistor N4, and the difference value between the reference voltage and the third voltage is not less than the source-gate threshold of the MOS transistor P6.
In practical use, when the other end of the resistor R1 is grounded, since the second voltage is greater than the reference voltage, the MOS transistor N4 is turned on, the MOS transistor P6 is turned off, the main current mirror unit of the first current mirror unit 1 generates a current I1, assuming that the reference voltage is Vbias, the current I1 is Vbias/R1, the current I1 is mirrored by the auxiliary current mirror unit of the first current mirror unit 1, the third current mirror unit 3 and the fourth current mirror unit 4 and then input to one end of the capacitor C2, and the other end of the capacitor C2 outputs a compensation current;
when the other end of the resistor R1 is connected with a power supply, because the third voltage is less than the reference voltage, the MOS tube N4 is turned off, the MOS tube P6 is turned on, the second current mirror unit 2 generates a current I2, and if the voltage of the power supply is VDD, the current I2 is (VDD-Vbias)/R1, the current I2 is mirrored by the slave current mirror unit of the second current mirror unit 2 and the fourth current mirror unit 4 and then is input to one end of the capacitor C2, and the other end of the capacitor C2 outputs a compensation current. Therefore, the invention can generate compensation current when the compensation resistor, namely the resistor R1, is connected with the ground in a pull-down mode or a power supply in a pull-up mode, and has stronger applicability.
As shown in fig. 2, in the present embodiment, the voltage clamping unit 5 includes a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor P4, a MOS transistor P5, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3, a resistor R2, and a capacitor C1;
the source electrode of the MOS tube P1 is respectively and electrically connected with the source electrode of the MOS tube P2 and the source electrode of the MOS tube P3; in actual use, the source electrode of the MOS tube P1 is electrically connected with a working power supply;
the drain electrode of the MOS tube P1 is electrically connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2 and the grid electrode of the MOS tube P3 respectively; in actual use, the drain electrode of the MOS tube P1 inputs bias current Ibias;
the drain electrode of the MOS tube P2 is respectively and electrically connected with the source electrode of the MOS tube P4 and the source electrode of the MOS tube P5; the grid electrode of the MOS tube P4 is a first voltage output end Vo1 and is electrically connected with one end of the resistor R1; the drain electrode of the MOS tube P4 is respectively and electrically connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 is respectively and electrically connected with the source electrode of the MOS tube N2 and the source electrode of the MOS tube N3; in actual use, the source electrode of the MOS tube N1 is grounded; in fig. 2, one end of a resistor R1 is electrically connected to one end of a switch S1 and one end of a switch S2, respectively, the other end of the switch S1 is grounded, and the other end of the switch S2 is electrically connected to a power supply;
the grid electrode of MOS pipe P5 is voltage input end VIN, the drain electrode of MOS pipe P5 is connected with the drain electrode of MOS pipe N2, resistance R2 one end and the grid electrode of MOS pipe N3 electricity respectively, the resistance R2 other end is connected with electric capacity C1 one end electricity, electric capacity C1 other end is second voltage output end Vo2, is connected with the drain electrode of MOS pipe P3 and the drain electrode of MOS pipe N3 electricity respectively.
As shown in fig. 3, in the present embodiment, the master current mirror unit of the first current mirror unit 1 includes a MOS transistor P7, and the slave current mirror unit of the first current mirror unit 1 includes a MOS transistor P9; the source electrode of the MOS transistor P7 is electrically connected with the source electrode of the MOS transistor P9, the drain electrode of the MOS transistor P7 is respectively electrically connected with the drain electrode of the MOS transistor N4, the grid electrode of the MOS transistor P7 and the grid electrode of the MOS transistor P9, and the drain electrode of the MOS transistor P9 is electrically connected with the main current mirror unit of the third current mirror unit 3; in actual use, the source electrode of the MOS transistor P7 is electrically connected with a working power supply, when the other end of the resistor R1 is grounded and the MOS transistor N4 is turned on, the MOS transistor P7 generates a current I1, and the current I1 is mirrored through the MOS transistor P9 and then input to the main current mirror unit of the third current mirror unit 3;
the master current mirror unit of the second current mirror unit 2 comprises a MOS transistor N5, and the slave current mirror unit of the second current mirror unit 2 comprises a MOS transistor N7; the drain electrode of the MOS transistor N5 is electrically connected with the drain electrode of the MOS transistor P6, the grid electrode of the MOS transistor N5 and the grid electrode of the MOS transistor N7 respectively, the source electrode of the MOS transistor N5 is electrically connected with the source electrode of the MOS transistor N7, and the drain electrode of the MOS transistor N7 is electrically connected with the main current mirror unit of the fourth current mirror unit 4; when the MOS transistor P6 is turned on, the MOS transistor N5 generates a current I2, and the current I2 is mirrored by the MOS transistor N7 and then input to the main current mirror unit of the fourth current mirror unit 4.
In combination with the above, when the resistor R1 is grounded or connected to a power supply, the voltage clamping unit 5 controls the MOS transistor N4 to be connected or controls the MOS transistor P6 to be connected, so that the first current mirror unit 1 or the second current mirror unit 2 generates a current, the current is finally mirrored by the fourth current mirror unit 4 and then input to the capacitor C2, and the capacitor C2 outputs a compensation current, so that the compensation current can be generated when the resistor R1 is grounded by being pulled down and when the power supply is pulled up, and the applicability is strong.
In addition, when the conventional power management chip is actually used, the working mode of the power management chip needs to be set besides the compensation current. The generation of the compensating current and the setting of the working mode of the existing power management chip are independently set by two different circuits, so that the area of the existing power management chip is large, the circuit structure is complex, and the cost is high.
Based on this, in order to generate the compensation current and set the operation mode of the power management chip on the same circuit, as shown in fig. 4, on the basis of the circuit shown in fig. 3, the slave current mirror unit of the first current mirror unit 1 further includes a MOS transistor P8, and the slave current mirror unit of the second current mirror unit 2 further includes a MOS transistor N6;
the source electrode of the MOS tube P8 is electrically connected with the source electrode of the MOS tube P7, the grid electrode of the MOS tube P8 is electrically connected with the grid electrode of the MOS tube P7, and the drain electrode of the MOS tube P8 is respectively electrically connected with the input end of the phase inverter X1 and the drain electrode of the MOS tube N6; the grid electrode of the MOS transistor N6 is electrically connected with the grid electrode of the MOS transistor N5, and the source electrode of the MOS transistor N6 is electrically connected with the source electrode of the MOS transistor N5.
In practical use, when the resistor R1 is grounded through the switch S1, the current I1 generated by the main current mirror unit of the first current mirror unit 1 is mirrored to the MOS transistor P8, at this time, a high level signal is input to the input terminal of the inverter X1, and a low level signal is output from the output terminal of the inverter X1;
when the resistor R1 is electrically connected with a power supply through the switch S2, the current generated by the second current mirror unit 2 is mirrored onto the MOS transistor N6, so that the MOS transistor N6 is conducted, at the moment, a low level signal is input into the input end of the phase inverter X1, and a high level signal is output from the output end of the phase inverter X1;
therefore, in fig. 4, when the resistor R1 is grounded and connected to a power supply, the inverter X1 will output level signals in two states, and the operating mode of the power management chip can be set according to the level state of the output signal of the inverter X1, for example, when the inverter X1 outputs a low level signal, the power management chip operates in a voltage control mode, and when the inverter X1 outputs a high level signal, the voltage management chip operates in a current operating mode.
In fig. 3 and 4, the master current mirror unit of the third current mirror unit 3 includes a MOS transistor N8, and the slave current mirror unit of the third current mirror unit 3 includes a MOS transistor N9;
the drain electrode of the MOS tube N8 is respectively and electrically connected with the drain electrode of the MOS tube P9, the grid electrode of the MOS tube N8 and the grid electrode of the MOS tube N9; the source electrode of the MOS tube N8 is electrically connected with the source electrode of the MOS tube N9; the drain electrode of the MOS tube N9 is electrically connected with the main current mirror unit of the fourth current mirror unit 4; in actual use, the source of the MOS transistor N8 is grounded.
In fig. 3 and 4, the master current mirror unit of the fourth current mirror unit 4 includes a MOS transistor P10 and a MOS transistor P11, and the slave current mirror unit of the fourth current mirror unit 4 includes a MOS transistor P12 and a MOS transistor P13;
the source electrode of the MOS tube P10 is electrically connected with the source electrode of the MOS tube P12; the drain electrode of the MOS tube P10 is electrically connected with the source electrode of the MOS tube P11, the grid electrode of the MOS tube P10 and the grid electrode of the MOS tube P12 respectively, and the drain electrode of the MOS tube P12 is electrically connected with the source electrode of the MOS tube P13; the drain electrode of the MOS tube P11 is electrically connected with the drain electrode of the MOS tube N9, the drain electrode of the MOS tube N7, the grid electrode of the MOS tube P11 and the grid electrode of the MOS tube P13 respectively, and the drain electrode of the MOS tube P13 is electrically connected with one end of the capacitor C2; in actual use, the source of the MOS transistor P10 is electrically connected to the operating power supply.
In conclusion, the invention can output the compensation current when the resistor R1 is grounded or connected with a power supply, and has stronger applicability; in addition, the invention can also output two level signals in different states according to the grounding and power connection of the resistor R1, and the level signals in the two states can be used for setting the working mode of the power management chip, so that when the invention is applied to the power management chip, the area of the power management chip can be reduced, the cost is reduced, and the circuit structure of the power management chip is simplified.
In light of the foregoing, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims (7)

1. The current compensation circuit for the power management chip is characterized by comprising an MOS tube N4, an MOS tube P6, a voltage clamping unit, a resistor R1, a first current mirror unit and a second current mirror unit; the voltage clamping unit comprises a voltage input end, a first voltage output end and a second voltage output end;
the grid electrode of the MOS tube N4 and the grid electrode of the MOS tube P6 are respectively and electrically connected with the second voltage output end; the drain electrode of the MOS tube N4 is electrically connected with the main current mirror unit of the first current mirror unit; the source electrode of the MOS tube N4 is respectively and electrically connected with the source electrode of the MOS tube P6 and the first voltage output end, and the drain electrode of the MOS tube P6 is electrically connected with the main current mirror unit of the second current mirror unit;
the first voltage output end is electrically connected with one end of the resistor R1; the voltage input end of the voltage clamping unit is configured to input a reference voltage, and the voltage clamping unit clamps the voltage of the first voltage output end to the reference voltage; when the other end of the resistor R1 is grounded, the voltage clamping unit clamps the voltage of the second voltage output end to a second voltage, and the second voltage is greater than the reference voltage; when the other end of the resistor R1 is connected with a power supply, the voltage clamping unit clamps the voltage of the second voltage output end to a third voltage, and the third voltage is smaller than the reference voltage.
2. The current compensation circuit for the power management chip as claimed in claim 1, wherein the voltage clamping unit comprises a MOS transistor P1, a MOS transistor P2, a MOS transistor P3, a MOS transistor P4, a MOS transistor P5, a MOS transistor N1, a MOS transistor N2, a MOS transistor N3, a resistor R2 and a capacitor C1;
the source electrode of the MOS tube P1 is respectively and electrically connected with the source electrode of the MOS tube P2 and the source electrode of the MOS tube P3;
the drain electrode of the MOS tube P1 is electrically connected with the grid electrode of the MOS tube P1, the grid electrode of the MOS tube P2 and the grid electrode of the MOS tube P3 respectively;
the drain electrode of the MOS transistor P2 is respectively and electrically connected with the source electrode of the MOS transistor P4 and the source electrode of the MOS transistor P5; the grid electrode of the MOS tube P4 is a first voltage output end and is electrically connected with one end of the resistor R1; the drain electrode of the MOS tube P4 is respectively and electrically connected with the drain electrode of the MOS tube N1, the grid electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, and the source electrode of the MOS tube N1 is respectively and electrically connected with the source electrode of the MOS tube N2 and the source electrode of the MOS tube N3;
the grid of MOS pipe P5 is the voltage input end, and the drain electrode of MOS pipe P5 is connected with the drain electrode of MOS pipe N2, resistance R2 one end and the grid electricity of MOS pipe N3 respectively, and the resistance R2 other end is connected with electric capacity C1 one end electricity, and the electric capacity C1 other end is second voltage output end, is connected with the drain electrode of MOS pipe P3 and the drain electrode electricity of MOS pipe N3 respectively.
3. The current compensation circuit for a power management chip according to claim 1, further comprising a third current mirror unit, a fourth current mirror unit and a capacitor C2, wherein the slave current mirror unit of the first current mirror unit is electrically connected to the master current mirror unit of the third current mirror unit; the slave current mirror unit of the third current mirror unit and the slave current mirror unit of the second current mirror unit are electrically connected to the master current mirror unit of the fourth current mirror unit, respectively, and the slave current mirror unit of the fourth current mirror unit is electrically connected to one end of the capacitor C2.
4. The current compensation circuit for a power management chip according to claim 3, wherein the master current mirror unit of the first current mirror unit comprises a MOS transistor P7, and the slave current mirror unit of the first current mirror unit comprises a MOS transistor P9; the source electrode of the MOS transistor P7 is electrically connected with the source electrode of the MOS transistor P9, the drain electrode of the MOS transistor P7 is respectively electrically connected with the drain electrode of the MOS transistor N4, the grid electrode of the MOS transistor P7 and the grid electrode of the MOS transistor P9, and the drain electrode of the MOS transistor P9 is electrically connected with the main current mirror unit of the third current mirror unit;
the main current mirror unit of the second current mirror unit comprises an MOS transistor N5, and the slave current mirror unit of the second current mirror unit comprises an MOS transistor N7; the drain electrode of the MOS transistor N5 is respectively and electrically connected with the drain electrode of the MOS transistor P6, the grid electrode of the MOS transistor N5 and the grid electrode of the MOS transistor N7, the source electrode of the MOS transistor N5 is electrically connected with the source electrode of the MOS transistor N7, and the drain electrode of the MOS transistor N7 is electrically connected with the main current mirror unit of the fourth current mirror unit.
5. The current compensation circuit for power management chip according to claim 4, wherein the slave current mirror unit of the first current mirror unit further comprises a MOS transistor P8, and the slave current mirror unit of the second current mirror unit further comprises a MOS transistor N6;
the source electrode of the MOS tube P8 is electrically connected with the source electrode of the MOS tube P7, the grid electrode of the MOS tube P8 is electrically connected with the grid electrode of the MOS tube P7, and the drain electrode of the MOS tube P8 is respectively electrically connected with the input end of the phase inverter X1 and the drain electrode of the MOS tube N6; the grid electrode of the MOS transistor N6 is electrically connected with the grid electrode of the MOS transistor N5, and the source electrode of the MOS transistor N6 is electrically connected with the source electrode of the MOS transistor N5.
6. The current compensation circuit for a power management chip according to claim 4, wherein the master current mirror unit of the third current mirror unit comprises MOS transistor N8, and the slave current mirror unit of the third current mirror unit comprises MOS transistor N9;
the drain electrode of the MOS transistor N8 is respectively and electrically connected with the drain electrode of the MOS transistor P9, the grid electrode of the MOS transistor N8 and the grid electrode of the MOS transistor N9; the source electrode of the MOS tube N8 is electrically connected with the source electrode of the MOS tube N9; the drain electrode of the MOS transistor N9 is electrically connected with the main current mirror unit of the fourth current mirror unit.
7. The current compensation circuit for a power management chip according to claim 6, wherein the master current mirror unit of the fourth current mirror unit comprises a MOS transistor P10 and a MOS transistor P11, and the slave current mirror unit of the fourth current mirror unit comprises a MOS transistor P12 and a MOS transistor P13;
the source electrode of the MOS tube P10 is electrically connected with the source electrode of the MOS tube P12; the drain electrode of the MOS transistor P10 is respectively and electrically connected with the source electrode of the MOS transistor P11, the grid electrode of the MOS transistor P10 and the grid electrode of the MOS transistor P12, and the drain electrode of the MOS transistor P12 is electrically connected with the source electrode of the MOS transistor P13; the drain electrode of the MOS transistor P11 is electrically connected with the drain electrode of the MOS transistor N9, the drain electrode of the MOS transistor N7, the grid electrode of the MOS transistor P11 and the grid electrode of the MOS transistor P13 respectively, and the drain electrode of the MOS transistor P13 is electrically connected with one end of the capacitor C2.
CN202210935209.1A 2022-08-05 2022-08-05 Current compensation circuit for power management chip Active CN115065246B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210935209.1A CN115065246B (en) 2022-08-05 2022-08-05 Current compensation circuit for power management chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210935209.1A CN115065246B (en) 2022-08-05 2022-08-05 Current compensation circuit for power management chip

Publications (2)

Publication Number Publication Date
CN115065246A CN115065246A (en) 2022-09-16
CN115065246B true CN115065246B (en) 2022-11-04

Family

ID=83207856

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210935209.1A Active CN115065246B (en) 2022-08-05 2022-08-05 Current compensation circuit for power management chip

Country Status (1)

Country Link
CN (1) CN115065246B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN208904873U (en) * 2018-09-14 2019-05-24 深圳南云微电子有限公司 A kind of compensation circuit of input voltage sampling
CN111367347A (en) * 2020-05-26 2020-07-03 江苏长晶科技有限公司 Line loss compensation method and circuit of linear voltage stabilizer
CN112448568A (en) * 2019-08-30 2021-03-05 圣邦微电子（北京）股份有限公司 Overvoltage clamping circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN208904873U (en) * 2018-09-14 2019-05-24 深圳南云微电子有限公司 A kind of compensation circuit of input voltage sampling
CN112448568A (en) * 2019-08-30 2021-03-05 圣邦微电子（北京）股份有限公司 Overvoltage clamping circuit
CN111367347A (en) * 2020-05-26 2020-07-03 江苏长晶科技有限公司 Line loss compensation method and circuit of linear voltage stabilizer

Also Published As

Publication number Publication date
CN115065246A (en) 2022-09-16

Similar Documents

Publication Publication Date Title
CN102263916B (en) LNB (Low Noise Block) power supply control circuit, power supply control system and digital set-top box
JPS60211517A (en) High frequency impedance matching controller
CN104991113A (en) Zero cross detection circuit applied to high-frequency switching power supply
CN110875630A (en) Backup switching device and control method thereof
CN101252355A (en) Dynamic frequency dividing circuit operating within limited frequency range
CN101546216A (en) Reset circuit
CN115065246B (en) Current compensation circuit for power management chip
CN114513046A (en) Standby power supply switching circuit and device
US20210204374A1 (en) Adaptive bleeder control method and circuit
CN109818411B (en) Power switch circuit, chip and power supply system suitable for power supply sudden change
US6717784B2 (en) Rush current suppression circuit
TW328588B (en) Semiconductor memory device
US5296760A (en) Voltage translator
CN108847771A (en) Extend the power supply circuit and Expander backboard in PMC chip service life
US20040051587A1 (en) Amplifying circuit with variable load drivability
US20090251124A1 (en) Circuit for the Generation of Two Symmetrical Buses of Tension With Respect to the Negative of the Feeding Tension
CN210670028U (en) Clock intersection point position detection and adjustment circuit
CN109787603B (en) Low-conduction flatness analog switch
CN113447697A (en) Signal detection circuit, signal detection method, touch panel and display device
CN105071637A (en) Output amplitude adjusting circuit of switch power
CN110763994A (en) Automobile switch detection working circuit structure
JPH0440947B2 (en)
CN219041460U (en) Power supply circuit, power supply circuit board and power supply equipment
US11632088B2 (en) Voltage converter and class-D amplifier
CN220553998U (en) Voltage comparator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant