CN210670028U - Clock intersection point position detection and adjustment circuit - Google Patents

Clock intersection point position detection and adjustment circuit Download PDF

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Publication number
CN210670028U
CN210670028U CN201922144561.XU CN201922144561U CN210670028U CN 210670028 U CN210670028 U CN 210670028U CN 201922144561 U CN201922144561 U CN 201922144561U CN 210670028 U CN210670028 U CN 210670028U
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clock
circuit
current
pmos tube
tube
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武鹏斌
张东亮
吕国峰
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Nanjing Derui Zhixin Electronic Technology Co ltd
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Nanjing Derui Zhixin Electronic Technology Co ltd
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Abstract

The utility model discloses a nodical position of clock detects and regulating circuit, including nodical position detection circuitry of clock and the nodical position regulating circuit of clock. The clock intersection point position detection circuit comprises a clock current conversion circuit and a current comparison circuit, wherein the clock current conversion circuit converts the difference of two paths of differential clock signals into differential current signals; the current comparison circuit compares the difference current signal with a reference current and identifies the position of the clock intersection point; the clock intersection position adjusting circuit comprises two paths of adjusting sub-circuits, adjusts the clock intersection to move up or down according to the clock intersection position, and feeds back the adjusted differential output signal to the clock intersection position detecting circuit through the phase inverter. The utility model discloses a circuit make full use of whole clock cycle combines the threshold voltage of sampling switch to in time adjust the nodical position of clock signal according to the condition of actual design circuit, improve clock signal's controllability, optimize the performance of whole circuit.

Description

Clock intersection point position detection and adjustment circuit
Technical Field
The utility model relates to an integrated circuit, concretely relates to nodical position of clock detects and regulating circuit.
Background
In most integrated circuit systems, a clock signal is required to control the operating state thereof. When a fully differential clock signal is required to control the switching on and off of the different channels, it is required that the crossing point of the differential clock signal must be at a certain potential between the power supply and ground, and the position of the crossing point can be adjusted according to the threshold voltage of the switching tube and the requirements of the actual design. As sampling systems become more frequent and have smaller sampling periods, the ratio of the rise time and fall time of the sampling clock in a single sampling period increases, thereby reducing the effective operating time of the single sampling period.
Because the change of the clock signal intersection point position is mostly due to the mismatch of the driving capacities of the PMOS and NMOS, and the intersection point position of the input signal also affects the intersection point position of the generated clock signal, the prior art mostly starts from solving the matching of the driving capacities of the transistors and ensuring the stability of the intersection point position of the input signal. However, due to the limitations of process technology, variations in power supply voltage and temperature, propagation of clock signals in the circuit, and changes in driving capability, the crossing point positions of the clock signals are affected, so that the problem of high or low crossing point positions of the output clock signals cannot be solved only by matching the driving capability of the transistor and ensuring the crossing point positions of the input signals.
SUMMERY OF THE UTILITY MODEL
Utility model purpose: an object of the utility model is to provide a clock nodical position detects and regulating circuit for the driving force of pipe changes along with technology, temperature and mains voltage's change in solving current clock production circuit, the nodical position of clock signal, the restriction of process technology that clock input signal's nodical position influence obtained, influences the defect that the nodical position of clock signal was put such as the influence of mains voltage and temperature and the change of driving force.
The technical scheme is as follows: the utility model provides a clock nodical position detects and regulating circuit, including the nodical position detection circuitry of clock and the nodical position regulating circuit of clock. The clock intersection point position detection circuit comprises a clock current conversion circuit and a current comparison circuit, wherein the clock current conversion circuit is used for converting the difference of two paths of differential clock signals into differential current signals; the current comparison circuit is used for comparing the difference current signal with a reference current and identifying the position of the clock intersection point; the clock intersection position adjusting circuit comprises two paths of adjusting sub-circuits and is used for adjusting the clock intersection to move up or down according to the clock intersection position and feeding back the adjusted differential output signal to the clock intersection position detecting circuit through the phase inverter.
Furthermore, the clock current conversion circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube;
the grid electrodes of the first PMOS tube and the first NMOS tube are connected to be used as a first input end of the clock intersection point position detection circuit; the grid electrodes of the second PMOS tube and the second NMOS tube are connected to be used as a second input end of the clock intersection point position detection circuit;
the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube; the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube and used as an output end of the differential current signal.
Further, the current comparison circuit comprises a current amplifier and a detection capacitor; the positive phase input end of the current amplifier is connected with the output end of the differential current signal; the inverting input end of the current amplifier is connected with a reference power supply, and the reference power supply is grounded; the output end of the current amplifier is grounded through the detection capacitor.
Furthermore, the clock intersection position adjusting circuit comprises a first adjusting sub-circuit and a second adjusting sub-circuit, wherein input ends of the first adjusting sub-circuit and the second adjusting sub-circuit are respectively connected with an output end of the current amplifier, and intersection position adjustment is carried out on the two paths of differential clock signals.
Further, the first regulating sub-circuit comprises a third PMOS tube, a fifth PMOS tube and a third NMOS tube; the third PMOS tube is connected with the fifth PMOS tube in parallel, the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the third PMOS tube and the fifth PMOS tube are used as first feedback nodes; the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube and serves as the input end of the first path of clock signal to be regulated;
the second regulating sub-circuit comprises a fourth PMOS tube, a sixth PMOS tube and a fourth NMOS tube; the fourth PMOS tube and the sixth PMOS tube are connected in parallel, the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as a second feedback node; the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the sixth PMOS tube and serves as the input end of the second path of clock signals to be regulated;
the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the output end of the current amplifier.
Further, the clock crossing point position adjustment circuit further includes a first feedback sub-circuit and a second feedback sub-circuit. The first feedback sub-circuit comprises a first inverter, the input end of the first inverter is connected with a first feedback node, and the output end of the first inverter is connected with the first input end of the clock intersection point position detection circuit; the second feedback sub-circuit comprises a second inverter, the input end of the second inverter is connected with the second feedback node, and the output end of the second inverter is connected with the second input end of the clock crossing point position detection circuit.
Has the advantages that: compared with the prior art, the utility model discloses a circuit detectable and adjustable difference clock signal are nodical, consider the importance of clock intersection to the effective operating time of sampling period, single periodic effective operating time has been increased, make full use of whole clock cycle, combine the threshold voltage of sampling switch, solved because technology, the temperature, the nodical unstable phenomenon of clock intersection that unsatisfactory factors such as mains voltage caused, and can in time adjust the nodical position of clock signal according to the condition of actual design circuit, improve clock signal's controllability, optimize the performance of whole circuit.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a simulation diagram of adjusting the position of the intersection point according to the embodiment of the present invention;
fig. 3 is a simulation diagram of the intersection point adjusting control voltage in the embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the following figures and examples:
the present application provides a clock crossing position detection and adjustment circuit, as shown in fig. 1, including a clock crossing position detection circuit and a clock crossing position adjustment circuit. The clock crossing position detection circuit includes a clock current conversion circuit 101 and a current comparison circuit 102, and the clock current conversion circuit 101 is configured to convert a difference between two differential clock signals into a differential current signal. The current comparison circuit 102 is configured to compare the differential current signal to a reference current to identify a clock crossing location. The clock intersection position adjusting circuit comprises two paths of adjusting sub-circuits 103 and two paths of feedback sub-circuits 104, and is used for adjusting the clock intersection to move up or down according to the clock intersection position, and feeding back the adjusted differential output signal to the clock intersection position detecting circuit through the inverter.
The clock current conversion circuit 101 comprises a first PMOS transistor Mp1A second PMOS transistor Mp2A first NMOS transistor Mn1A second NMOS transistor Mn2；
First PMOS transistor Mp1And a first NMOS transistor Mn1The grid of which is connected with a first input terminal Clkp as a clock crossing point position detection circuit; second PMOS transistor Mp2And a second NMOS transistor Mn2The grid of the first input terminal Clkn is connected with a second input terminal Clkn used as a clock crossing point position detection circuit;
first PMOS transistor Mp1The source electrode of the transistor is connected with the power supply, and the drain electrode of the transistor is connected with the second PMOS tube Mp2A source electrode of (a); second NMOS transistor Mn2The source electrode of the first NMOS tube is grounded, and the drain electrode of the first NMOS tube is connected with the source electrode M of the second NMOS tuben1(ii) a First NMOS transistor Mn1Drain electrode of and the second PMOS transistor Mp2Is connected as an output terminal for the differential current signal.
The current comparison circuit 102 includes a current amplifier and a detection capacitor C1(ii) a The positive phase input end of the current amplifier is connected with the output end of the differential current signal; the inverting input end of the current amplifier is connected with a reference power supply I1Reference power supply I1Grounding; the output end of the current amplifier passes through a detection capacitor C1And (4) grounding.
The two-way regulation sub-circuit 103 comprises a first regulation sub-circuit and a second regulation sub-circuitA segment circuit. The first regulator sub-circuit comprises a third PMOS transistor Mp3The fifth PMOS transistor Mp5And a third NMOS transistor Mn3(ii) a Third PMOS transistor Mp3And a fifth PMOS transistor Mp5In parallel connection, the source electrode is connected with a power supply VCC, the drain electrode is connected with a third NMOS tube Mn3As a first feedback node Clkp 2; third NMOS transistor Mn3The source electrode of the transistor is grounded, and the grid electrode of the transistor is connected with the fifth PMOS tube Mp5Is connected as the input terminal Clkp1 of the first clock signal to be adjusted.
The second regulator sub-circuit comprises a fourth PMOS transistor Mp4Sixth PMOS transistor Mp6And a fourth NMOS transistor Mn4(ii) a Fourth PMOS transistor Mp4And a sixth PMOS transistor Mp6The source electrodes of the NMOS transistors are connected with a power supply VCC in parallel, the drain electrodes of the NMOS transistors are connected with a fourth NMOS transistor M in paralleln4As a second feedback node Clkn 2; fourth NMOS transistor Mn4The source electrode of the PMOS transistor is grounded, and the grid electrode of the PMOS transistor is connected with the sixth PMOS tube Mp6Is connected as an input Clkn1 for the second clock signal to be conditioned.
Third PMOS transistor Mp3Grid and fourth PMOS tube Mp4Is connected with the output end of the current amplifier.
The clock crossing point position adjustment circuit further includes a first feedback sub-circuit and a second feedback sub-circuit. The first feedback sub-circuit comprises a first inverter INV1, the input end of the first inverter INV1 is connected with the first feedback node Clkp2, and the output end of the first inverter INV1 is connected with the first input end Clkp of the clock crossing point position detection circuit; the second feedback sub-circuit comprises a second inverter INV2, an input of the second inverter is connected to the second feedback node Clkn2, and an output is connected to the second input Clkn of the clock crossing position detecting circuit.
The working principle is as follows: it is difficult to accurately measure the position of the clock crossing point because the time width of the clock transition edge is small. Considering that short-circuit current exists when the clock jumps, the position of the intersection point can be determined by utilizing the short-circuit current, and the position information of the intersection point is converted into current information. As shown in FIG. 1, when the clock crossing point positions of Clkp and Clkn are low, M isp1And Mp2Time ratio of conduction Mn1And Mn2Conduction ofIs long and flows through the PMOS transistor Mp1And Mp2Is larger than the current flowing through the NMOS transistor Mn1And Mn2The current of (a); the current difference is passed through a current amplifier to a capacitor C1Charging; similarly, when the position of the intersection point of Clkp and Clkn is higher, M isp1And Mp2Time ratio of conduction Mn1And Mn2Short conduction time, then flows through PMOS transistor Mp1And Mp2Is less than the current flowing through the NMOS transistor Mn1And Mn2The current difference is passed through a current amplifier to a capacitor C1And (4) discharging. Through the above process, the detection of the clock signal intersection position is realized.
When the circuit is used, the input of an external circuit is connected to the first input end and the second input end of the circuit, two paths of differential signals to be detected and adjusted, which are output by the external circuit, are respectively input into the clock intersection position detection and adjustment circuit of the application through the input end Clkp1 of the first path of clock signal to be adjusted and the input end Clkn1 of the second path of clock signal to be adjusted (here, the two paths of differential signals to be detected and adjusted are changed into clock signals Clkp1 and Clkn 1). When the circuit is powered on, when the intersection point positions of clock signals Clkp1 and Clkn1 are high, Clkp2 and Clkn2 respectively pass through the clock intersection point position adjusting circuit and secondary inversion of inverters INV1 and INV2, the intersection point positions of the first input end Clkp and the second input end Clkn signals obtained through feedback are basically consistent with Clkp1 and Clkn1, namely, the circuit is high, and an NMOS transistor M is connected with a power supply, and the power supply is connected with a power supply through a power supply circuit, so that the power supply is highn1And Mn2Turn-on time ratio PMOS transistor Mp1And Mp2Is long and the current flowing through the NMOS is greater than the current flowing through the PMOS, so that the capacitance C is1Discharge so that Mp3And Mp4The driving capability of the tube is enhanced so that the rising time of the clock signal is reduced and the falling time is increased, and the clock crossing point positions of the first feedback node output signal Clkp2 and the second feedback node Clkn2 of the clock crossing point position adjusting circuit are shifted up. The differential output clock signals Clkp2 and Clkn2 are input to inverters INV1 and INV2, respectively, and the position of the intersection of the Clkp and Clkn signals is shifted down below the position of the intersection of the original Clkp1 and Clkn 1. The Clkp and Clkn of the external circuit are used as the input signals of the external circuit, and the output signals of the circuit areSince the positions of the clock signal intersections are low, the Clkp1 and the Clkn1 pass through the above-mentioned detection and adjustment circuit, and the adjustment of the positions of the intersections is completed until the positions of the intersections of the Clkp and the Clkn signals are adjusted to the midpoint.
Similarly, when the intersection positions of the clock signals Clkp1 and Clkn1 are low, the intersection positions of the obtained Clkp and Clkn signals are still low through the clock intersection position adjusting circuit itself and the inversions of the inverters INV1 and INV2, respectively, so the PMOS transistor Mp1And Mp2Is in turn on time ratio of NMOS transistor Mn1And Mn2Has long conduction time and flows through the PMOS transistor Mp1And Mp2Is larger than the current flowing through the NMOS transistor Mn1And Mn2So that the capacitance C is1Charging, resulting in Mp3And Mp4The driving capability of the tube is weakened so that the rising time of the clock signal increases and the falling time decreases, the clock crossing point positions of the first feedback output Clkp2 and the second feedback output Clkn2 of the clock crossing point position adjusting circuit shift down, the crossing point positions of the Clkp and Clkn clock signals shift up through inversion of INV1 and INV2, and the crossing point position is higher than the crossing point positions of Clkp1 and Clkn 1. Clkp and Clkn are used as input signals of an external circuit, output signals of the circuit are Clkp1 and Clkn1, and because the intersection positions of the clock signals at the moment are high, the circuit is circulated for multiple times until the intersection positions of the Clkp and Clkn signals are adjusted to the middle point, and the adjustment of the intersection positions is completed.
As shown in fig. 2, taking the example that the clock crossing positions of the input differential clock signals Clkp1 (solid line in the figure) and Clkn1 (dashed line in the figure) are low, after the adjustment by the clock crossing position detection and adjustment circuit, the clock crossing positions of the adjusted output signals Clkp (solid line in the figure) and Clkn (dashed line in the figure) measured at the first input terminal and the second input terminal are in the middle. After the clock crossing is centered, capacitor C is adjusted as shown in FIG. 31The voltage at the two ends is stable and unchanged.
The above embodiments should be understood as merely illustrative of the present invention and not as limiting the scope of the invention, and after reading the contents of the present invention, the skilled person can make various changes or parameter modifications to the present invention, and these equivalent changes and modifications also fall into the scope of the present invention defined by the claims.

Claims (6)

1. A clock crossing point position detection and adjustment circuit is characterized by comprising a clock crossing point position detection circuit and a clock crossing point position adjustment circuit;
the clock intersection point position detection circuit comprises a clock current conversion circuit and a current comparison circuit, wherein the clock current conversion circuit is used for converting the difference of two paths of differential clock signals into differential current signals; the current comparison circuit is used for comparing the differential current signal with a reference current and identifying the position of a clock intersection point;
the clock intersection position adjusting circuit comprises two paths of adjusting sub-circuits and is used for adjusting the clock intersection to move up or down according to the clock intersection position and feeding back the adjusted differential output signal to the clock intersection position detecting circuit through a phase inverter.
2. The clock crossing position detecting and adjusting circuit of claim 1, wherein the clock current converting circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor;
the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected to be used as a first input end of the clock intersection point position detection circuit; the grid electrodes of the second PMOS tube and the second NMOS tube are connected to be used as a second input end of the clock intersection point position detection circuit;
the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube; the source electrode of the second NMOS tube is grounded, and the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube; and the drain electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube and is used as the output end of the differential current signal.
3. The clock crossing location detection and adjustment circuit of claim 2 wherein the current comparison circuit comprises a current amplifier and a detection capacitor;
the non-inverting input end of the current amplifier is connected with the output end of the differential current signal; the inverting input end of the current amplifier is connected with a reference power supply, and the reference power supply is grounded; the output end of the current amplifier is grounded through the detection capacitor.
4. The clock crossing position detecting and adjusting circuit of claim 3, wherein the clock crossing position adjusting circuit comprises a first adjusting sub-circuit and a second adjusting sub-circuit, input terminals of the first adjusting sub-circuit and the second adjusting sub-circuit are respectively connected with an output terminal of the current amplifier, and crossing position adjustment is performed on two paths of differential clock signals.
5. The clock crossing position detecting and adjusting circuit of claim 4, wherein the first adjusting sub-circuit comprises a third PMOS transistor, a fifth PMOS transistor and a third NMOS transistor;
the third PMOS tube is connected with the fifth PMOS tube in parallel, the source electrode of the third PMOS tube is connected with a power supply, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the third PMOS tube and the fifth PMOS tube are used as a first feedback node; the source electrode of the third NMOS tube is grounded, and the grid electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube and serves as the input end of the first path of clock signal to be regulated;
the second regulating sub-circuit comprises a fourth PMOS tube, a sixth PMOS tube and a fourth NMOS tube;
the fourth PMOS tube is connected with the sixth PMOS tube in parallel, the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and serves as a second feedback node; the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the sixth PMOS tube and serves as the input end of the second path of clock signal to be regulated;
and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the output end of the current amplifier.
6. The clock crossing position detection and adjustment circuit of claim 5, wherein the clock crossing position adjustment circuit further comprises a first feedback sub-circuit and a second feedback sub-circuit;
the first feedback sub-circuit comprises a first inverter, the input end of the first inverter is connected with a first feedback node, and the output end of the first inverter is connected with the first input end of the clock crossing point position detection circuit;
the second feedback sub-circuit comprises a second inverter, the input end of the second inverter is connected with a second feedback node, and the output end of the second inverter is connected with the second input end of the clock crossing point position detection circuit.
CN201922144561.XU 2019-12-04 2019-12-04 Clock intersection point position detection and adjustment circuit Active CN210670028U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201922144561.XU CN210670028U (en) 2019-12-04 2019-12-04 Clock intersection point position detection and adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201922144561.XU CN210670028U (en) 2019-12-04 2019-12-04 Clock intersection point position detection and adjustment circuit

Publications (1)

Publication Number Publication Date
CN210670028U true CN210670028U (en) 2020-06-02

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Application Number Title Priority Date Filing Date
CN201922144561.XU Active CN210670028U (en) 2019-12-04 2019-12-04 Clock intersection point position detection and adjustment circuit

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