CN116054797A - Low-power-consumption reset circuit with voltage return difference - Google Patents
Low-power-consumption reset circuit with voltage return difference Download PDFInfo
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- CN116054797A CN116054797A CN202211687837.9A CN202211687837A CN116054797A CN 116054797 A CN116054797 A CN 116054797A CN 202211687837 A CN202211687837 A CN 202211687837A CN 116054797 A CN116054797 A CN 116054797A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
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Abstract
The invention relates to a reset circuit, in particular to a low-power-consumption reset circuit with voltage return difference. It is characterized by that it includes VDD, VOUT, branch I, branch II and current mirror. The VDD is adaptively connected with a current mirror. The first branch circuit comprises a MOS tube N2, the MOS tube N2 is a depletion type MOS tube, the drain electrode of the MOS tube N2 is connected with the current mirror in an adaptive mode, the grid electrode of the MOS tube N2 is grounded, the source electrode of the MOS tube N2 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded. The second branch comprises an MOS tube N3, the drain electrode of the MOS tube N3 is an A point, the drain electrode of the MOS tube N3 is connected with the current mirror in an adaptive mode, the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N2, and the grid electrode of the MOS tube N3 forms a reference voltage VREF. The point A is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the VOUT. The divider resistor is connected with the VDD in an adaptive manner to form a sampling voltage. The voltage dividing resistor is connected with a return difference switch, and the return difference switch is connected with the point A in an adaptive manner. The reset circuit has simple structure and lower power consumption.
Description
Technical Field
The invention relates to a reset circuit, in particular to a low-power-consumption reset circuit which does not need an additional reference current circuit and can automatically generate a charged return difference of a reference current.
Background
It is known in the integrated circuit industry that there are basically reset circuits in the chip. The reset circuit has a plurality of types, for example, a resistor-capacitor sampling input voltage is used for controlling an inverter or a schmitt trigger to turn over to give a control signal, but when the level is close to the turning-over voltage, the anti-interference capability of power supply disturbance is poor, and the error trigger signal is easily given by repeated oscillation. To stabilize this function, a return difference switch voltage is required, and a comparator is typically used as a reset circuit.
As shown in fig. 1, the conventional reset circuit with a return difference switch needs a reference voltage VREF circuit, voltage of VCC collected by voltage dividing resistors R1, R2 and R3 is compared with VREF by a comparator U1, when VDD voltage is low, VOUT output is low, INV1 output is high, NM1 is turned on, R3 is shorted, the ratio of the voltage dividing resistor connected in series by R2 and R3 to the voltage dividing ratio of R1 to VDD is low, so that a higher VDD voltage is needed to make FB terminal larger than VREF, when FB voltage is larger than VREF voltage, VOUT output is high, INV1 output is low, NM1 is turned off, R3 is released, the voltage dividing resistor connected in series by R2 and R3 and R1 normally divide the voltage of VDD, and FB divided value is low when FB divided value is smaller than VREF. However, this reset circuit requires additional VREF and an operating current IB1 to operate, resulting in a complex structure of the entire circuit and large static power consumption.
Disclosure of Invention
The invention aims to solve the technical problem of providing a low-power-consumption reset circuit with a voltage return difference, which is simple in structure and low in power consumption.
In order to solve the problems, the following technical scheme is provided:
the low-power-consumption reset circuit with the voltage return difference switch and the voltage return difference is characterized by comprising VDD, VOUT, a first branch, a second branch and a current mirror; the VDD is adaptively connected with the current mirror and is used for providing a driving voltage for the current mirror. The first branch circuit comprises a MOS tube N2, the MOS tube N2 is a depletion type MOS tube, the drain electrode of the MOS tube N2 is connected with the current mirror in an adaptive mode, the grid electrode of the MOS tube N2 is grounded, the source electrode of the MOS tube N2 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded. The second branch comprises a MOS tube N3, the drain electrode of the MOS tube N3 is an A point, the drain electrode of the MOS tube N3 is connected with the current mirror in an adaptive mode, the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N2, and the grid electrode of the MOS tube N3 forms a reference voltage VREF. The point A is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the VOUT. The voltage dividing resistor is connected with the VDD in an adaptive manner to form a sampling voltage, the sampling voltage is connected with the grid electrode of the MOS tube N3, the sampling voltage is compared with the reference voltage VREF, when the sampling voltage is larger than the reference voltage VREF, the MOS tube N3 is conducted, and when the sampling voltage is smaller than the reference voltage VREF, the MOS tube N3 is closed. The voltage dividing resistor is connected with a return difference switch, and the return difference switch is connected with the point A in an adaptive manner.
The current mirror comprises a MOS tube P1 and a MOS tube P2, wherein the source electrode of the MOS tube P1 and the source electrode of the MOS tube P2 are connected with the VDD, the grid electrode of the MOS tube P1 is connected with the drain electrode of the MOS tube P1 and the grid electrode of the MOS tube P2, the drain electrode of the MOS tube P1 is connected with the drain electrode of the MOS tube N2, and the drain electrode of the MOS tube P2 is connected with the drain electrode of the MOS tube N3.
The divider resistor comprises a resistor R2, a resistor R3 and a resistor R4, VDD is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the grid electrode of the MOS tube N3 and one end of the resistor R3 respectively, the other end of the resistor R3 is connected with one end of the resistor R4, and the other end of the resistor R4 is grounded. The return difference switch is positioned between two ends of the resistor R4. And one end of R2 connected with R3 forms the sampling voltage.
The return difference switch comprises a MOS tube N1, one end of a resistor R4 connected with a resistor R3 is connected with the drain electrode of the MOS tube N1, the other end of the resistor R4 is connected with the source electrode of the MOS tube N1, and the grid electrode of the MOS tube N1 is connected with the point A.
By adopting the scheme, the method has the following advantages:
because the branch I of the low-power-consumption reset circuit with the voltage return difference comprises the MOS tube N2, the MOS tube N2 is a depletion type MOS tube, the drain electrode of the MOS tube N2 is connected with the current mirror in an adaptive manner, the grid electrode of the MOS tube N2 is grounded, the source electrode of the MOS tube N2 is connected with one end of the resistor R1, the other end of the resistor R1 is grounded, the branch II comprises the MOS tube N3, the drain electrode of the MOS tube N3 is an A point, the drain electrode of the MOS tube N3 is connected with the current mirror in an adaptive manner, the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N2, the grid electrode of the MOS tube N3 forms a reference voltage VREF, the A point is connected with the input end of the inverter INV1, the output end of the inverter INV1 is connected with the VOUT, the voltage dividing resistor is connected with the grid electrode of the MOS tube N3 in an adaptive manner, the sampling voltage is compared with the reference voltage VREF, when the sampling voltage is larger than the reference voltage VREF, the MOS tube N3 is turned on, when the sampling voltage is smaller than the reference voltage VREF, the voltage is turned off, the voltage is connected with the voltage return difference switch, and the switch is connected with the point A. The reset circuit utilizes the grid electrode of the depletion type MOS tube N2 to generate reference current IREF through grounding and self-bias, and utilizes the VDD and the divider resistor to generate reference voltage VREF, so that the reset circuit can work without additional reference voltage VREF and working current IB1, the structure of the whole circuit is greatly simplified, the self-bias generation of the reference current does not need to consume the VDD, and the power consumption of the whole circuit is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a reset circuit with a return difference switch in the background art;
FIG. 2 is a schematic diagram of a low power reset circuit with voltage return difference according to the present invention;
FIG. 3 is a voltage comparison diagram of VDD and VOUT in the low power reset circuit with voltage return difference according to the present invention;
fig. 4 is a waveform diagram showing the current flowing through DS with temperature change at the GS ground of the MOS transistor N2 in the low power consumption reset circuit with voltage return difference according to the present invention;
FIG. 5 is a graph of VGS along with temperature change, wherein the ends of a MOS tube N2 and a MOS tube N3GD in the low-power-consumption reset circuit with the voltage return difference are connected, and the ends of the MOS tube N2 and the MOS tube N3GD to S are connected with each other through an S ground;
FIG. 6 is a graph of the temperature change of VR1 in the low power reset circuit with voltage return difference of the present invention;
fig. 7 is a simulated waveform diagram of a low power reset circuit with voltage return difference of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the accompanying drawings.
As shown in fig. 2, the low power reset circuit with voltage return difference of the present invention includes VDD, VOUT, branch one, branch two and a current mirror. The VDD is adaptively connected with the current mirror and is used for providing a driving voltage for the current mirror. The first branch circuit comprises a MOS tube N2, the MOS tube N2 is a depletion type MOS tube, the drain electrode of the MOS tube N2 is connected with the current mirror in an adaptive mode, the grid electrode of the MOS tube N2 is grounded, the source electrode of the MOS tube N2 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded. The second branch comprises a MOS tube N3, the drain electrode of the MOS tube N3 is an A point, the drain electrode of the MOS tube N3 is connected with the current mirror in an adaptive mode, and the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N2. The current mirror comprises a MOS tube P1 and a MOS tube P2, wherein the source electrode of the MOS tube P1 and the source electrode of the MOS tube P2 are connected with the VDD, the grid electrode of the MOS tube P1 is connected with the drain electrode of the MOS tube P1 and the grid electrode of the MOS tube P2, the drain electrode of the MOS tube P1 is connected with the drain electrode of the MOS tube N2, and the drain electrode of the MOS tube P2 is connected with the drain electrode of the MOS tube N3. The reference current IREF is generated by utilizing the grid electrode grounding self-bias of the depletion type MOS transistor N2, and the current mirror copies the reference current IREF into a branch II.
The point A is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the VOUT to form an output port.
The grid electrode of the MOS tube N3 forms a reference voltage VREF. The voltage dividing resistor is connected with the VDD in an adaptive manner to form a sampling voltage, the sampling voltage is connected with the grid electrode of the MOS tube N3, the sampling voltage is compared with the reference voltage VREF, when the sampling voltage is larger than the reference voltage VREF, the MOS tube N3 is conducted, and when the sampling voltage is smaller than the reference voltage VREF, the MOS tube N3 is closed. The voltage dividing resistor is connected with a return difference switch, and the return difference switch is connected with the point A in an adaptive manner. The divider resistor comprises a resistor R2, a resistor R3 and a resistor R4, VDD is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the grid electrode of the MOS tube N3 and one end of the resistor R3 respectively, the other end of the resistor R3 is connected with one end of the resistor R4, the other end of the resistor R4 is grounded, and one end of the resistor R2 connected with the resistor R3 forms the sampling voltage. The voltage dividing resistor is connected with a return difference switch, the return difference switch comprises a MOS tube N1, one end of a resistor R4 connected with a resistor R3 is connected with the drain electrode of the MOS tube N1, the other end of the resistor R4 is connected with the source electrode of the MOS tube N1, and the grid electrode of the MOS tube N1 is connected with the point A.
In this embodiment, the MOS transistor P1 and the MOS transistor P2 are PMOS transistors, and the MOS transistor N1, the MOS transistor N2, and the MOS transistor N3 are NMOS transistors.
The MOS transistor N2 is a depletion type NMOS transistor, and the depletion type MOS transistor has the characteristics that when VGS is smaller than 0V, the current flowing through DS gradually decreases until the MOS transistor is completely turned off along with the voltage reduction of VGS, and the depletion type NMOS transistor G is grounded and self-biased to generate current. As shown in fig. 4, the source resistor R1 of the MOS transistor N2 can adjust the current, and then provides the current to the second branch through the current mirror, so as to provide the reference current IREF.
As shown in fig. 5, the VGS curve of the MOS transistor N3 decreases with increasing temperature, the VGS curve of the depletion type MOS transistor N2 increases with increasing temperature, and the current generated by the MOS transistor N2 increases with increasing temperature when the temperature is high, so the voltage of the resistor R1 increases with increasing temperature, as shown in fig. 6. The gate terminal of the MOS transistor N3 is the reference voltage VREF, vref=vgs N3 +V R1 The grid electrode of the MOS tube N2 is grounded and V R1 Equal to VGS N2 . I.e., the reference voltage VREF is approximately equal to the sum of the upper end of fig. 5 and the voltage value of fig. 6. VGS (gas guide System) N3 Is of negative temperature coefficient, VGS N2 (i.e., VR 1) is a positive temperature coefficient, and the sizes of the MOS transistor N2 and the MOS transistor N3 and the size of the resistor R1 are properly adjusted, so that the added voltage values of the two transistors at different temperatures are basically consistent. If the reset voltage needs to be flexibly controlled, the resistor R1 is externally arranged, and the reset voltage can be adjusted only by adjusting the voltage value of the reference voltage VREF through adjusting the size of the resistor R1.
When the VDD voltage rises from low during operation, the reference voltage VREF is low, the point a is high, the MOS transistor N1 is turned on, the resistor R4 is shorted, the ratio of the voltage dividing resistor connected in series by the resistor R3 and the resistor R4 to the voltage dividing ratio of the resistor R2 to VDD is low, and a higher VDD voltage is required to turn on the MOS transistor N3. When VDD > (1+r2/R3) ×vref, MOS transistor N3 is turned on, point a is pulled down by MOS transistor N3, VOUT output is high, when VDD voltage drops from high, MOS transistor N3 is turned on, point a is pulled down, the resistor set formed by series connection of resistor R3 and resistor R4 normally divides VDD with resistor R2, and when VDD < (1+r2/(r3+r4)), VOUT output is low, as shown in fig. 3. In fig. 3, VUP represents a rising on voltage, VDW drops off voltage, and the two voltage signals are lower than VUP in comparison with VDD voltage, resulting in voltage hysteresis.
As shown in FIG. 7, the low power reset circuit with voltage return difference of the present invention has VDD >2.9V, VOUT is high, and when VDD <2.45V, VOUT output is low.
The application of the reset circuit is extremely wide, and almost all chips are used. The low-power-consumption reset circuit with the voltage return difference has a simple structure, can flexibly control reset voltage through an external resistor and can be integrated internally, has high portability, is not influenced by process, temperature and VDD voltage basically, and can be applied to various circuits needing reset functions.
Claims (4)
1. The low-power-consumption reset circuit with the voltage return difference is characterized by comprising VDD, VOUT, a first branch, a second branch and a current mirror; the VDD is adaptively connected with the current mirror and is used for providing driving voltage for the current mirror; the first branch comprises a MOS tube N2, the MOS tube N2 is a depletion type MOS tube, the drain electrode of the MOS tube N2 is connected with the current mirror in an adaptive manner, the grid electrode of the MOS tube N2 is grounded, the source electrode of the MOS tube N2 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded; the second branch comprises a MOS tube N3, the drain electrode of the MOS tube N3 is an A point, the drain electrode of the MOS tube N3 is connected with the current mirror in an adaptive manner, the source electrode of the MOS tube N3 is connected with the source electrode of the MOS tube N2, and the grid electrode of the MOS tube N3 forms a reference voltage VREF; the point A is connected with the input end of the inverter INV1, and the output end of the inverter INV1 is connected with the VOUT; the voltage dividing resistor is adaptively connected with the VDD to form a sampling voltage, the sampling voltage is connected with the grid electrode of the MOS tube N3, the sampling voltage is compared with the reference voltage VREF, when the sampling voltage is larger than the reference voltage VREF, the MOS tube N3 is conducted, and when the sampling voltage is smaller than the reference voltage VREF, the MOS tube N3 is closed; the voltage dividing resistor is connected with a return difference switch, and the return difference switch is connected with the point A in an adaptive manner.
2. The low power reset circuit of claim 1 wherein said current mirror comprises a MOS transistor P1 and a MOS transistor P2, wherein the source of the MOS transistor P1 and the source of the MOS transistor P2 are connected to said VDD, the gate of the MOS transistor P1 is connected to the drain thereof and the gate of the MOS transistor P2, the drain of the MOS transistor P1 is connected to the drain of the MOS transistor N2, and the drain of the MOS transistor P2 is connected to the drain of the MOS transistor N3.
3. The low power consumption reset circuit with voltage return difference according to claim 1 or 2, wherein the voltage dividing resistor comprises a resistor R2, a resistor R3 and a resistor R4, VDD is connected with one end of the resistor R2, the other end of the resistor R2 is respectively connected with the gate of the MOS transistor N3 and one end of the resistor R3, the other end of the resistor R3 is connected with one end of the resistor R4, and the other end of the resistor R4 is grounded; the return difference switch is positioned between two ends of the resistor R4; and one end of R2 connected with R3 forms the sampling voltage.
4. The low power consumption reset circuit with voltage return difference as set forth in claim 3, wherein said return difference switch comprises a MOS transistor N1, one end of a resistor R4 connected to a resistor R3 is connected to a drain electrode of the MOS transistor N1, the other end of the resistor R4 is connected to a source electrode of the MOS transistor N1, and a gate electrode of the MOS transistor N1 is connected to said point a.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211687837.9A CN116054797A (en) | 2022-12-28 | 2022-12-28 | Low-power-consumption reset circuit with voltage return difference |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211687837.9A CN116054797A (en) | 2022-12-28 | 2022-12-28 | Low-power-consumption reset circuit with voltage return difference |
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| CN116054797A true CN116054797A (en) | 2023-05-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116700458A (en) * | 2023-08-09 | 2023-09-05 | 深圳奥简科技有限公司 | Voltage monitoring reset circuit and electronic equipment |
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| CN1409489A (en) * | 2001-09-18 | 2003-04-09 | 精工电子有限公司 | Electronic equipment with CMOS circuit |
| CN102347753A (en) * | 2010-07-26 | 2012-02-08 | 三美电机株式会社 | Reset circuit and apparatus including the reset circuit |
| CN107066003A (en) * | 2016-12-30 | 2017-08-18 | 西南技术物理研究所 | Low-power-consumptioreference reference voltage source |
| CN109474263A (en) * | 2018-12-17 | 2019-03-15 | 上海贝岭股份有限公司 | A kind of electrification reset circuit |
| JP2019062473A (en) * | 2017-09-27 | 2019-04-18 | ラピスセミコンダクタ株式会社 | Power-on reset circuit and semiconductor device |
| EP3905522A1 (en) * | 2020-04-29 | 2021-11-03 | ams International AG | Power on reset circuit and integrated circuit including the same |
| CN114285396A (en) * | 2021-12-27 | 2022-04-05 | 上海贝岭股份有限公司 | Power-on reset circuit and electronic equipment |
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2022
- 2022-12-28 CN CN202211687837.9A patent/CN116054797A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1409489A (en) * | 2001-09-18 | 2003-04-09 | 精工电子有限公司 | Electronic equipment with CMOS circuit |
| CN102347753A (en) * | 2010-07-26 | 2012-02-08 | 三美电机株式会社 | Reset circuit and apparatus including the reset circuit |
| CN107066003A (en) * | 2016-12-30 | 2017-08-18 | 西南技术物理研究所 | Low-power-consumptioreference reference voltage source |
| JP2019062473A (en) * | 2017-09-27 | 2019-04-18 | ラピスセミコンダクタ株式会社 | Power-on reset circuit and semiconductor device |
| CN109474263A (en) * | 2018-12-17 | 2019-03-15 | 上海贝岭股份有限公司 | A kind of electrification reset circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116700458A (en) * | 2023-08-09 | 2023-09-05 | 深圳奥简科技有限公司 | Voltage monitoring reset circuit and electronic equipment |
| CN116700458B (en) * | 2023-08-09 | 2024-01-26 | 深圳奥简科技有限公司 | Voltage monitoring reset circuit and electronic equipment |
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