CN210604769U

CN210604769U - Undervoltage detection circuit with zero static power consumption

Info

Publication number: CN210604769U
Application number: CN201920604958.XU
Authority: CN
Inventors: 庄在龙
Original assignee: Nanjing Xinnaite Semiconductor Co ltd
Current assignee: Nanjing Xinnaite Semiconductor Co ltd
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2020-05-22
Anticipated expiration: 2029-04-29

Abstract

The utility model provides an undervoltage detection circuit with zero static power consumption, which comprises a PMOS tube PM1, a PM2 and a PM 3; NMOS transistors NM1 and NM 2; inverters I1 and I2; the capacitor CP and the power supply voltage VDD can be applied to an SOC chip or an analog chip and provide a reset signal in the power-down process. The utility model discloses there is not static consumption under normal operating condition, and power supply voltage's threshold value can be set for very little, can use in the low-voltage environment.

Description

Undervoltage detection circuit with zero static power consumption

Technical Field

The utility model belongs to integrated circuit design field, concretely relates to under-voltage detection circuit of zero static consumption.

Background

As shown in fig. 1, in a conventional undervoltage detection circuit, three series resistors are used to generate a divided voltage, a positive input terminal of a comparator is connected to a divided voltage point, a negative input terminal of the comparator is connected to a reference voltage, and an output of the comparator is shaped by a phase inverter to generate an undervoltage detection signal, which is effective when the voltage level is low. Meanwhile, the signal end is connected with the grid electrode of the NMOSNMOS tube, and the drain electrode of the NMOS tube is connected with the second voltage dividing point of the voltage dividing resistor. The source end of the NMOS tube and one end of the third resistor are grounded together. When the detection signal changes to low level, the NMOS tube is disconnected, and rises through the first voltage division point, so that a hysteresis effect is generated.

The resistor and the comparator of the common power-down detection circuit structure consume direct current power consumption in normal work, and the static power consumption of the resistor voltage division part can be reduced by improving the resistor, but the area of the resistor is inevitably increased, so that the common power-down detection circuit structure is not suitable for low-power consumption application. Also, in applications where the supply voltage is relatively low, the reference voltage and the operating state of the comparator are difficult to guarantee, which makes this configuration less suitable for low voltage applications.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem that exists among the prior art, the utility model provides a zero-power consumption just can be in the undervoltage detection circuit who uses in the low-voltage environment. The technical scheme of the utility model as follows:

an under-voltage detection circuit with zero static power consumption comprises PMOS tubes PM1, PM2 and

PM 3; NMOS transistors NM1 and NM 2; inverters I1 and I2; a capacitor CP and a supply voltage VDD;

PM1 connected to power supply voltage VDD and output voltage Vp;

CP, in series with PM 1;

the CMOS inverter 1 is formed by connecting power supply voltages VDD, PM2 and NM1 in series and outputs a voltage Va;

the CMOS inverter 2 is formed by connecting power supply voltages VDD, PM3 and NM2 in series, and inputs a voltage Va;

the secondary inverter is formed by connecting I1 and I2 in series and outputs an under-voltage control signal;

the CMOS inverter 1, the CMOS inverter 2 and the secondary inverter are sequentially connected in series to output an under-voltage control signal.

Specifically, the gate (G) of the PM1 is connected to the drain (D) and to ground via the capacitor CP, and the source (S) of the PM1 is connected to the power supply voltage VDD; the capacitor CP and the PM1 provide a voltage Vp, and a gate (G) of the PM1 is connected with a source (S) of the PM 2; the gate (G) of the PM2 is connected with the gate (G) of the NM1 and the power supply voltage VDD, and the drain (D) of the PM2 is connected with the drain (D) of the NM 1; the grid (G) of the PM3 is connected with the grid (G) of the NM2, the drain (D) of the PM3 is connected with the drain (D) of the NM2, and the source (S) of the PM3 is connected with the power supply voltage VDD; the drain (D) PM3 gate (G) of the PM2 is connected; the source (S) of NM1 and the source (S) of NM2 are grounded; the drain of the PM3 is connected with the input end of an inverter I1; the output end of the inverter I1 is connected with the input end of the inverter I2, and the inverter I2 outputs a logic control output signal s _ uvb.

Further, the PM1 threshold voltage is VTHP; and Vp is VDD-VTHP.

Based on the technical scheme, the utility model discloses the technological effect that can realize does:

1. the utility model discloses an under-voltage detection circuit of zero static consumption, because the detection path is the turn-off state all the time, when consequently under the normal operating condition, no static consumption.

2. The utility model discloses an under-voltage detection circuit of zero static power consumption, VDD's threshold VDDTH depends on PM2 in addition, and NM 1's size, very little that can set for accords with low-voltage application environment, can use under the low pressure condition.

Drawings

FIG. 1 is a schematic diagram of a conventional common undervoltage detection circuit

Fig. 2 is the schematic diagram of the undervoltage detection circuit with zero static power consumption of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings, and it is to be understood that the described embodiments are merely illustrative of some, but not all, embodiments of the invention.

As shown in fig. 2, the present embodiment provides an under-voltage detection circuit with zero static power consumption, which includes PMOS transistors PM1, PM2, and PM 3; NMOS transistors NM1 and NM 2; inverters I1 and I2; a capacitor CP and a supply voltage VDD.

PM1 connected to power supply voltage VDD and output voltage Vp;

CP, in series with PM 1;

Specifically, the gate (G) of PM1 is connected to the drain (D) and to ground via capacitor CP, and the source (S) of PM1 is connected to power supply voltage VDD. Capacitor CP and PM1 provide voltage Vp, and the gate (G) of PM1 is connected to the source (S) of PM 2. The gate (G) of PM2 is connected to the gate (G) of NM1 and to the power supply voltage VDD, and the drain (D) of PM2 is connected to the drain (D) of NM 1. The gate (G) of PM3 is connected to the gate (G) of NM2, the drain (D) is connected to the drain (D) of NM2, and the source (S) is connected to the power supply voltage VDD. The drain (D) of PM2 is connected to the PM3 gate (G). The source (S) of NM1 and the source (S) of NM2 are grounded. The drain of PM3 is connected to the input of inverter I1. The output terminal of the inverter I1 is connected to the input terminal of the inverter I2, and the inverter I2 outputs a logic control output signal s _ uvb.

Preferably, the PM1 threshold voltage is VTHP, Vp-VDD-VTHP.

Based on the above structure, the utility model discloses an under-voltage detection circuit of zero static power consumption, when supply voltage VDD was very high, PM1 regarded as diode connection device, and the voltage difference of its source (S) and grid (G) is close a threshold voltage, namely Vp ═ VDD-VTHP; at this time, the gate (G) of PM2 is connected to the power supply voltage VDD and is in an off state, and the gate (G) of NM1 is connected to the power supply voltage VDD and is in an on state, so Va is at a low potential. Va is changed into high potential after passing through inverters of PM3 and NM2, and then is shaped by two stages of inverters I1 and I2, finally a control signal s _ uvb output by I2 is high level, the chip works normally, and no static power consumption exists.

When VDD begins to drop, because capacitor CP keeps electric charge, no bleeder path exists, voltage Vp keeps, when VDD drops to VDDTH, namely the source voltage of PM2 is higher than the grid voltage by more than one threshold value, PM2 begins to conduct, when VDD further drops, the driving capability of PM2 is larger than that of NM1, Va is reversed, the inverter formed by PM3 and NM2 is reversed, through shaping of I1 and I2, finally s _ uvb output by I2 becomes low level, and the chip enters an undervoltage state. The switching point of s _ uvb is related to the size selection of PM2 and NM1, and when Ids, PM2 > Ids, NM1, Va is switched from low voltage to high voltage, wherein

The size of PM2 and NM1 can be adjusted to meet the voltage trip point requirement at low voltages. The capacitance CP is chosen depending on the time of charge storage, the coupling effect of the parasitic capacitance, the larger the area allows the better.

The utility model discloses an under-voltage detection circuit of zero static consumption utilizes electric capacity CP's charge storage function, after VDD descends to settlement threshold point VDDTH, produces the under-voltage logic signal of chip, because the detection access is the turn-off state all the time, consequently normal operating condition, no static consumption, VDDTH depends on PM2 and NM 1's size in addition, very little being applicable to low-voltage application environment that can set for.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims

1. The undervoltage detection circuit with zero static power consumption is characterized by comprising PMOS tubes PM1, PM2 and PM 3; NMOS transistors NM1 and NM 2; inverters I1 and I2; a capacitor CP and a supply voltage VDD;

PM1 connected to power supply voltage VDD and output voltage Vp;

CP, in series with PM 1;

2. The brown-out detection circuit with zero static power consumption of claim 1, comprising a supply voltage VDD; the grid (G) and the drain (D) of the PM1 are connected and grounded through a capacitor CP, and the source (S) of the PM1 is connected with a power supply voltage VDD; the capacitor CP and the PM1 provide a voltage Vp, and a gate (G) of the PM1 is connected with a source (S) of the PM 2; the gate (G) of the PM2 is connected with the gate (G) of the NM1 and the power supply voltage VDD, and the drain (D) of the PM2 is connected with the drain (D) of the NM 1; the grid (G) of the PM3 is connected with the grid (G) of the NM2, the drain (D) of the PM3 is connected with the drain (D) of the NM2, and the source (S) of the PM3 is connected with the power supply voltage VDD; the drain (D) PM3 gate (G) of the PM2 is connected; the source (S) of NM1 and the source (S) of NM2 are grounded; the drain of the PM3 is connected with the input end of an inverter I1; the output end of the inverter I1 is connected with the input end of the inverter I2, and the inverter I2 outputs a logic control output signal s _ uvb.

3. The brown-out detection circuit with zero static power consumption of claim 1, wherein the PM1 threshold voltage is VTHP; and Vp is VDD-VTHP.