CN209948734U - Automatic load detection circuit - Google Patents
Automatic load detection circuit Download PDFInfo
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- CN209948734U CN209948734U CN201920864128.0U CN201920864128U CN209948734U CN 209948734 U CN209948734 U CN 209948734U CN 201920864128 U CN201920864128 U CN 201920864128U CN 209948734 U CN209948734 U CN 209948734U
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- 238000001514 detection method Methods 0.000 title claims abstract description 54
- 238000007599 discharging Methods 0.000 claims description 8
- 238000012031 short term test Methods 0.000 abstract description 4
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model provides an automatic load detection circuitry is applied to charge-discharge circuit system, automatic load detection circuitry includes first resistance, second resistance, first current source, second current source, first transistor, second transistor, third transistor, comparator and logic control module. Compared with the prior art, the utility model discloses an automatic load detection circuit can short-term test, and circuit area is less, circuit structure is simple easily extends.
Description
Technical Field
The utility model relates to an electronic circuit technical field especially relates to an automatic load detection circuit.
Background
At present, mobile devices such as smart phones, wearable devices, electric tools, unmanned aerial vehicles and the like are used more and more. The charging and discharging circuit in the mobile device is an important component. The charging and discharging circuit generates output voltage according to a certain voltage value through an internal circuit, the output voltage of the charging and discharging circuit is used for charging and discharging a load, the automatic load detection circuit is a basic circuit of the charging and discharging circuit, and the automatic load detection circuit is beneficial to improving the reliability of the charging and discharging circuit.
The automatic load detection circuit of the related art generally detects a voltage change across a load using an analog circuit to determine whether the load is normally charged or the load is pulled out.
However, in the related art, the analog circuit is directly used for logic judgment, which results in more circuits using the comparator, larger circuit area, and longer detection time.
Therefore, it is necessary to provide a new automatic load detection circuit to solve the above problems.
SUMMERY OF THE UTILITY MODEL
To the not enough of above prior art, the utility model provides a can short-term test, and circuit area is less, circuit structure is simple easily the automatic load detection circuit who extends.
In order to solve the above technical problem, the present invention provides an automatic load detection circuit applied to a charging/discharging circuit system, wherein the automatic load detection circuit comprises a first resistor, a second resistor, a first current source, a second current source, a first transistor, a second transistor, a third transistor, a comparator and a logic control module;
the first end of the first resistor, the input end of the first current source, the input end of the second current source, the gate of the first transistor and the positive input end of the comparator are all connected to a bias power supply voltage;
a second end of the first resistor is respectively connected to the drain of the second transistor and the gate of the third transistor;
a first end of the second resistor is connected to the ground, and a second end of the second resistor is connected to the drain of the third transistor;
an output end of the first current source is respectively connected to a source electrode of the first transistor, a source electrode of the third transistor and a negative input end of the comparator and is used as a load voltage signal input end;
the output end of the second current source is connected to the drain electrode of the first transistor;
the grid electrode of the second transistor is connected to the second input end of the logic control module and serves as a reset signal input end, and the source electrode of the second transistor is connected to the ground;
the output end of the comparator is connected to the first input end of the logic control module;
a third input end of the logic control module is used as a load state signal input end;
a first output end of the logic control module is used as a first control signal output end;
and a second output end of the logic control module is used as a second control signal output end.
Preferably, the first transistor and the second transistor are both NMOS transistors, and the third transistor is a PMOS transistor.
Preferably, the current magnitude of the first current source and the second current source can be adjusted.
Preferably, the logic control module is a digital circuit.
Preferably, the logic control module receives the detection signal output by the comparator, the reset signal and the load state signal to perform logic operation, and generates the first control signal and the second control signal for controlling load charging according to an operation result.
Preferably, when the reset signal is at a high level, the automatic load detection circuit is set to a zero reset state, the zero reset state is that the voltage value of the load voltage signal is equal to the bias power supply voltage, and the first control signal, the second control signal and the load state signal are all at a low level.
Compared with the prior art, the utility model discloses an automatic load detection circuit is through adopting first current source with the circuit structure of second current source, the circuit selects the electric current size according to the function, thereby makes automatic load detection circuit can the short-term test load state, and passes through logic control module realizes that load state detects through logical operation, thereby automatic load detection circuit's circuit structure is simple easily extends, and its required analogue means is less to make circuit area less.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings:
fig. 1 is a circuit structure diagram of the automatic load detection circuit of the present invention;
FIG. 2 is a voltage time response plot of a critical node for a load pull-out condition during the load charging process of FIG. 1;
FIG. 3 is a graph of voltage time response of a critical node of FIG. 1 where the load is charged to full.
Detailed Description
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.
The embodiments/examples set forth herein are specific embodiments of the present invention and are presented for illustrative purposes only, and are not intended to be construed as limitations on the scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
Referring to fig. 1, the present invention provides an automatic load detection circuit 100, wherein the automatic load detection circuit 100 includes a first resistor R1, a second resistor R2, a first current source I1, a second current source I2, a first transistor M1, a second transistor M2, a third transistor M3, a comparator COMP, and a logic control module LOG.
The automatic load detection circuit 100 is generally applied to a charging circuit system or a complete machine, and is used for rapidly controlling an internal circuit of the charging circuit system or the complete machine when a load is plugged in or pulled out, so that the load is charged and a corresponding circuit is rapidly charged or in a standby state.
Specifically, the circuit structure of the automatic load detection circuit 100 is as follows:
a first end of the first resistor R1, an input end of the first current source I1, an input end of the second current source I2, a gate of the first transistor M1, and a positive input end of the comparator COMP are all connected to a bias supply voltage BAT.
A second end of the first resistor RI is respectively connected to the drain of the second transistor M2 and the gate of the third transistor M3.
A first end of the second resistor R2 is connected to ground GND, and a second end of the second resistor R2 is connected to the drain of the third transistor M3.
An output end of the first current source I1 is respectively connected to a source electrode of the first transistor M1, a source electrode of the third transistor M3 and a negative input end of the comparator COMP, and serves as a load voltage signal Vo input end;
the output terminal of the second current source I2 is connected to the drain of the first transistor M1.
The gate of the second transistor M2 is connected to the second input terminal of the logic control module LOG and serves as the input terminal of the reset signal Pulld _ vth, and the source of the second transistor M2 is connected to the ground GND.
An output end of the comparator COMP is connected to a first input end of the logic control module LOG.
A third input terminal of the logic control module LOG serves as an input terminal of a load state signal EN _ vocls.
A first output terminal of the logic control module LOG serves as a first control signal Load _ on output terminal.
And a second output end of the logic control module LOG is used as a second control signal Load _ in output end.
In the embodiment, on the basis of ensuring the circuit performance, all the NMOS transistors and PMOS transistors are unified in size, so that layout optimization is realized, and the layout area is reduced, thereby facilitating the expansion of application. Specifically, the first transistor M1 and the second transistor M2 are both NMOS transistors, and the third transistor M3 is a PMOS transistor. Wherein the first transistor M1 and the second transistor M2 are the same size. Of course, without limitation, a designer may also perform a customized design for each MOS transistor according to performance and layout design requirements.
In this embodiment, the logic control module LOG receives the detection signal Load _ det, the reset signal Pulld _ vth, and the Load state signal EN _ vocls output by the comparator COMP to perform a logic operation, and generates the first control signal Load _ on and the second control signal Load _ in for controlling the Load charging according to an operation result. The logic control module LOG is a digital circuit. The logic control module LOG is realized by adopting a digital circuit, has the characteristics of small number of devices and small layout area, and can reduce the power consumption of the circuit. Of course, without limitation, the logic control module LOG may be implemented by an analog circuit or a digital-analog hybrid circuit.
When the reset signal Pulld _ vth is at a high level, the automatic Load detection circuit 100 is set to a reset state, the reset state is that the voltage value of the Load voltage signal Vo is equal to the bias power supply voltage BAT, and the first control signal Load _ on, the second control signal Load _ in, and the Load state signal EN _ vocls are all at a low level.
When the reset signal Pulld _ vth is at a low level, the threshold voltage of the first transistor M1 is set to vth, and when the voltage value of the load voltage signal Vo is greater than the voltage value BAT-vth and less than the bias power voltage BAT, i.e., BAT-vth < Vo < BAT, the first current source I1 is turned on, and the first transistor M1 is turned off, so that the second current source I2 is turned off. That is to say only the first current source I1 supplies current to the circuit. When the voltage value of the load voltage signal Vo is smaller than the voltage value BAT-vth, the first transistor M1 is turned on, so that the second current source I2 is turned on, that is, the first current source I1 and the second current source I2 are both turned on and simultaneously supply current to the circuit. The load is generally a capacitive device including a capacitor, so that the current supply is increased, and the circuit structure can reduce the detection time of the automatic load detection circuit 100. In the related art circuit, the comparator is generally used to determine when to turn on or off the current source, and compared with the automatic load detection circuit 100 that only uses the first transistor M1 for control, the related art circuit has many devices, is complex in circuit, and has a large circuit area.
In this embodiment, the current magnitudes of the first current source I1 and the second current source I2 are both adjustable. The adjustable first current source I1 and the adjustable second current source I2 are used for facilitating the design and the use of the circuit according to the specific circuit, and the automatic load detection circuit 100 can be optimized to adjust the detection time and the power consumption.
The operation principle of the automatic load detection circuit 100 is as follows:
at the beginning, the automatic load detection circuit 100 is powered on, in this embodiment, the power supply voltage of the automatic load detection circuit 100 is 5V, and the voltage value of the bias power supply voltage BAT is BAT.
Referring to fig. 2, when a Load is inserted, the circuit state of the automatic Load detection circuit 100 is that the voltage value of the Load voltage signal Vo is smaller than the bias power voltage BAT, the detection signal Load _ det output by the comparator COMP is at a high level, and the first control signal Load _ on, the second control signal Load _ in, and the Load state signal EN _ vocls output by the logic control module LOG are all at a high level. The automatic Load detection circuit 100 starts to charge the Load, and at this time, the comparator COMP outputs a detection signal Load _ det at a low level, the Load state signal EN _ vocls is cleared, and the second control signal Load _ in goes low.
When a Load is pulled out, the Load state signal EN _ vocls becomes low level, the reset signal Pulld _ vth is triggered to become high level, the automatic Load detection circuit 100 enters the zero clearing reset state, the Load voltage is set to be low level, the detection signal Load _ det is high level, the Load voltage is charged and boosted to the bias power supply voltage BAT, the detection signal Load _ det is converted into low level, and the first control signal Load _ on is converted into low level.
Referring to fig. 3, when the Load charging is completed, the Load state signal EN _ vocls becomes low level, the reset signal Pulld _ vth is triggered to become high level, the automatic Load detection circuit 100 enters the reset state, the Load voltage is set to low level, the detection signal Load _ det is high level, the Load voltage is charged and boosted to the bias power supply voltage BAT, the first control signal Load _ on is kept at high level, and the second control signal Load _ in is kept at low level.
Compared with the prior art, the utility model discloses an automatic load detection circuit is through adopting first current source with the circuit structure of second current source, the circuit selects the electric current size according to the function, thereby makes automatic load detection circuit can the short-term test load state, and passes through logic control module realizes that load state detects through logical operation, thereby automatic load detection circuit's circuit structure is simple easily extends, and its required analogue means is less to make circuit area less.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and those skilled in the art should understand that modifications or equivalent substitutions made on the present invention without departing from the spirit and scope of the present invention should be included in the scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (6)
1. An automatic load detection circuit is applied to a charging and discharging circuit system and is characterized by comprising a first resistor, a second resistor, a first current source, a second current source, a first transistor, a second transistor, a third transistor, a comparator and a logic control module;
the first end of the first resistor, the input end of the first current source, the input end of the second current source, the gate of the first transistor and the positive input end of the comparator are all connected to a bias power supply voltage;
a second end of the first resistor is respectively connected to the drain of the second transistor and the gate of the third transistor;
a first end of the second resistor is connected to the ground, and a second end of the second resistor is connected to the drain of the third transistor;
an output end of the first current source is respectively connected to a source electrode of the first transistor, a source electrode of the third transistor and a negative input end of the comparator and is used as a load voltage signal input end;
the output end of the second current source is connected to the drain electrode of the first transistor;
the grid electrode of the second transistor is connected to the second input end of the logic control module and serves as a reset signal input end, and the source electrode of the second transistor is connected to the ground;
the output end of the comparator is connected to the first input end of the logic control module;
a third input end of the logic control module is used as a load state signal input end;
a first output end of the logic control module is used as a first control signal output end;
and a second output end of the logic control module is used as a second control signal output end.
2. The automatic load detection circuit of claim 1, wherein the first transistor and the second transistor are both NMOS transistors and the third transistor is a PMOS transistor.
3. The automatic load detection circuit of claim 1, wherein the first current source and the second current source are adjustable in current magnitude.
4. The automatic load detection circuit of claim 1, wherein the logic control module is a digital circuit.
5. The automatic load detection circuit of claim 1, wherein the logic control module receives the detection signal outputted from the comparator, the reset signal and the load status signal to perform a logic operation, and generates the first control signal and the second control signal for controlling the charging of the load according to the operation result.
6. The automatic load detection circuit according to claim 1, wherein when the reset signal is at a high level, the automatic load detection circuit is set to a clear reset state, the clear reset state is a state in which a voltage value of the load voltage signal is equal to the bias supply voltage, and the first control signal, the second control signal, and the load state signal are all at a low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920864128.0U CN209948734U (en) | 2019-06-06 | 2019-06-06 | Automatic load detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920864128.0U CN209948734U (en) | 2019-06-06 | 2019-06-06 | Automatic load detection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN209948734U true CN209948734U (en) | 2020-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920864128.0U Withdrawn - After Issue CN209948734U (en) | 2019-06-06 | 2019-06-06 | Automatic load detection circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110165743A (en) * | 2019-06-06 | 2019-08-23 | 深圳市思远半导体有限公司 | Automatic load detection circuit and automatic load detection method |
| CN112345867A (en) * | 2020-11-13 | 2021-02-09 | 昂宝电子（上海）有限公司 | Apparatus and method for load detection |
-
2019
- 2019-06-06 CN CN201920864128.0U patent/CN209948734U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110165743A (en) * | 2019-06-06 | 2019-08-23 | 深圳市思远半导体有限公司 | Automatic load detection circuit and automatic load detection method |
| CN110165743B (en) * | 2019-06-06 | 2024-02-23 | 深圳市思远半导体有限公司 | Automatic load detection circuit and automatic load detection method |
| CN112345867A (en) * | 2020-11-13 | 2021-02-09 | 昂宝电子（上海）有限公司 | Apparatus and method for load detection |
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Granted publication date: 20200114 Effective date of abandoning: 20240223 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20200114 Effective date of abandoning: 20240223 |