CN109959817B - Undervoltage detection circuit applicable to low-voltage environment - Google Patents
Undervoltage detection circuit applicable to low-voltage environment Download PDFInfo
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- CN109959817B CN109959817B CN201910354502.7A CN201910354502A CN109959817B CN 109959817 B CN109959817 B CN 109959817B CN 201910354502 A CN201910354502 A CN 201910354502A CN 109959817 B CN109959817 B CN 109959817B
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- 238000001514 detection method Methods 0.000 title claims abstract description 24
- 239000013256 coordination polymer Substances 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 230000003068 static effect Effects 0.000 abstract description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
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Abstract
The invention provides an undervoltage detection circuit applicable to a low-voltage environment, which comprises a PMOS tube PM1; NMOS transistors NM1 and NM2; inverters I1 and I2; one end of the capacitor CP is connected with the power supply voltage VDD, and the other end of the capacitor CP is connected with the source end of the NM2, wherein the NM2 is a low threshold NMOS tube. The invention can be applied in low voltage environment and has no static power consumption in normal working state.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to an undervoltage detection circuit applicable to a low-voltage environment.
Background
As shown in fig. 1, in a conventional undervoltage detection circuit structure, three resistors are connected in series to generate a divided voltage, a positive input terminal of a comparator is connected to a divided voltage point, a negative input terminal of the comparator is connected to a reference voltage, and an output of the comparator is shaped by an inverter to generate an undervoltage detection signal and is effective at a low level. Meanwhile, the signal end is connected with the grid electrode of the NMOS tube, and the drain electrode of the NMOS tube is connected with the second voltage dividing point of the voltage dividing resistor. The source end of the NMOS tube and one end of the third resistor are commonly grounded. When the detection signal is changed into a low level, the NMOS tube is disconnected and is raised through a first voltage division point, so that a hysteresis effect is generated.
The resistor and the comparator of the common power-down detection circuit structure consume direct current power consumption in normal operation, and the static power consumption of the resistor voltage division part can be reduced by improving the resistor, but the resistance area is inevitably increased, so that the resistor and the comparator are not suitable for low-power consumption application. Also, in applications where the supply voltage is relatively low, the reference voltage and the operating state of the comparator are difficult to guarantee, which makes this structure less suitable for low voltage applications.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a zero-power undervoltage detection circuit which can be applied in a low-voltage environment. The technical scheme of the invention is as follows:
An under-voltage detection circuit applicable to a low-voltage environment, comprising: PMOS tube PM1; NMOS transistors NM1 and NM2; inverters I1 and I2; a capacitor CP and a power supply voltage VDD;
PM1, which is connected with a power supply voltage VDD and outputs a voltage VP;
NM2, input voltage VP;
NM1, NM2, output voltage VQ;
CP, one end of which is connected with the power supply voltage VDD and the other end of which is respectively connected with NM1 and NM2 in series;
The second-stage inverter is formed by connecting I1 and I2 in series, inputs a voltage VP signal and outputs an undervoltage control signal;
the PM1 is respectively connected with the NM2 and the secondary inverter in series;
The NM1, NM2 and the secondary inverter are sequentially connected in series;
the NM2 employs a low threshold NMOS device.
Specifically, the gate (G) of the PM1 is grounded, the source (S) is connected to the power supply voltage VDD, the drain (D) of the PM1 is connected to the drain of the NM2, and is connected to the input terminal of the inverter I1; the source electrode (S) of the NM1 is grounded, and the grid electrode (G) is connected with the drain electrode (D) and is commonly connected with the source electrode (S) of the NM 2; the grid electrode (G) of the NM2 is grounded, the source electrode (S) is connected with one end of a capacitor CP, and the other end of the capacitor CP is connected with a power supply voltage VDD; the output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs an undervoltage control signal s_ uvb.
Further, the typical threshold voltage of the NM2 is 300-500 mV.
Based on the technical scheme, the invention has the following technical effects:
1. the invention is suitable for undervoltage detection application in low voltage environment, the voltage turning point of the power supply voltage VDD depends on the size selection of PM1 and NM2, and can be determined by simulation, and the turning point is approximately near the threshold voltage of PMOS, thus being suitable for low voltage application.
2. The undervoltage detection circuit applicable to the low-voltage environment has the advantages that when the undervoltage detection circuit works normally, the power supply voltage VDD is high, the grid source voltage of the NM1 is only slightly higher than the ground potential, the grid source voltage of the NM2 is negative voltage, the cut-off is further facilitated, and the access has no static power consumption.
Drawings
FIG. 1 is a schematic diagram of a conventional under-voltage detection circuit;
FIG. 2 is a schematic diagram of an under-voltage detection circuit applicable to a low-voltage environment.
Detailed Description
The following description of the present invention will be made with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention.
As shown in fig. 2, the present embodiment provides an undervoltage detection circuit applicable to a low voltage environment, including a PMOS tube PM1; NMOS transistors NM1 and NM2; inverters I1 and I2; a capacitor CP and a supply voltage VDD.
PM1, which is connected with a power supply voltage VDD and outputs a voltage VP;
NM2, input voltage VP;
NM1, NM2, output voltage VQ;
CP, one end of which is connected with the power supply voltage VDD and the other end of which is respectively connected with NM1 and NM2 in series;
The second-stage inverter is formed by connecting I1 and I2 in series, inputs a voltage VP signal and outputs an undervoltage control signal;
PM1 is respectively connected with NM2 and a secondary inverter in series;
NM1, NM2 and the two-stage inverter are sequentially connected in series;
NM2 employs a low threshold NMOS device.
Specifically, the gate (G) of PM1 is grounded, the source (S) is connected to the power supply voltage VDD, the drain (D) of PM1 is connected to the drain of NM2, and is connected to the input of the inverter I1. The source (S) of NM1 is grounded, and the gate (G) is connected to the drain (D) and commonly connected to the source (S) of NM 2. The gate (G) of NM2 is grounded, the source (S) is connected to one end of the capacitor CP, and the other end of the capacitor CP is connected to the power supply voltage VDD. The output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs an undervoltage control signal s_ uvb.
Preferably, the typical threshold voltage of NM2 is 300-500 mV.
Based on the above structure, the invention is suitable for undervoltage detection application in low voltage environment, when the power supply voltage VDD is at high level, PM1 is conducted, VP potential is equal to the power supply potential, the grid electrode (G) of NM2 is grounded, the source electrode (S) voltage is the grid source voltage of NM1, and because no direct current flows, the grid source voltage of NM1 is only slightly higher than ground potential (depending on leakage current and subthreshold working state of NM 1), and at the moment, the grid source voltage of NM2 is negative voltage, which is more helpful to cut off, thereby ensuring that a channel has no static power consumption. The voltage difference between the power supply voltage VDD and ground is approximated across the capacitor CP. NM1 and NM2 employ low threshold NMOS devices with typical threshold voltages of 400 mV; so s_ uvb is high and the chip works normally.
When the power supply voltage VDD falls, VP follows the power supply voltage VDD, VQ is kept low, and when the power supply voltage VDD reaches around the threshold value of PM1, PM1 gradually goes into an off state, VP and VQ gradually go into a high-resistance state. When the power supply voltage VDD further drops and reaches the inversion voltage, the voltage of the VQ approaches to the negative voltage due to the charge holding effect of the capacitor CP and the fact that the VP and VQ paths have no charge discharging paths, at this time, the source and drain of the NM1 are exchanged, the gate and source voltages are equal and are completely turned off, and the gate and source voltage of the NM2 has a voltage difference, and due to the low threshold device, when the VQ reaches-400 mv, the NM2 is turned on, the VP is pulled down to a low potential, even the negative voltage, and after the VP is shaped by I1 and I2, the output s_ uvb is a low potential, and an under-voltage detection signal is provided.
The undervoltage detection circuit applicable to the low-voltage environment has the advantages that the voltage inversion point of the power supply voltage VDD depends on the size selection of PM1 and NM2 and can be determined by simulation, but the inversion point is approximately near the PMOS threshold voltage, and the undervoltage detection circuit is suitable for low-voltage application. The common NMOS tube and PMOS have a small difference in threshold value, so that the detection circuit is difficult to trigger, and NM2 adopts a low-threshold device, so that the undervoltage detection circuit can be triggered after VDD is reduced to a certain extent.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.
Claims (2)
1. An undervoltage detection circuit for use in a low voltage environment, comprising: PMOS tube PM1; NMOS transistors NM1 and NM2; inverters I1 and I2; a capacitor CP and a power supply voltage VDD;
PM1, which is connected with a power supply voltage VDD and outputs a voltage VP;
NM2, input voltage VP;
NM1, NM2, output voltage VQ;
CP, one end of which is connected with the power supply voltage VDD and the other end of which is respectively connected with NM1 and NM2 in series;
The second-stage inverter is formed by connecting I1 and I2 in series, inputs a voltage VP signal and outputs an undervoltage control signal;
the PM1 is respectively connected with the NM2 and the secondary inverter in series;
The NM1, NM2 and the secondary inverter are sequentially connected in series;
the NM2 adopts a low-threshold NMOS device;
The grid electrode (G) of the PM1 is grounded, the source electrode (S) is connected with the power supply voltage VDD, the drain electrode (D) of the PM1 is connected with the drain electrode of the NM2, and the drain electrode is connected with the input end of the inverter I1; the source electrode (S) of the NM1 is grounded, and the grid electrode (G) is connected with the drain electrode (D) and is commonly connected with the source electrode (S) of the NM 2; the grid electrode (G) of the NM2 is grounded, the source electrode (S) is connected with one end of a capacitor CP, and the other end of the capacitor CP is connected with a power supply voltage VDD; the output end of the inverter I1 is connected with the input end of the inverter I2, and the output end of the inverter I2 outputs an undervoltage control signal s_ uvb.
2. The brown-out detection circuit according to claim 1, wherein the typical threshold voltage of NM2 is 300-500 mV.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910354502.7A CN109959817B (en) | 2019-04-29 | 2019-04-29 | Undervoltage detection circuit applicable to low-voltage environment |
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| CN201910354502.7A CN109959817B (en) | 2019-04-29 | 2019-04-29 | Undervoltage detection circuit applicable to low-voltage environment |
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| CN109959817A CN109959817A (en) | 2019-07-02 |
| CN109959817B true CN109959817B (en) | 2024-05-10 |
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| CN113849029B (en) * | 2021-09-26 | 2022-08-26 | 电子科技大学 | Under-voltage detection circuit of self-biased reference source |
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