CN201774453U - Power supply voltage detection circuit of switching power supply - Google Patents
Power supply voltage detection circuit of switching power supply Download PDFInfo
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- CN201774453U CN201774453U CN2010205116478U CN201020511647U CN201774453U CN 201774453 U CN201774453 U CN 201774453U CN 2010205116478 U CN2010205116478 U CN 2010205116478U CN 201020511647 U CN201020511647 U CN 201020511647U CN 201774453 U CN201774453 U CN 201774453U
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Abstract
The utility model discloses a power supply voltage detection circuit of a switching power supply. The power supply voltage detection circuit adopts the structure that an inverting input terminal of a differential amplifier is connected with a power supply voltage sampling point through a second switch and is connected with a first output terminal through a first switch, and a non-inverting input terminal of the differential amplifier is connected with a reference voltage circuit; the input terminal of the reference voltage circuit is connected with a reference voltage calibration circuit; the input terminal of a logic control circuit, the grid electrode of the first switch and the control signal input terminal of the differential amplifier are connected with a logic control signal, and the output terminal of the logic control circuit is connected with the grid electrode of the second switch; and the logic control circuit controls the multiplexing of the differential amplifier during reference voltage calibration and voltage detection through the first switch and the second switch. By virtue of the embodiment of the utility model, the detection precision of power supply voltage can be improved.
Description
Technical field
The utility model relates to the switch power technology field, particularly relates to a kind of voltage detection circuit of Switching Power Supply.
Background technology
In some electronic systems, when supply voltage dropped to certain set point, it is unstable that the work of circuit can become, and may produce misoperation.Given this, the service voltage that need provide voltage detection circuit to come testing circuit, when service voltage dropped to certain set point, testing circuit output control signal made system reset, avoids under low-pressure state misoperation taking place.
With reference to Fig. 1, be the voltage detection circuit figure of the Switching Power Supply of prior art.Described circuit comprises: resistor voltage divider circuit 11, comparator 12 and reference voltage circuit 13.Wherein, described resistor voltage divider circuit 11 comprises first resistance R 11 and second resistance R 12.
In conjunction with shown in Figure 1, supply voltage VDD obtains voltage INPUT through the dividing potential drop of first resistance R 11 and second resistance R 12, the inverting input of input comparator 12; The in-phase input end of comparator 12 meets the reference voltage V REF of reference voltage circuit 13 outputs.The operation principle of this circuit is: when the negative input voltage INPUT of comparator 12 was higher than homophase input voltage VREF, the output OUTPUT of comparator 12 was a low level; When the negative input voltage INPUT of comparator 12 was lower than homophase input voltage VREF, the output OUTPUT of comparator 12 was a high level.
In the foregoing circuit, because INTPUT voltage obtains by first resistance R 11 and second resistance R, 12 dividing potential drops by supply voltage VDD, so can the sample variation of vdd voltage of INPUT.Simultaneously, reference voltage V REF does not change with supply voltage VDD, therefore can realize the detection to supply voltage VDD according to the logic level change of the OUTPUT of comparator 12 outputs.Concrete, foregoing circuit can produce different logic control signals when mains voltage variations arrives certain set point, finish the detection to supply voltage.
But in the existing testing circuit, the reference voltage V REF that comparator 12 receives is produced by independent reference voltage circuit 13.Consider in the components and parts manufacturing process to produce deviation, and such deviation may be bigger between the different circuit, simultaneously, this deviation still produces at random.Therefore, existing testing circuit has certain deviation, so accuracy is not very high.Require less system for the supply voltage error range, in the certain precision claimed range, comparator 12 can accurately not detect the variation of supply voltage in the system, causes disabler.
The utility model content
In view of this, the purpose of this utility model is to provide a kind of voltage detection circuit of Switching Power Supply, can improve the accuracy of detection of supply voltage.
The utility model embodiment provides a kind of voltage detection circuit of Switching Power Supply, comprising:
The inverting input of differential amplifier connects the supply voltage sampled point by second switch, and the in-phase input end of described differential amplifier connects reference voltage circuit, and the inverting input of described differential amplifier connects first output by first switch;
The input termination reference voltage calibration circuit of described reference voltage circuit;
The grid of the input of logic control circuit, described first switch and the signal input end of described differential amplifier connect logic control signal, the grid of the described second switch of output termination of described logic control circuit;
Described logic control circuit is controlled described differential amplifier multiplexing when reference voltage calibration and the voltage detecting by described first switch and second switch.
Preferably, described circuit also comprises resistor voltage divider circuit;
Described resistor voltage divider circuit comprises first divider resistance and second divider resistance; The positive termination supply voltage of described first divider resistance, the negative terminal of first divider resistance connects the anode of second divider resistance, the negativing ending grounding of second divider resistance;
The common port of described first divider resistance and second divider resistance is described supply voltage sampled point.
Preferably, described differential amplifier is the high-gain amplifier that difference is imported single-ended output.
Preferably, described differential amplifier comprises:
The transistorized source electrode of the one PMOS, the transistorized source electrode of the 2nd PMOS, the transistorized source electrode of the 3rd PMOS connect supply voltage jointly; The one PMOS transistor drain connects the positive pole of current source, the minus earth of current source; Transistorized grid of the one PMOS and drain electrode short circuit, the transistorized grid of a PMOS connects transistorized grid of the 2nd PMOS and the transistorized grid of the 3rd PMOS; The 2nd PMOS transistor drain connects transistorized source electrode of the 4th PMOS and the transistorized source electrode of the 5th PMOS; The transistorized grid of the 4th PMOS is the inverting input of differential amplifier, and the transistorized grid of the 5th PMOS is the in-phase input end of differential amplifier; The 4th PMOS transistor drain connects the drain electrode of second nmos pass transistor, the drain and gate short circuit of second nmos pass transistor, the source ground of second nmos pass transistor; The 5th PMOS transistor drain connects the drain electrode of the 3rd nmos pass transistor, and the grid of the 3rd nmos pass transistor connects the grid of second nmos pass transistor, the source ground of the 3rd nmos pass transistor; The 3rd PMOS transistor drain connects the drain electrode of the grid and the 4th nmos pass transistor of first nmos pass transistor, and the 3rd PMOS transistor drain also connects second input of NOR gate and the negative pole of electric capacity; The positive pole of electric capacity connects the drain electrode of the 6th nmos pass transistor through the 3rd resistance, and first end of the grid of the 6th nmos pass transistor and NOR gate together connects logic control signal; The grid of the source electrode of the 6th nmos pass transistor and the 4th nmos pass transistor together connects the drain electrode of the 3rd nmos pass transistor; The grid of the 4th nmos pass transistor connects the grid of the 5th nmos pass transistor, the source ground of the source electrode of the 4th nmos pass transistor and the 5th nmos pass transistor; The drain electrode of first nmos pass transistor connects supply voltage, and the source electrode of first nmos pass transistor connects the drain electrode of the 5th nmos pass transistor, and the common ends of the two is as first output of differential amplifier; The input of the output termination not gate of NOR gate, the output of not gate is as second output of differential amplifier.
Preferably, multiplexing be specially of described differential amplifier when reference voltage calibration and voltage detecting: described differential amplifier carries out the function conversion between unit gain amplifying circuit and voltage comparator.
Preferably, described logic control circuit is a not gate.
Preferably, described first switch and/or second switch are nmos pass transistor.
Preferably, described reference voltage calibration circuit is used for according to the deviation between reference voltage initial value and the default reference voltage desired value, and the reference voltage that described reference voltage circuit is exported to described differential amplifier is calibrated;
Wherein, described reference voltage initial value is the output voltage of described differential amplifier when being in unit gain amplifying circuit mode of operation.
According to the specific embodiment that the utility model provides, the utility model discloses following technique effect:
In the described circuit of the utility model embodiment, logic control circuit realizes that by first switch and second switch control differential amplifier multiplexing when reference voltage calibration and the voltage detecting differential amplifier carries out function conversion between unit gain amplifying circuit and voltage comparator.When the difference amplifier is in unit gain amplifying circuit pattern, obtain the reference voltage initial value by measuring its output end voltage, the reference voltage that in-phase input end receives is calibrated, offset the test error that the input offset voltage of differential amplifier brings.For differential amplifier, the value of reference voltage is adjustable very accurate, can improve the accuracy that supply voltage detects, and then the circuit that makes the utility model provide can be applicable to the system that the supply voltage accuracy of detection is had relatively high expectations.
Description of drawings
Fig. 1 is the voltage detection circuit figure of the Switching Power Supply of prior art;
Fig. 2 is the voltage detection circuit figure of the Switching Power Supply of the utility model embodiment;
Fig. 3 is the differential amplifier circuit structure chart of the utility model embodiment.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, the utility model is described in further detail below in conjunction with the drawings and specific embodiments.
In view of this, the purpose of this utility model is to provide a kind of voltage detection circuit of Switching Power Supply, can improve the accuracy of detection of supply voltage.
With reference to Fig. 2, be the voltage detection circuit figure of the Switching Power Supply of the utility model embodiment.Described circuit comprises: resistor voltage divider circuit 21, differential amplifier 22, reference voltage circuit 23, reference voltage calibration circuit 24, logic control circuit 25 and first switch 26, second switch 27.
Described resistor voltage divider circuit 21 is connected between supply voltage VDD and the ground; The output of described resistor voltage divider circuit 21 connects the inverting input of differential amplifier 22 as supply voltage sampled point A by second switch 27.
The input of the output termination reference voltage circuit 23 of described reference voltage calibration circuit 24, the in-phase input end of the output termination differential amplifier 22 of described reference voltage circuit 23.
Described first switch 26 is connected between first output of the inverting input of differential amplifier 22 and differential amplifier 22.
The signal input end of the grid of the input of described logic control circuit 25, described first switch 26 and differential amplifier 22 meets logic control signal CTL, the grid of the output termination second switch 27 of described logic control circuit 25.
Described logic control circuit 25 is by the described differential amplifier 22 of described first switch 26 and second switch 27 controls multiplexing when reference voltage calibration and the voltage detecting.Wherein, multiplexing be specially of described differential amplifier 22 when reference voltage calibration and voltage detecting: described differential amplifier 22 carries out the function conversion between unit gain amplifying circuit and voltage comparator.
Concrete, in conjunction with shown in Figure 2, the grid of described first switch 26 meets logic control signal CTL, and the grid of described second switch 27 meets logic control signal CTLB through described logic control circuit 25.Wherein, CTL is a pair of opposite logic control signal with CTLB, and when CTL was high level, CTLB was a low level; When CTL was low level, CTLB was a high level.Described first switch 26 and second switch 27 can make differential amplifier 22 be operated under the different patterns, to realize different circuit functions under the control of logic control signal CTL and CTLB.
The operation principle of described voltage detection circuit is as described below:
At first, control CTL is a high level, and then CTLB is a low level, and described differential amplifier 22 is connected first output by first switch 26 with inverting input, constitute a unity gain amplifier.At this moment, the input signal of unity gain amplifier is the reference voltage initial value that reference voltage circuit 23 produces.By circuit general knowledge as can be known, when difference amplifier 22 component unit gain amplifiers, its output output voltage equates that with the voltage of its normal phase input end input the output voltage that detect unity gain amplifier this moment obtains described reference voltage initial value.Described reference voltage calibration circuit 24 is calibrated reference voltage V REF according to described reference voltage initial value, obtains the required reference voltage of differential amplifier 22 reality.
Concrete calibration process is: system preestablishes a reference voltage desired value, described reference voltage calibration circuit 24 is according to the difference between described reference voltage initial value and the reference voltage desired value, adjust described reference voltage V REF and change to a relative approaching numerical value, thereby reduce the difference between described reference voltage V REF and the reference voltage desired value with described reference voltage desired value from described reference voltage initial value.
Then, control CTL is a low level, and then CTLB is a high level, and the inverting input of described differential amplifier 22 is connected with supply voltage sampled point A by second switch 27, is operated in the voltage comparator pattern.At this moment, the output of voltage comparator is second output of differential amplifier 22, the variation of supply voltage VDD is delivered to the inverting input of differential amplifier 22 by the sampled voltage INPUT real-time sampling of supply voltage sampled point A output, and reference voltage V REF connects the in-phase input end of differential amplifier 22.When sampled voltage INPUT was higher than reference voltage V REF, voltage comparator second output was output as low level; When sampled voltage INPUT was lower than reference voltage V REF, voltage comparator second output was output as high level.Therefore, can detect supply voltage in real time according to the variation of the logic level of described differential amplifier 22 outputs.
The described circuit of the utility model embodiment, logic control circuit 25 realizes that by the described differential amplifier 22 of described first switch 26 and second switch 27 controls multiplexing when reference voltage calibration and the voltage detecting differential amplifier 22 carries out function conversion between unit gain amplifying circuit and voltage comparator.When difference amplifier 22 is in unit gain amplifying circuit pattern, obtain the reference voltage initial value by measuring its output end voltage, the reference voltage that in-phase input end receives is calibrated, and said process can be offset the test error that the input offset voltage of differential amplifier 22 brings.For differential amplifier 22, the value of reference voltage V REF is adjustable very accurate, can improve the accuracy that supply voltage detects, and makes the described circuit of the utility model embodiment can be applicable to the system that the supply voltage accuracy of detection is had relatively high expectations.
Concrete, in conjunction with shown in Figure 2, described resistor voltage divider circuit 21 can comprise the first divider resistance R21 and the second divider resistance R22; The positive termination supply voltage VDD of the described first divider resistance R21, the negative terminal of the first divider resistance R21 connects the anode of the second divider resistance R22, the negativing ending grounding of the second divider resistance R22; The common port of the described first divider resistance R21 and the second divider resistance R22 is the output of described resistor voltage divider circuit 21, is designated as supply voltage sampled point A end.
The output of described resistor voltage divider circuit 21 (being supply voltage sampled point A end) connects first end of second switch 27, the inverting input of the described differential amplifier 22 of second termination of described second switch 27.
The input of the output termination reference voltage circuit 23 of described reference voltage calibration circuit 24; The in-phase input end of the output termination differential amplifier 22 of described reference voltage circuit 23.
The inverting input of the described differential amplifier 22 of first termination of described first switch 26, the first output OUT BUF of the second termination differential amplifier 22.
Described logic control circuit 25 is specifically as follows a not gate.The signal input end of the grid of the input of not gate 25, described first switch 26 and differential amplifier 22 meets logic control signal CTL, the grid of the output termination second switch 27 of not gate 25.Corresponding, described first switch 26 and second switch 27 can adopt nmos pass transistor to realize.
The operation principle of this circuit is:
At first, the input signal of not gate 25 (being logic control signal) CTL connects high level, and then the output signal CTLB of not gate 25 is a low level.At this moment, CTL controls 26 conductings of first switch, CTLB control second switch 27 turn-offs, and makes the inverting input of differential amplifier 22 and supply voltage sampled point A end disconnect, and first output OUT_BUF of differential amplifier 22 and inverting input are communicated with by first switch 26.Differential amplifier 22 component unit gain amplifiers, its input signal are the reference voltage V REF from reference voltage circuit 23 outputs.At this moment, the output voltage of measurement differential amplifier 22 can obtain the initial value of reference voltage.Reference voltage calibration circuit 24 is calibrated according to the reference voltage V REF of described initial value to 23 outputs of described reference voltage circuit, obtains the required reference voltage of differential amplifier 22.
Then, the input signal CTL of not gate 25 connects low level, and then the output signal CTLB of not gate 25 is a high level.At this moment, CTL controls first switch 26 and turn-offs, 27 conductings of CTLB control second switch make the inverting input of differential amplifier 22 be communicated with by second switch 27 with supply voltage sampled point A end, and first output OUT_BUF of differential amplifier 22 and inverting input disconnect.Differential amplifier 22 is operated in open loop situations as voltage comparator, its in-phase input end meets the reference voltage V REF after the calibration, its inverting input meets power supply sampled voltage INPUT, wherein, described power supply sampled voltage INPUT is obtained through the first divider resistance R21 and the second divider resistance R22 dividing potential drop by supply voltage VDD.When described supply voltage VDD rises, power supply sampled voltage INPUT follows VDD and rises, when the power supply sampled voltage INPUT that receives when the inverting input of difference amplifier 22 was higher than the reference voltage V REF that in-phase input end receives, its second output OUT_COMP was a low level; When described supply voltage VDD descends, power supply sampled voltage INPUT follows VDD and descends, when the power supply sampled voltage INPUT that receives when the inverting input of difference amplifier 22 was lower than the reference voltage V REF that in-phase input end receives, its second output OUT_COMP was a high level.Thus, the variation of supply voltage VDD can be by power supply sampled voltage INPUT real-time sampling, deliver to the inverting input of differential amplifier 22, reference voltage V REF does not change with supply voltage VDD simultaneously, therefore, can detect supply voltage VDD in real time according to the variation of the logic level of the second output OUT_COMP of differential amplifier 22.
Among the utility model embodiment, described differential amplifier can adopt difference to import the high-gain amplifier of single-ended output.With reference to Fig. 3, be the differential amplifier circuit structure chart of the utility model embodiment.What Fig. 3 provided only is a kind of embodiment of described differential amplifier circuit, and in other embodiment of the utility model, described differential amplifier circuit can adopt other execution mode to realize.The differential amplifier that increases compensating element, and switch formation by the high gain voltage comparator that the utility model is provided is equally applicable to the utility model, belongs within the protection range of the present utility model.
Described differential amplifier 22 comprises: a PMOS transistor M30, the 2nd PMOS transistor M31, the 3rd PMOS transistor M32, the 4th PMOS transistor M34, the 5th PMOS transistor M35, the first nmos pass transistor M33, the second nmos pass transistor M36, the 3rd nmos pass transistor M37, the 4th nmos pass transistor M38, the 5th nmos pass transistor M39, the 6th nmos pass transistor MCTL, NOR gate 31, not gate 32, the 3rd resistance 33, electric capacity 34 and current source 35.
The one PMOS transistor M30, the 2nd PMOS transistor M31 and the 3rd PMOS transistor M32 constitute current-mirror structure, produce current offset, the source electrode of the source electrode of a PMOS transistor M30, the 2nd PMOS transistor M31, the source electrode of the 3rd PMOS transistor M32 meet supply voltage VDD jointly; The drain electrode of the one PMOS transistor M30 connects the positive pole of current source 35, the minus earth of current source 35, and wherein, current source 35 is used to differential amplifier 22 that current reference is provided; The grid of the one PMOS transistor M30 and drain electrode short circuit, the grid of a PMOS transistor M30 connects the grid of the 2nd PMOS transistor M31 and the grid of the 3rd PMOS transistor M32; The drain electrode of the 2nd PMOS transistor M31 connects the source electrode of the 4th PMOS transistor M34 and the source electrode of the 5th PMOS transistor M35; The 4th PMOS transistor M34 and the 5th PMOS transistor M35 constitute input difference to pipe, wherein, the grid of the 4th PMOS transistor M34 is the inverting input INN of differential amplifier 22, and the grid of the 5th PMOS transistor M35 is the in-phase input end INP of differential amplifier 22; The drain electrode of the 4th PMOS transistor M34 connects the drain electrode of the second nmos pass transistor M36, the drain and gate short circuit of the second nmos pass transistor M36, the source ground of the second nmos pass transistor M36; The drain electrode of the 5th PMOS transistor M35 connects the drain electrode of the 3rd nmos pass transistor M37, and the grid of the 3rd nmos pass transistor M37 connects the grid of the second nmos pass transistor M36, the source ground of the 3rd nmos pass transistor M37; The drain electrode of the 3rd PMOS transistor M32 connects the drain electrode of grid and the 4th nmos pass transistor M38 of the first nmos pass transistor M33, and the drain electrode of the 3rd PMOS transistor M32 also connects second input of NOR gate 31 and the negative pole of electric capacity 34; The positive pole of electric capacity 34 connects the drain electrode of the 6th nmos pass transistor MCTL through the 3rd resistance 33, first end of the grid of the 6th nmos pass transistor MCTL and NOR gate 31 together meets control signal CTL, wherein, electric capacity 34 and the 3rd resistance 33 common compensating circuits that constitute differential amplifier 22 improve its stability; The grid of the source electrode of the 6th nmos pass transistor MCTL and the 4th nmos pass transistor M38 together connects the drain electrode of the 3rd nmos pass transistor M37; The grid of the 4th nmos pass transistor M38 connects the grid of the 5th nmos pass transistor M39, the source ground of the source electrode of the 4th nmos pass transistor M38 and the 5th nmos pass transistor M39; The drain electrode of the first nmos pass transistor M33 meets supply voltage VDD, and the source electrode of the first nmos pass transistor M33 connects the drain electrode of the 5th nmos pass transistor M39, and the common ends of the two is as the first output OUT_BUF of differential amplifier 22; The input of the output termination not gate 32 of NOR gate 31, the output of not gate 32 is as the second output OUT_COMP of differential amplifier 22.
When control signal CTL connects high level, differential amplifier 22 connects into the unit gain structure by first switch 26 with the first output OUT_BUF and inverting input INN, the 6th nmos pass transistor MCTL is as switch conduction, the electric capacity 34 and the 3rd resistance 33 that constitute compensating circuit can carry out frequency compensation to this unity gain amplifier, make it stable measuring basis voltage VREF.The first nmos pass transistor M33 and the 5th nmos pass transistor M39 constitute the output buffer stage, can improve the load capacity of unity gain amplifier.Simultaneously, control signal CTL is as the input signal of NOR gate 31 first ends, with the second output OUT_COMP set of differential amplifier 22.
When control signal CTL connect low level, the second output OUT_COMP of differential amplifier 22 was released, and differential amplifier 22 detects the variation of supply voltage VDD as voltage comparator work at this moment.The in-phase input end INP of differential amplifier 22 meets reference voltage V REF, and inverting input INN meets the sampled voltage INPUT of supply voltage VDD, and the output result is through the shaping of NOR gate 31 and not gate 32, from the second output OUT_COMP output of differential amplifier 22.
More than to the voltage detection circuit of a kind of Switching Power Supply provided by the utility model, be described in detail, used specific case herein principle of the present utility model and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, part in specific embodiments and applications all can change.In sum, this description should not be construed as restriction of the present utility model.
Claims (8)
1. the voltage detection circuit of a Switching Power Supply is characterized in that, comprising:
The inverting input of differential amplifier connects the supply voltage sampled point by second switch, and the in-phase input end of described differential amplifier connects reference voltage circuit, and the inverting input of described differential amplifier connects first output by first switch;
The input termination reference voltage calibration circuit of described reference voltage circuit;
The grid of the input of logic control circuit, described first switch and the signal input end of described differential amplifier connect logic control signal, the grid of the described second switch of output termination of described logic control circuit;
Described logic control circuit is controlled described differential amplifier multiplexing when reference voltage calibration and the voltage detecting by described first switch and second switch.
2. voltage detection circuit according to claim 1 is characterized in that described circuit also comprises resistor voltage divider circuit;
Described resistor voltage divider circuit comprises first divider resistance and second divider resistance; The positive termination supply voltage of described first divider resistance, the negative terminal of first divider resistance connects the anode of second divider resistance, the negativing ending grounding of second divider resistance;
The common port of described first divider resistance and second divider resistance is described supply voltage sampled point.
3. voltage detection circuit according to claim 1 is characterized in that, described differential amplifier is the high-gain amplifier that difference is imported single-ended output.
4. voltage detection circuit according to claim 3 is characterized in that, described differential amplifier comprises:
The transistorized source electrode of the one PMOS, the transistorized source electrode of the 2nd PMOS, the transistorized source electrode of the 3rd PMOS connect supply voltage jointly; The one PMOS transistor drain connects the positive pole of current source, the minus earth of current source; Transistorized grid of the one PMOS and drain electrode short circuit, the transistorized grid of a PMOS connects transistorized grid of the 2nd PMOS and the transistorized grid of the 3rd PMOS; The 2nd PMOS transistor drain connects transistorized source electrode of the 4th PMOS and the transistorized source electrode of the 5th PMOS; The transistorized grid of the 4th PMOS is the inverting input of differential amplifier, and the transistorized grid of the 5th PMOS is the in-phase input end of differential amplifier; The 4th PMOS transistor drain connects the drain electrode of second nmos pass transistor, the drain and gate short circuit of second nmos pass transistor, the source ground of second nmos pass transistor; The 5th PMOS transistor drain connects the drain electrode of the 3rd nmos pass transistor, and the grid of the 3rd nmos pass transistor connects the grid of second nmos pass transistor, the source ground of the 3rd nmos pass transistor; The 3rd PMOS transistor drain connects the drain electrode of the grid and the 4th nmos pass transistor of first nmos pass transistor, and the 3rd PMOS transistor drain also connects second input of NOR gate and the negative pole of electric capacity; The positive pole of electric capacity connects the drain electrode of the 6th nmos pass transistor through the 3rd resistance, and first end of the grid of the 6th nmos pass transistor and NOR gate together connects logic control signal; The grid of the source electrode of the 6th nmos pass transistor and the 4th nmos pass transistor together connects the drain electrode of the 3rd nmos pass transistor; The grid of the 4th nmos pass transistor connects the grid of the 5th nmos pass transistor, the source ground of the source electrode of the 4th nmos pass transistor and the 5th nmos pass transistor; The drain electrode of first nmos pass transistor connects supply voltage, and the source electrode of first nmos pass transistor connects the drain electrode of the 5th nmos pass transistor, and the common ends of the two is as first output of differential amplifier; The input of the output termination not gate of NOR gate, the output of not gate is as second output of differential amplifier.
5. voltage detection circuit according to claim 1 is characterized in that, multiplexing be specially of described differential amplifier when reference voltage calibration and voltage detecting:
Described differential amplifier carries out the function conversion between unit gain amplifying circuit and voltage comparator.
6. voltage detection circuit according to claim 5 is characterized in that,
Described logic control circuit is a not gate.
7. voltage detection circuit according to claim 5 is characterized in that,
Described first switch and/or second switch are nmos pass transistor.
8. voltage detection circuit according to claim 5, it is characterized in that, described reference voltage calibration circuit is used for according to the deviation between reference voltage initial value and the default reference voltage desired value, and the reference voltage that described reference voltage circuit is exported to described differential amplifier is calibrated;
Wherein, described reference voltage initial value is the output voltage of described differential amplifier when being in unit gain amplifying circuit mode of operation.
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| CN2010205116478U CN201774453U (en) | 2010-08-26 | 2010-08-26 | Power supply voltage detection circuit of switching power supply |
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| CN2010205116478U CN201774453U (en) | 2010-08-26 | 2010-08-26 | Power supply voltage detection circuit of switching power supply |
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-
2010
- 2010-08-26 CN CN2010205116478U patent/CN201774453U/en not_active Expired - Lifetime
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