CN108990238B - Sound-light control circuit - Google Patents
Sound-light control circuit Download PDFInfo
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- CN108990238B CN108990238B CN201811012307.8A CN201811012307A CN108990238B CN 108990238 B CN108990238 B CN 108990238B CN 201811012307 A CN201811012307 A CN 201811012307A CN 108990238 B CN108990238 B CN 108990238B
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- 238000001514 detection method Methods 0.000 claims abstract description 53
- 230000003287 optical effect Effects 0.000 claims abstract description 16
- 230000005236 sound signal Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 70
- 239000013256 coordination polymer Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 9
- 102100031024 CCR4-NOT transcription complex subunit 1 Human genes 0.000 description 3
- 102100031033 CCR4-NOT transcription complex subunit 3 Human genes 0.000 description 3
- 102100032981 CCR4-NOT transcription complex subunit 4 Human genes 0.000 description 3
- 101000919674 Caenorhabditis elegans CCR4-NOT transcription complex subunit let-711 Proteins 0.000 description 3
- 101100384374 Drosophila melanogaster Not10 gene Proteins 0.000 description 3
- 101000919672 Homo sapiens CCR4-NOT transcription complex subunit 1 Proteins 0.000 description 3
- 101000919663 Homo sapiens CCR4-NOT transcription complex subunit 3 Proteins 0.000 description 3
- 101000942594 Homo sapiens CCR4-NOT transcription complex subunit 4 Proteins 0.000 description 3
- 101100294409 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NOT5 gene Proteins 0.000 description 2
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 2
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 2
- 102100031025 CCR4-NOT transcription complex subunit 2 Human genes 0.000 description 1
- 101001092183 Drosophila melanogaster Regulator of gene activity Proteins 0.000 description 1
- 101000919667 Homo sapiens CCR4-NOT transcription complex subunit 2 Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
- H03K17/941—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated using an optical detector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/105—Controlling the light source in response to determined parameters
- H05B47/115—Controlling the light source in response to determined parameters by determining the presence or movement of objects or living beings
- H05B47/12—Controlling the light source in response to determined parameters by determining the presence or movement of objects or living beings by detecting audible sound
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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- Amplifiers (AREA)
- Electronic Switches (AREA)
Abstract
The invention relates to the technical field of control, in particular to an acousto-optic control circuit which comprises an acoustic detection circuit, an optical detection circuit, a logic unit, an oscillator, a timer, a driving circuit and a reference circuit, wherein the acoustic detection circuit is connected with the optical detection circuit; the sound detection circuit is used for detecting sound signals, and the output end of the sound detection circuit is connected with the first input end and the second input end of the logic unit; the optical detection circuit is used for detecting optical signals, and the output end of the optical detection circuit is connected with the third input end of the logic unit; the output end of the oscillator is connected with the input end of the timer; the output end of the timer is connected with the fourth input end of the logic unit; the output end of the logic unit is connected with the input end of the driving circuit; the driving circuit is connected with the controlled device; the reference circuit provides reference voltage and internal power supply for the system; the acousto-optic control circuit has the advantages of simple peripheral circuit structure, low cost, low standby power consumption and the like.
Description
Technical Field
The invention relates to the technical field of control, in particular to an acousto-optic control circuit.
Background
The existing acousto-optic control circuit is generally formed by building a 4-way 2-input NAND gate logic chip together with other components, has a complex peripheral circuit structure, is high in circuit cost and high in standby power consumption, and is not beneficial to popularization and application.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an acousto-optic control circuit with a simple structure.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
an acousto-optic control circuit comprises an acoustic detection circuit, an optical detection circuit, a logic unit, an oscillator, a timer, a driving circuit and a reference circuit;
the sound detection circuit is used for detecting sound signals, and the output end of the sound detection circuit is connected with the first input end and the second input end of the logic unit;
the optical detection circuit is used for detecting optical signals, and the output end of the optical detection circuit is connected with the third input end of the logic unit;
the output end of the oscillator is connected with the input end of the timer;
the output end of the timer is connected with the fourth input end of the logic unit;
the output end of the logic unit is connected with the input end of the driving circuit;
the driving circuit is connected with the controlled device;
the reference circuit provides a reference voltage and an internal power supply to the system.
Preferably, the reference circuit comprises a BGP circuit and an operational amplifier, wherein the BGP circuit is used for generating reference voltages and comprises a first output end, a second output end, a third output end, a fourth output end and a fifth output end, the five output ends respectively provide five reference voltages, the first output end of the BGP circuit is connected with the positive input end of the operational amplifier, and the output end of the operational amplifier is connected with the negative input end of the BGP circuit and serves as a VDDAUX signal end.
Preferably, the sound detection circuit comprises a pickup circuit, a band-pass filter amplifier, a first comparator and a second comparator, wherein the output end of the pickup circuit is connected with the input end of the band-pass filter amplifier, the output end of the band-pass filter amplifier is respectively connected with the inverting input end of the first comparator and the non-inverting input end of the second comparator, the non-inverting input end of the first comparator is connected with the second output end of the reference circuit, the output end of the first comparator is connected with the first input end of the logic unit, the inverting input end of the second comparator is connected with the fourth output end of the reference circuit, and the output end of the second comparator is connected with the second input end of the logic unit.
Preferably, the pickup circuit comprises a sound sensor, a resistor R9 and a capacitor C5, wherein one end of the resistor R9 is connected with the VDDAUX signal end, the other end of the resistor R9 is respectively connected with the positive input end of the sound sensor and one end of the capacitor C5, and the output end of the pickup circuit is grounded, and the other end of the capacitor C5 and the negative input end of the sound sensor are grounded; the band-pass filter amplifier comprises a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a first amplifier and a second amplifier, wherein one end of the resistor R0 is used as an input end of the band-pass filter amplifier and is connected with an output end of a pickup circuit, the other end of the resistor R0 is respectively connected with one end of the resistor R1 and one end of the capacitor CO, the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with one end of the resistor R2 and one end of the positive input end of the first amplifier, the negative input end of the first amplifier is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the output end of the first amplifier is respectively connected with one end of the resistor R5 and one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with one end of the positive input end of the second amplifier, the negative end of the second amplifier is respectively connected with one end of the resistor C3 and one end of the resistor C3, and the other end of the resistor C4 is respectively connected with one end of the resistor C4 and the other end of the resistor C4 and the other end of the resistor C4 is respectively connected with the other end of the resistor C4.
Preferably, the light detection circuit comprises a photoresistor, a photoresistor detection circuit and a third comparator, wherein the output end of the photoresistor is connected with the input end of the photoresistor detection circuit, the output end of the photoresistor detection circuit is connected with the inverting input end of the third comparator, the non-inverting input end of the third comparator is connected with the fifth output end of the reference circuit, and the output end of the third comparator is connected with the third input end of the logic unit.
Preferably, one end of the photoresistor is grounded, and the other end of the photoresistor is used as an output end of the photoresistor; the photoresistor detection circuit comprises a current source, a resistor R10, a resistor R11, a capacitor C6 and a capacitor C7, wherein one end of the current source is connected with the VDD end of an external power supply, the other end of the current source is connected with the output end of the photoresistor and one end of the capacitor R10 respectively, the other end of the resistor R10 is connected with one end of the capacitor C6 and one end of the resistor R11 respectively, and the other end of the resistor R11 is connected with one end of the capacitor C7 and serves as the output end of the photoresistor detection circuit.
Preferably, the logic unit comprises a first and gate, a second and gate, a third and gate, a first RS trigger, a first not gate and a second not gate, wherein the first input end of the first and gate is used as the first input end of the logic unit, the second input end of the first and gate is used as the second input end of the logic unit, the output end of the second and gate is connected with the first input end of the third and gate, the second input end of the third and gate is used as the fourth input end of the logic unit and is connected with the CLR end of the first RS trigger and the output end of the timer, the output end of the third and gate is connected with the CP end of the first RS trigger, the S input end of the first RS trigger is provided with a high level, the Q output end of the first and the second not gate is connected with the input end of the second not gate, and the output end of the second not gate is used as the output end of the logic unit.
Preferably, the oscillator includes a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C8, a PMOS transistor P1, an NMOS transistor N1, a third amplifier, a fourth amplifier, a second RS flip-flop, and a third not gate, one end of the resistor R12 is connected to the VDD terminal of the external power supply, the other end is connected to one end of the resistor R13 and the negative input terminal of the third amplifier, the other end of the resistor R13 is connected to one end of the resistor R14 and the positive input terminal of the fourth amplifier, the positive input terminal of the third amplifier is connected to the negative input terminal of the fourth amplifier, one end of the capacitor C8, one end of the capacitor R15, the output terminal is connected to the S input terminal of the second RS flip-flop, the output terminal of the fourth amplifier is connected to the R input terminal of the second RS flip-flop, the other end of the resistor R15 is connected to the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected to the NMOS terminal of the external power supply, the gate is connected to the NMOS terminal of the VDD terminal of the external power supply, and the second RS flip-flop is connected to the gate of the second RS flip-flopThe output end is connected, the Q output end of the second RS trigger is connected with the input end of a third NOT gate, the output end of the third NOT gate is used as the output end of the oscillator, and the other end of the resistor R14, the other end of the capacitor C8 and the source electrode of the NMOS tube N1 are grounded.
Preferably, the timer comprises 22 frequency dividers, and the 22 frequency dividers are cascaded in turn, wherein the input end of the first frequency divider is used as the input end of the timer, and the output end of the last frequency divider is used as the output end of the timer.
Preferably, the driving circuit includes a fourth and gate, a fifth and gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a tenth not gate, an eleventh not gate, a twelfth not gate, a PMOS transistor P2, and an NMOS transistor N2, wherein a first input terminal of the fourth and gate is connected to an input terminal of the fourth not gate and serves as an input terminal of the driving circuit, a second input terminal is connected to an output terminal of the tenth and eleventh not gates, respectively, an output terminal is connected to an input terminal of the fifth not gate, an output terminal of the fourth and a second input terminal of the fifth and gate are connected, a first input terminal of the fifth and gate is connected to an output terminal of the sixth not gate, an output terminal is connected to an input terminal of the ninth not gate, an output terminal of the fifth not gate is connected to an input terminal of the sixth not gate, an output terminal of the seventh not gate is connected to an input terminal of the eighth not gate, an output terminal of the eighth not gate is connected to an output terminal of the eighth not gate, and an output terminal of the eighth not gate is connected to the NMOS transistor N2.
From the above description, it can be seen that the present invention has the following advantages: the acousto-optic control circuit has the advantages of simple peripheral circuit structure, low cost, low standby power consumption and the like.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of the reference circuit of the present invention;
FIG. 3 is a schematic diagram of the structure of a BGP circuit in the reference circuit of the present invention;
FIG. 4 is a schematic diagram of the sound detection circuit of the present invention;
FIG. 5 is a schematic diagram of a light detection circuit according to the present invention;
FIG. 6 is a schematic diagram of a logic cell of the present invention;
FIG. 7 is a schematic diagram of the structure of an oscillator of the present invention;
FIG. 8 is a schematic diagram of the structure of the timer of the present invention;
fig. 9 is a schematic diagram of the structure of the driving circuit of the present invention.
Detailed Description
One embodiment of the present invention is described in detail with reference to fig. 1, but does not limit the claims of the present invention in any way.
As shown in fig. 1, an acousto-optic control circuit comprises an acoustic detection circuit, an optical detection circuit, a logic unit, an oscillator, a timer, a driving circuit and a reference circuit; the sound detection circuit is used for detecting sound signals, and the output end of the sound detection circuit is connected with the first input end and the second input end of the logic unit; the optical detection circuit is used for detecting optical signals, and the output end of the optical detection circuit is connected with the third input end of the logic unit; the output end of the oscillator is connected with the input end of the timer; the output end of the timer is connected with the fourth input end of the logic unit; the output end of the logic unit is connected with the input end of the driving circuit; the driving circuit and the controlled device (such as a silicon controlled rectifier, a triode and the like); the reference circuit provides a reference voltage and an internal power supply to the system.
The technical scheme is designed in a refinement way, and the method is as follows:
as shown in fig. 2, the reference circuit includes a BGP circuit (i.e., a bandgap reference circuit) and an operational amplifier, where the BGP circuit is configured to generate a reference voltage, and includes a first output end, a second output end, a third output end, a fourth output end, and a fifth output end, where the five output ends respectively provide five reference voltages, the first output end of the BGP circuit is connected to a positive input end of the operational amplifier, and an output end of the operational amplifier is connected to its own negative input end and is used as a VDDAUX signal end. The BGP circuit is a common circuit, and the structural design thereof is not described herein, and reference may be made to the structure shown in fig. 3, where the left circuit in fig. 3 is a start circuit, and the right circuit is a bandgap reference voltage circuit.
As shown in fig. 4, the sound detection circuit includes a pickup circuit, a band-pass filter amplifier, a first comparator and a second comparator, the output end of the pickup circuit is connected with the input end of the band-pass filter amplifier, the output end of the band-pass filter amplifier is connected with the inverting input end of the first comparator and the non-inverting input end of the second comparator, the non-inverting input end of the first comparator is connected with the second output end of the reference circuit, the output end is connected with the first input end of the logic unit, the inverting input end of the second comparator is connected with the fourth output end of the reference circuit, and the output end is connected with the second input end of the logic unit, wherein:
(1) The sound pickup circuit comprises a sound sensor MIC, a resistor R9 and a capacitor C5, wherein one end of the resistor R9 is connected with the VDDAIX signal end, the other end of the resistor R9 is respectively connected with the positive input end of the sound sensor MIC and one end of the capacitor C5, the output end of the sound pickup circuit is grounded, and the other end of the capacitor C5 and the negative input end of the sound sensor are grounded;
(2) The band-pass filter amplifier comprises a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a first amplifier U1 and a second amplifier U2, wherein one end of the resistor R0 is used as an input end MICIN of the band-pass filter amplifier and is connected with an output end of a pickup circuit, the other end of the resistor R0 is respectively connected with one end of the resistor R1 and one end of the capacitor CO, the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with one end of the resistor R2 and one end of the positive input end of the first amplifier U1, the negative input end of the first amplifier U1 is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the output end of the first amplifier U1 is respectively connected with the other end of the resistor R5, the other end of the capacitor C3 is respectively connected with one end of the positive input end of the resistor R3, the other end of the second amplifier U2 is respectively connected with one end of the resistor C3, the negative end of the resistor C2 is connected with the other end of the resistor C7, the other end of the resistor C4 is respectively connected with the other end of the resistor C4, and the other end of the resistor C4 is connected with the other end of the resistor C4.
As shown in fig. 5, the light detection circuit includes a light resistor RL, a light resistor detection circuit and a third comparator, wherein an output end of the light resistor RL is connected with an input end of the light resistor detection circuit, an output end of the light resistor detection circuit is connected with an inverting input end of the third comparator, a non-inverting input end of the third comparator is connected with a fifth output end of the reference circuit, and an output end of the third comparator is connected with a third input end of the logic unit, wherein:
(1) One end of the photoresistor RL is grounded, and the other end of the photoresistor RL is used as an output end of the photoresistor RL;
(2) The photoresistor detection circuit comprises a current source I1, a resistor R10, a resistor R11, a capacitor C6 and a capacitor C7, wherein one end of the current source I1 is connected with the VDD end of an external power supply, the other end of the current source I1 is used as an input end CDSIN of the photoresistor detection circuit to be respectively connected with the output end of a photoresistor RL and one end of the capacitor R10, the other end of the resistor R10 is respectively connected with one end of the capacitor C6 and one end of the resistor R11, and the other end of the resistor R11 is connected with one end of the capacitor C7 and is used as an output end of the photoresistor detection circuit.
As shown in fig. 6, the logic unit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a first RS flip-flop, a first NOT gate NOT1, AND a second NOT gate NOT2, where a first input terminal of the first AND gate AND1 is a first input terminal of the logic unit, a second input terminal is a second input terminal of the logic unit, an output terminal is connected to the first input terminal of the second AND gate AND2, a second input terminal of the second AND gate AND2 is a third input terminal of the logic unit, an output terminal is connected to the first input terminal of the third AND gate AND3, a second input terminal of the third AND gate AND3 is a fourth input terminal of the logic unit AND is connected to a CLR terminal of the first RS flip-flop, an output terminal of the timer is connected to a CP terminal of the first RS flip-flop, an S input terminal of the first RS flip-flop is set at a high level, an Q output terminal is connected to an input terminal of the first NOT gate NOT1, AND an output terminal of the first NOT gate NOT1 is connected to an input terminal of the second NOT gate AND 2.
As shown in fig. 7, the oscillator includes a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C8, a PMOS transistor P1, an NMOS transistor N1, a third amplifier U3, a fourth amplifier U4, a second RS flip-flop, and a third NOT3, wherein one end of the resistor R12 is connected to the VDD terminal of the external power supply, the other end is connected to one end of the resistor R13 and the negative input terminal of the third amplifier U3, the other end of the resistor R13 is connected to one end of the resistor R14 and the positive input terminal of the fourth amplifier U4, the positive input terminal of the third amplifier U3 is connected to the negative input terminal of the fourth amplifier U4, one end of the capacitor C8, and one end of the capacitor R15, the output terminal of the fourth amplifier U4 is connected to the R input terminal of the second RS flip-flop, the other end of the resistor R15 is connected to the drain of the PMOS transistor P1, the drain of the NMOS transistor N1, the source of the NMOS transistor P1 is connected to the NMOS terminal of the power supply, and the source of the NMOS transistor P1 is connected to the VDD terminal of the external power supply, and the second RS flip-flopThe output end is connected, the Q output end of the second RS trigger is connected with the input end of the third NOT3, the output end of the third NOT3 is used as the output end OSC of the oscillator, and the other end of the resistor R14, the other end of the capacitor C8 and the source electrode of the NMOS tube N1 are grounded.
As shown in fig. 8, the Timer includes 22 frequency dividers, and the 22 frequency dividers are cascaded in sequence, wherein the input end of the first frequency divider is used as the input end of the Timer, and the output end of the last frequency divider is used as the output end timer_out of the Timer.
As shown in fig. 9, the driving circuit includes a fourth AND gate AND4, a fifth AND gate AND5, a fourth NOT gate NOT4, a fifth NOT gate NOT5, a sixth NOT gate NOT6, a seventh NOT gate NOT7, an eighth NOT gate NOT8, a ninth NOT gate NOT9, a tenth NOT gate NOT10, an eleventh NOT gate NOT11, a twelfth NOT gate NOT12, a PMOS pipe P2 AND an NMOS pipe N2, a first input terminal of the fourth AND gate AND4 is connected to an input terminal of the fourth NOT gate NOT4 AND serves as an input terminal of the driving circuit, a second input terminal is connected to an output terminal of the tenth NOT gate NOT10 AND an input terminal of the eleventh NOT gate NOT11, an output terminal of the fourth AND gate NOT4 is connected to a second input terminal of the fifth AND gate AND5, the first input end of the fifth AND gate AND5 is respectively connected with the output end of the sixth NOT6 AND the input end of the seventh NOT7, the output end is connected with the input end of the ninth NOT9, the output end of the fifth NOT5 is connected with the input end of the sixth NOT6, the output end of the seventh NOT7 is connected with the input end of the eighth NOT8, the output end of the ninth NOT9 is connected with the input end of the tenth NOT10, the output end of the eleventh NOT11 is connected with the input end of the twelfth NOT12, the grid electrode of the PMOS tube P2 is connected with the output end of the eighth NOT8, the source electrode is connected with the VDD end of the external power supply, the drain electrode is connected with the drain electrode of the NMOS tube N2 AND serves as a signal output end SCRCTRL of the driving circuit, AND the grid electrode of the NMOS tube N2 is connected with the output end of the twelfth NOT12 AND the source electrode is grounded.
The ground mentioned in the technical scheme is connected with the ground of an external power supply.
The working principle of the invention is as follows:
the sound sensor of the pickup circuit picks up a sound signal and converts the sound signal into an electric signal to be output to the band-pass filter amplifier, the band-pass filter amplifier filters and amplifies the received signal and outputs the signal to the first comparator and the second comparator, and the first comparator and the second comparator compare the signal and output the comparison result to the logic unit;
the photoresistor of the light detection circuit receives the light signal and converts the light signal into an electric signal and then outputs the electric signal to the photoresistor electric measurement circuit, a second-order low-pass filter is formed by a resistor R10, a resistor R11, a capacitor C6 and a capacitor C7, the received electric signal is filtered and then is output to a third comparator, the third comparator compares the signals, and the comparison result is output to the logic unit;
the oscillator is generated by RC charge and discharge, when the voltage of a capacitor C8 is lower, the Q output end of a second RS trigger outputs a low level, R15 is connected to VDD, C8 is charged, when the voltage of the C8 exceeds the reference level of an amplifier U3 to enable U3 to turn over, the second RS trigger turns over, R15 is connected to GND, the capacitor C8 begins to discharge, when the voltage of the C8 is lower than the reference level of the amplifier U4, U4 turns over, the second RS trigger turns over, and the oscillator completes a period;
the output end OSC of the oscillator is input to a timer, and the timer is formed by cascading 22 frequency dividers;
the logic unit receives the comparison result of the first comparator, the comparison result of the second comparator, the comparison result of the third comparator and the output signal of the timer, and outputs the output signal to be low level and high level at ordinary times when the timer finishes timing. When the external environment becomes dark and the output of the first AND gate and the output of the third comparator are both high level, the RS trigger is turned over, the output becomes high, the DRV becomes high, the timer starts to count, and the sound detection circuit and the light detection circuit are turned off.
The sound and light control circuit can be applied to lighting lamp control in public places and can also be used as a switch.
In summary, the invention has the following advantages: the acousto-optic control circuit has the advantages of simple peripheral circuit structure, low cost, low standby power consumption and the like.
It is to be understood that the foregoing detailed description of the invention is merely illustrative of the invention and is not limited to the embodiments of the invention. It will be understood by those of ordinary skill in the art that the present invention may be modified or substituted for elements thereof to achieve the same technical effects; as long as the use requirement is met, the invention is within the protection scope of the invention.
Claims (4)
1. An acousto-optic control circuit, characterized in that: the device comprises a sound detection circuit, a light detection circuit, a logic unit, an oscillator, a timer, a driving circuit and a reference circuit;
the sound detection circuit is used for detecting sound signals, and the output end of the sound detection circuit is connected with the first input end and the second input end of the logic unit; the sound detection circuit comprises a pickup circuit, a band-pass filter amplifier, a first comparator and a second comparator, wherein the output end of the pickup circuit is connected with the input end of the band-pass filter amplifier, the output end of the band-pass filter amplifier is respectively connected with the inverting input end of the first comparator and the non-inverting input end of the second comparator, the non-inverting input end of the first comparator is connected with the second output end of the reference circuit, the output end of the first comparator is connected with the first input end of the logic unit, the inverting input end of the second comparator is connected with the fourth output end of the reference circuit, and the output end of the second comparator is connected with the second input end of the logic unit;
the optical detection circuit is used for detecting optical signals, and the output end of the optical detection circuit is connected with the third input end of the logic unit; the light detection circuit comprises a photoresistor, a photoresistor detection circuit and a third comparator, wherein the output end of the photoresistor is connected with the input end of the photoresistor detection circuit, the output end of the photoresistor detection circuit is connected with the inverting input end of the third comparator, the non-inverting input end of the third comparator is connected with the fifth output end of the reference circuit, and the output end of the third comparator is connected with the third input end of the logic unit;
the output end of the oscillator is connected with the input end of the timer; the oscillator comprises a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C8, a PMOS tube P1, an NMOS tube N1, a third amplifier, a fourth amplifier, a second RS trigger and a third NOT gate, wherein one end of the resistor R12 is connected with the VDD end of an external power supply, the other end of the resistor R13 is respectively connected with one end of the resistor R13 and the negative input end of the third amplifier, the other end of the resistor R13 is respectively connected with one end of the resistor R14 and the positive input end of the fourth amplifier, the positive input end of the third amplifier is respectively connected with the negative input end of the fourth amplifier, one end of the capacitor C8 and one end of the capacitor R15, the output end of the third amplifier is connected with the S input end of the second RS trigger, the output end of the fourth amplifier is connected with the R input end of the second RS trigger, the other end of the resistor R15 is respectively connected with the drain electrode of the PMOS tube P1 and the drain electrode of the NMOS tube N1, the source electrode of the PMOS tube P1 is respectively connected with the NMOS end of the external power supply, the grid electrode is respectively connected with the NMOS end of the grid electrode of the resistor P1 and the drain electrode of the NMOS tube N1, the grid electrode is respectively connected with the drain electrode of the NMOS tube N1, the grid electrode of the grid electrode is connected with the drain electrode of the NMOS tube C1, the grid electrode is connected with the drain electrode of the grid electrode of the NMOS tube, the grid electrode is the grid electrode, the grid electrode is the electrode, the electrode is and the electrode, the electrode is electrode and the electrode is the electrode, the electrode is electrode;
the output end of the timer is connected with the fourth input end of the logic unit; the timer comprises 22 frequency dividers, the 22 frequency dividers are sequentially cascaded, the input end of the first frequency divider is used as the input end of the timer, and the output end of the last frequency divider is used as the output end of the timer;
the output end of the logic unit is connected with the input end of the driving circuit; the logic unit comprises a first AND gate, a second AND gate, a third AND gate, a first RS trigger, a first NOT gate and a second NOT gate, wherein the first input end of the first AND gate is used as the first input end of the logic unit, the second input end of the first AND gate is used as the second input end of the logic unit, the output end of the second AND gate is connected with the first input end of the third AND gate, the second input end of the third AND gate is used as the fourth input end of the logic unit and is connected with the CLR end of the first RS trigger and the output end of the timer, the output end of the third AND gate is connected with the CP end of the first RS trigger, the S input end of the first RS trigger is provided with a high level, the Q output end of the first NOT gate is connected with the input end of the second NOT gate, and the output end of the second NOT gate is used as the output end of the logic unit;
the driving circuit is connected with the controlled device;
the reference circuit comprises a BGP circuit and an operational amplifier, wherein the BGP circuit is used for generating reference voltages and comprises a first output end, a second output end, a third output end, a fourth output end and a fifth output end, the five output ends respectively provide five reference voltages, the first output end of the BGP circuit is connected with the positive input end of the operational amplifier, and the output end of the operational amplifier is connected with the negative input end of the operational amplifier and is used as a VDDAUX signal end; the reference circuit provides a reference voltage and an internal power supply to the system.
2. The acousto-optic control circuit according to claim 1, wherein: the sound pickup circuit comprises a sound sensor, a resistor R9 and a capacitor C5, wherein one end of the resistor R9 is connected with the VDDAIX signal end, the other end of the resistor R9 is respectively connected with the positive input end of the sound sensor and one end of the capacitor C5, and the output end of the sound pickup circuit is grounded;
the band-pass filter amplifier comprises a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C0, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a first amplifier and a second amplifier, wherein one end of the resistor R0 is used as an input end of the band-pass filter amplifier and is connected with an output end of a pickup circuit, the other end of the resistor R0 is respectively connected with one end of the resistor R1 and one end of the capacitor CO, the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and one end of the capacitor C2, the other end of the capacitor C2 is respectively connected with one end of the resistor R2 and one end of the positive input end of the first amplifier, the negative input end of the first amplifier is respectively connected with one end of the resistor R5 and one end of the resistor R6, the other end of the output end of the first amplifier is respectively connected with one end of the resistor R5 and one end of the capacitor C3, the other end of the capacitor C3 is respectively connected with one end of the positive input end of the second amplifier, the negative end of the second amplifier is respectively connected with one end of the resistor C3 and one end of the resistor C3, and the other end of the resistor C4 is respectively connected with one end of the resistor C4 and the other end of the resistor C4 and the other end of the resistor C4 is respectively connected with the other end of the resistor C4.
3. The acousto-optic control circuit according to claim 1, wherein: one end of the photoresistor is grounded, and the other end of the photoresistor is used as an output end of the photoresistor;
the photoresistor detection circuit comprises a current source, a resistor R10, a resistor R11, a capacitor C6 and a capacitor C7, wherein one end of the current source is connected with the VDD end of an external power supply, the other end of the current source is connected with the output end of the photoresistor and one end of the capacitor R10 respectively, the other end of the resistor R10 is connected with one end of the capacitor C6 and one end of the resistor R11 respectively, and the other end of the resistor R11 is connected with one end of the capacitor C7 and serves as the output end of the photoresistor detection circuit.
4. The acousto-optic control circuit according to claim 1, wherein: the driving circuit comprises a fourth AND gate, a fifth AND gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a PMOS pipe P2 and an NMOS pipe N2, wherein the first input end of the fourth AND gate is connected with the input end of the fourth NOT gate and serves as the input end of the driving circuit, the second input end is respectively connected with the output end of the tenth NOT gate and the input end of the eleventh NOT gate, the output end of the fourth NOT gate is connected with the input end of the fifth NOT gate, the first input end of the fifth AND gate is respectively connected with the output end of the sixth NOT gate and the input end of the seventh NOT gate, the output end of the fifth NOT gate is connected with the input end of the ninth NOT gate, the output end of the fifth NOT gate is connected with the input end of the eighth NOT gate, the output end of the seventh NOT gate is connected with the PMOS pipe P2, the output end of the seventh NOT gate is connected with the drain of the eighth NOT gate, the output end of the PMOS pipe P2 is connected with the drain of the eighth NOT gate.
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| CN209120520U (en) * | 2018-08-31 | 2019-07-16 | 无锡麟力科技有限公司 | A kind of acousto-optic controlled circuit |
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