JP2001118993A - Power supply voltage detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the voltage level of low-voltage power, without increasing power consumption in a semiconductor device having at lest two power supply voltages different in voltage levels. SOLUTION: The input part of a CMOS inverter 803 is connected to a low voltage power source 801, and CMOS inverter output corresponding to the voltage level of the low voltage power source 801 is outputted. Thus, the voltage level of low voltage power source 801 is detected. The operating voltage supply part of the CMOS inverter 803 is connected to a high voltage power source 802 through voltage drop means 806 and 807, so that the voltage of the level lower than the voltage level of the high voltage power source 802 is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power supply voltage detection circuit, and more particularly to a power supply voltage detection circuit used in a semiconductor device having at least two power supply voltages.

[0002]

2. Description of the Related Art In recent years, a power supply voltage of an LSI internal circuit has been reduced to 1.8 V or lower due to a demand for lower power consumption of electronic equipment and a reduction in transistor breakdown voltage due to miniaturization of a process. . Accordingly, while the power supply voltage of the internal circuit is 1.8 V or lower, the interface with the LSI peripheral element is 3.3 V.
Due to the operation, there is a case where it is required to output a 3.3V amplitude, and one LSI requires two or more different power supply voltages. In this case, for example, in a level shift circuit that realizes a signal from the low-voltage operation circuit or the low-voltage operation semiconductor device to the high-voltage operation circuit or the high-voltage operation semiconductor device, the power supply of the low-voltage operation circuit is improper for some reason. When the circuit becomes stable or cuts off, a through current flows in the level shift circuit and the output signal becomes unstable, causing malfunction of other circuits or, in some cases, a large current flowing. May cause problems. In order to prevent this, a configuration is adopted in which, when the power supply of the low-voltage operation circuit is cut off, a circuit for preventing a through current in the level shift circuit and fixing the output thereof is added to the level shift circuit. ing.

FIG. 4 shows an example of a conventional level shift circuit which prevents a through current in the level shift circuit and fixes its output when the power supply to the low voltage operation circuit is cut off. It will be explained based on this. Where 501
Is an input signal terminal from a low voltage (for example, 1.8 V) operation circuit, and 502 is an output terminal to a high voltage (for example, 3.3 V) operation circuit. 503 is a high voltage power supply (for example, 3.
3V). Inverters 504 and 505 operate on a low-voltage power supply (for example, 1.8 V).

Reference numeral 506 denotes an N-channel MOS transistor which receives a signal from an input signal terminal 501 at its gate via low voltage power supply operation inverters 504 and 505, and uses a ground power supply as a source. Reference numeral 507 denotes an N-channel MOS transistor, which receives a signal having a phase opposite to that of the signal from the input signal terminal 501 at the gate via only the low-voltage power supply operation inverter 504, uses the ground power supply as a source, and connects the drain to Connected to source.

[0005] 509, 510 and 511 are P-channel MOS transistors whose sources are connected to the high voltage power supply terminal 503. The drain of P-channel MOS transistor 510 and the drain of N-channel MOS transistor 506 are connected to each other, and an intermediate node 514 is provided therebetween.
Are formed, and the drain of P-channel MOS transistor 509 and the drain of N-channel MOS transistor 508 are connected to each other so that intermediate node 515 is provided therebetween.
Is formed. P-channel MOS transistor 509
Is connected to the intermediate node 514. The intermediate node 515 is connected to the output signal terminal 502 via an inverter 512 operated by a high voltage power supply (3.3 V).

An intermediate node 515 has a gate of a P-channel MOS transistor 510 and a P-channel MOS transistor 510.
The drain of the S transistor 511 is connected.
The gate of N-channel MOS transistor 508 and the gate of P-channel MOS transistor 511 are connected to control input terminal 513. The operation of the level shift circuit configured as described above will be described below.

When the power (1.8 V) of the low-voltage operation circuit is supplied (hereinafter referred to as “active”),
First, when the voltage of the input signal terminal 501 from the low-voltage operation circuit is at the H level (1.8 V), the output of the low-voltage power supply operation inverter 504 is 0 V, and the output of the low-voltage power supply operation inverter 505 is 1.8 V. is there. At this time, N-channel MOS transistor 506 is on and N-channel MOS transistor 507 is off. Also, N
Since the channel MOS transistor 506 is on, the intermediate node 514 is at 0 V,
The transistor 509 is on.

When active, 3.3 V is input to control input terminal 513, and at this time, an N-channel MOS
The transistor 508 is on, and the P-channel MO
S transistor 511 is off. At this time, since P-channel MOS transistor 509 is on, intermediate node 515 has the same potential as high-voltage power supply terminal 503 at 3.3 V, and P-channel MOS transistor 510 is off. The output voltage of the high-voltage power supply operation inverter 512 becomes 0 V, and the L level is output to the output terminal 502.

An H level (1.8) is input to an input signal terminal 501.
When a signal that changes from V) to the L level (0 V) is input, the output of the low-voltage power supply operation inverter 504 changes from 0 V to 1.8 V, and the output of the low-voltage power supply operation inverter 505 changes from 1.8 V to 0 V. Changes to Accordingly, N-channel MOS transistor 506 shifts from on to off, and N-channel MOS transistor 507 shifts from off to on. As the N-channel MOS transistor 507 shifts to the ON state, the potential of the intermediate node 515 drops, and the P-channel MOS transistor 510 turns on. At the same time, the potential of intermediate node 514 rises, and P-channel MOS transistor 509 starts to turn off. In these operations, the intermediate node 514 has the same potential as the high-voltage power supply terminal 503 at 3.3 V, and
The process ends when the intermediate node 515 is completely at 0V and the output of the high-voltage power supply operation inverter 512 is completely at 3.3V. That is, the potential of the output signal terminal 502 becomes 3.3 V, and an H level is output.

When a signal that changes from the L level (0 V) to the H level (1.8 V) is input to the input signal terminal 501, the operation reverses to the above, and the potential of the output signal terminal 502 becomes 0 V. The L level is output. With the above operation, the output signal terminal 502 is connected to the input signal terminal 50.
1 and a signal having a phase opposite to that of the signal to 1. The amplitude of this signal is 3.
It becomes 3V, and a level shift operation is performed.

When the power supply of the low-voltage operation circuit is not supplied from the active state, that is, the state shifts to the sleep state, the potential of the control input terminal 513 is set to 0V. At this time, N-channel MOS transistor 508 is off, and P-channel MOS transistor 511 is on. Therefore, even when the voltage of the input signal terminal 501 is undefined, the potential of the intermediate node 515 is 3.3 V
, And the P-channel MOS transistor 510 is turned off, so that it is possible to prevent a steady current from flowing from the high voltage power supply terminal 503 via the P-channel MOS transistor 510 to increase power consumption. At the same time, the output terminal 502 is fixed at the L level (0 V) and does not become unstable.

In the configuration of the conventional level shift circuit,
It is necessary to input a signal indicating that the power supply of the low-voltage operation circuit is turned off from the control input terminal 513 to the level shift circuit by some means. The specification of inputting this signal from the outside is a problem that must be considered on the side using the LSI. In order to solve this problem, it is necessary to provide a means for detecting the voltage level of the power supply of the low-voltage circuit inside the LSI.

[0013]

An example of the means for detecting the voltage level of the power supply of the low-voltage circuit will be described with reference to FIG. Reference numeral 601 denotes a terminal of a low-voltage power supply (for example, 1.8 V). 602 and 603 are resistors connected in series between the high voltage power supply terminal 503 and the ground power supply. 604
Adjusts the resistance value of the resistor 602 and the resistance value of the resistor 603 at an internal node between the resistor 602 and the resistor 603 so that an arbitrary voltage between the high-voltage power supply (3.3 V) and the ground power supply is adjusted. I can make it. Reference numeral 605 denotes a comparator that operates on the high voltage power supply, compares the voltage level of the low voltage power supply 601 with the voltage level of the internal node 604, and outputs the result from the output signal terminal 606 at an L level or an H level.

However, in this case, a problem arises in that current constantly flows from the high voltage power supply terminal 503 to the ground power supply via the resistors 602 and 603, and power consumption increases. Another example of the means for detecting the voltage level of the power supply of the low-voltage circuit will be described with reference to FIG. 613, a CMOS inverter functioning as a logic gate;
It comprises a channel type MOS transistor 611 and a P channel type MOS transistor 612, the input of which is connected to the low voltage power supply terminal 601 and the output thereof is connected to the output signal terminal 606, and the source of the P channel type MOS transistor 612 has a high voltage. The power supply terminal 503 is connected.

With this configuration, the terminal 601 is set by setting the inversion level of the CMOS inverter 613 to an appropriate value according to the voltage level input to the terminal 601.
, The voltage level of the power supply of the low-voltage circuit input to the low-voltage circuit can be detected. However, in this case, the P-channel type M
The threshold voltage of the OS transistor 612 is set to 0.5 V, N
Assuming that the threshold voltage of channel type MOS transistor 611 is 0.4 V, even if the voltage level of low voltage power supply 601 is 1.8 V, which is the original voltage level, N channel type MOS transistor 611 is on. Since the P-channel type MOS transistor 612 is also in the ON state, similarly, a current constantly flows from the high voltage power supply terminal 503 to the ground power supply via the CMOS inverter 613, which causes a problem that power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a circuit capable of detecting a voltage level of a low-voltage power supply without increasing power consumption.

[0017]

In order to solve the above-mentioned problems, a power supply voltage detecting circuit according to the present invention has a structure in which an input section of a CMOS inverter is connected to a low-voltage power supply and the input voltage of the CMOS inverter is adjusted according to the voltage level of the low-voltage power supply. Output from the CMOS inverter to detect the voltage level of the low-voltage power supply, and the operating voltage supply unit of the CMOS inverter is connected to the high-voltage power supply via voltage dropping means. And a voltage lower than the voltage level of the high-voltage power supply is supplied.

With such a configuration, the area of the semiconductor device is slightly increased by arranging the power supply voltage detection circuit inside the semiconductor device. However, the output of the power supply voltage detection circuit is controlled by the low voltage operation circuit. When the power supply is cut off, the power supply to the low-voltage operation circuit is prevented for some reason by inputting it to the control terminal of a level shift circuit equipped with a circuit that prevents through current in the level shift circuit and fixes its output. When the semiconductor device becomes unstable or has been cut off, there is no need to consider a signal indicating that the power supply of the low-voltage operation circuit is cut off on the side using the semiconductor device. In addition, since the operating voltage supply unit is connected to the high voltage power supply via the voltage drop unit, a voltage at a level lower than the voltage level of the high voltage power supply is configured to be supplied. Without increasing the power, a through current flows in the level shift circuit, or the output signal becomes unstable and malfunctions in other circuits, and in some cases, a large current flows in other circuits. And the like can be prevented from occurring.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The means specifically adopted in the first aspect of the present invention detects a power supply voltage of a semiconductor device including a low-voltage power supply and a high-voltage power supply having a higher voltage level than the low-voltage power supply. A circuit constituted by a CMOS inverter to output a CMOS inverter output corresponding to the voltage level of the low-voltage power supply when an input section of the CMOS inverter is connected to the low-voltage power supply; Thereby, the voltage level of the low-voltage power supply is configured to be detected, and the operating voltage supply unit of the CMOS inverter includes:
By being connected to the high-voltage power supply via a voltage drop means, an operation voltage having a lower level than the voltage level of the high-voltage power supply is supplied.

With such a configuration, the area of the semiconductor device is slightly increased by disposing the power supply voltage detection circuit inside the semiconductor device. When the power supply is cut off, the power supply to the low-voltage operation circuit is prevented for some reason by inputting it to the control terminal of a level shift circuit equipped with a circuit that prevents through current in the level shift circuit and fixes its output. When the semiconductor device becomes unstable or has been cut off, there is no need to consider a signal indicating that the power supply of the low-voltage operation circuit is cut off on the side using the semiconductor device. In addition, since the operating voltage supply unit is connected to the high voltage power supply via the voltage drop unit, a voltage at a level lower than the voltage level of the high voltage power supply is configured to be supplied. Without increasing the power, a through current flows in the level shift circuit, or the output signal becomes unstable and malfunctions in other circuits, and in some cases, a large current flows in other circuits. And the like can be prevented from occurring.

Specifically, the means taken by the invention of claim 2 is as follows:
2. The CMOS inverter according to claim 1, comprising:
An OS inverter, a second CMOS inverter having an input connected to the output of the first CMOS inverter, and an input connected to the output of the second CMOS inverter; A third CMOS inverter having an output connected to the output of the CMOS inverter and the input of the second CMOS inverter;
A feedback circuit is formed by the third CMOS inverter, and the feedback circuit raises the voltage level of the low-voltage power supply connected to the input section of the first CMOS inverter. Than the voltage level of the low voltage power supply when the output is inverted,
When the voltage level of the low-voltage power supply decreases, the voltage level of the low-voltage power supply becomes lower when the output of the first CMOS inverter is inverted.

With such a configuration, malfunctions can be reduced by the action of the feedback circuit for giving the input a Schmitt width. Specifically, in a semiconductor device provided with a plurality of input cells and output cells, a wiring connected to an output terminal of the power supply voltage detection circuit according to claim 1 or 2 is provided for each cell. Are provided so that one power supply voltage detection circuit can be shared by a plurality of cells.

With this configuration, the total layout area of the circuits can be reduced as compared with the case where the power supply voltage detection circuits are provided corresponding to the respective level shift circuits and the like. (First Embodiment) FIG. 1 shows a power supply voltage detection circuit according to a first embodiment of the present invention. In the figure, reference numeral 801 denotes a power supply terminal connected to a low-voltage power supply (for example, 1.8 V), and 802 denotes a power supply terminal connected to a high-voltage power supply (for example, 3.3 V). Reference numeral 803 denotes a CMOS inverter functioning as a logic gate, which includes an N-channel MOS transistor 804 and a P-channel MOS transistor 805, and has an input connected to the low-voltage power supply terminal 801.

The source of the P-channel MOS transistor 805 of the CMOS inverter 803 is a P-channel MOS transistor 806 and a P-channel MOS transistor 806.
The transistor 807 is connected to a high-voltage power supply terminal 802. The gate of this P-channel MOS transistor 806 is
6, and the gate of the P-channel MOS transistor 807 is connected to the drain of the P-channel MOS transistor 807.

Reference numeral 808 denotes a CMO functioning as a logic gate.
The S inverter is composed of an N-channel MOS transistor 809 and a P-channel MOS transistor 810, and its input is connected to the output of the CMOS inverter 803. P of this CMOS inverter 808
The source of the channel MOS transistor 810 is connected to a high-voltage power supply terminal 802 via a P-channel MOS transistor 811. This P channel type MO
The gate of the S transistor 811 is a P-channel MOS
It is connected to the drain of the transistor 811.

Reference numeral 812 denotes a CMO functioning as a logic gate.
The S inverter is composed of an N-channel MOS transistor 813 and a P-channel MOS transistor 814, the input of which is connected to the output of the CMOS inverter 808, and the output of which is connected to the signal output terminal 815. The source of the P-channel MOS transistor 814 is connected to the high voltage power supply terminal 802.

The operation of the power supply voltage detecting circuit configured as described above will be described below with reference to FIG. First, the voltage of the high-voltage power supply at the power supply terminal 802 is 3.3 V as described above, and the P-channel MOS transistors 805, 806, 807, 810, 811, 8
14, the threshold voltage of the power supply terminal 801 is set to 0.5V.
The case where the voltage level of the low-voltage power supply is higher than 2.8 V will be described. That is, a case where the voltage of the power supply terminal 801 is higher than a value obtained by subtracting the voltage of the threshold value (0.5 V) from the voltage (3.3 V) of the power supply terminal 802 will be described.

At this time, the N-channel MOS transistor 804 is completely turned on, and the P-channel MOS transistor 804 is turned on.
The transistor 805 is completely off. Therefore,
The output potential of the CMOS inverter 803 becomes 0 V, and C
The L level is output from the signal output terminal 815 by the operation of the MOS inverters 808 and 812. At this time, since the P-channel MOS transistors 805 and 814 and the N-channel MOS transistor 809 are off,
No substantial through current flows through the CMOS inverters 803, 808, 812.

Next, the voltage level of the low-voltage power supply is 2.8.
A case where the voltage is equal to or lower than V and higher than 1.8 V which is a normal voltage of the low-voltage power supply will be described. At this time, the N-channel MOS transistor 804 is on. At this time, the gate and the drain of the P-channel MOS transistor 807 are connected,
Since the gate and the drain of the channel type MOS transistor 806 are also connected, the potential of the source of the P-channel type MOS transistor 805 is 2.3 V, so that the P-channel type MOS transistor 805 is in an off state with a weak leakage current. Becomes As a result, a weak through current flows through the CMOS inverter 803. Also CMO
The output of the S inverter 803 becomes 0 V, and the operation of the CMOS inverters 808 and 812 causes the signal output terminal 815 to operate.
Output the L level. At this time, since the P-channel MOS transistor 814 and the N-channel MOS transistor 809 are in the off state, almost no through current flows through the CMOS inverters 808 and 812.

Next, an N-channel MOS transistor 8
The case where the voltage level of the low-voltage power supply is lower than 0.4 V when the threshold voltage of No. 04 is 0.4 V will be described. At this time, the N-channel MOS transistor 804 is in an off state with a weak leakage current. P-channel type M
Since the gate and the drain of the OS transistor 807 are connected and the gate and the drain of the P-channel MOS transistor 806 are connected, the potential of the source of the P-channel MOS transistor 805 is 2.3 V
Becomes At this time, the P-channel MOS transistor 8
Reference numeral 05 denotes an ON state, and a weak through current flows through the CMOS inverter 803. The output of the CMOS inverter 803 becomes 2.3V.

As a result, the input of CMOS inverter 808 becomes 2.3 V, so that the N-channel type MOS
The transistor 809 is on. P-channel type M
Since the gate and the drain of the OS transistor 811 are connected, the potential of the source of the P-channel MOS transistor 810 is set to 2.
8V, and this P-channel MOS transistor 81
0 turns off. Therefore, the output of the CMOS inverter 808 becomes 0 V, and the CMOS inverter 812
The operation from the signal output terminal 815 to the H level (3.3
V) is output. At this time, as described above, the P-channel type MOS transistor 810 is turned off,
Since the output of the S inverter 808, that is, the input of the CMOS inverter 812 is 0 V, the N-channel type MO
Since the S transistor 813 is also off, the CMOS
Almost no through current flows through inverters 808 and 812.

Next, the voltage level of the low-voltage power supply is 0.4 V
The case where the voltage is 1.8 V or less, that is, the case where the determination of the potential of the low-voltage power supply connected to the power supply terminal 801 is performed by switching the CMOS inverter 803 will be described. In this case, the CMOS inverter 803
Is set to the judgment voltage, when the potential of the low-voltage power supply is higher than the switching level of the CMOS inverter 803, the CMOS inverter 80
3, 808 and 812, the signal output terminal 815
Output an L level (0 V). When the potential of the low-voltage power supply is lower than the switching level of the CMOS inverter 803, the CMOS inverters 803, 808,
By the operation of 812, the H level (3.3 V) is output from the signal output terminal 815.

As described above, according to the present embodiment, almost no through current flows, so that the potential of the low-voltage power supply can be detected without increasing power consumption. In the above example, by setting the normal potential of the low-voltage power supply to be higher than 1.8 V, a voltage detection circuit in which only a weak through current flows even in the normal mode can be configured.

The original voltage of the low-voltage power supply is 1.8 V,
If the values of the high-voltage power supply voltage 3.3 V, the threshold voltage of the P-channel MOS transistor 0.5 V, and the threshold voltage of the N-channel MOS transistor 0.4 V change, the CMOS inverter and the high voltage The number of P-channel MOS transistors connected in series between the power supply terminal and the gate and the drain, and the number of CMOS inverters from the low-voltage power supply terminal 801 to the signal output terminal 815 connected to the low-voltage power supply Similarly, by changing the number of stages, a through current hardly flows, and therefore a circuit capable of detecting the potential of the low-voltage power supply without increasing power consumption can be configured. Also, a MOS transistor interposed between the CMOS inverter and the high-voltage power supply terminal is:
P-channel type MO with gate and drain connected as described above
Instead of the S transistor, an N-channel MOS transistor whose gate and drain are connected can be used. Furthermore, instead of these MOS transistors,
A diode element or the like can be used.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described with reference to the power supply voltage detection circuit of FIG. In the power supply voltage detection circuit of the present embodiment, a feedback circuit is added to the power supply voltage detection circuit of the first embodiment shown in FIG. In FIG. 2, reference numeral 821 denotes a feedback circuit, which is an N-channel MOS transistor 822 and a P-channel MOS transistor 822.
CM composed of channel type MOS transistor 823
An OS inverter 824, a high-voltage power supply terminal 802, and a P-channel MOS transistor 825 and a P-channel MOS transistor 826 interposed between the high-voltage power supply terminal 802 and the P-channel MOS transistor 823. ing. CMOS inverter 824
Is connected to the output of the CMOS inverter 808,
The output of the CMOS inverter 824 is connected to the input of the CMOS inverter 808. The gate of the P-channel MOS transistor 825 is connected to the drain of the P-channel MOS transistor 825,
The gate of the S transistor 826 is connected to the drain of the P-channel MOS transistor 826.

The other configuration is the same as that of the power supply voltage detecting circuit shown in FIG. 1. The portions having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. . The operation of the power supply voltage detection circuit configured as described above will be described below with reference to FIG.

When the voltage level of the low-voltage power supply at the low-voltage power supply terminal 801 is 1.8 V, which is the highest level for performing the potential determination by switching the CMOS inverter 803, that is, when the input voltage level of the CMOS inverter 808 is 0 V In this case, since the gate and the drain of P-channel MOS transistor 811 are connected, the potential of the source of P-channel MOS transistor 810 is 2.8 V, and CMOS inverter 808
Has an output voltage level of 2.8V. At this time, the N-channel type M of the CMOS inverter 824 of the feedback circuit 821 is used.
The OS transistor 822 is on, and the P-channel MOS transistor 823 is off.

At this time, paying attention to the CMOS inverter 803, the N-channel MOS transistor 804 is turned on and the N-channel MOS transistor 8 connected to the output side of the CMOS inverter 803 is turned on.
22 is also in the ON state, the voltage level of the low-voltage power supply drops, and the input voltage of the CMOS inverter 808 becomes 0V.
The voltage level of the low-voltage power supply at the time of inverting the voltage to 2.3 V is lower than that in the first embodiment. Then, the input voltage of the CMOS inverter 808 is changed from 0V to 2.3.
When inverted to V, the CMOS inverter 808 operates, and the N-channel MOS transistor 822 shifts to the off state. At the same time, an H level (3.3 V) is output from the signal output terminal 815 via the CMOS inverter 812.

When the voltage level of the low-voltage power supply at the low-voltage power supply terminal 801 is 0.4 V, which is the minimum level for performing the potential determination by switching the CMOS inverter 803, the output voltage level of the CMOS inverter 808 is 0V. It is. At this time, the N-channel MOS transistor 822 of the CMOS inverter 824 of the feedback circuit 821 is off, and the P-channel MOS transistor 823 is on. The gate and the drain of the P-channel MOS transistor 826 are connected, and the P-channel MOS transistor 8
25 also has a gate and a drain connected, so that the source potential of P-channel MOS transistor 823 is 2.3 V, and therefore, CMOS inverter 824
Has an output voltage level of 2.3V.

At this time, paying attention to the CMOS inverter 803, the P-channel MOS transistor 805 is turned on and the P-channel MOS transistor 8 connected to the output side of the CMOS inverter 803 is turned on.
23 is also in the ON state, the voltage level of the low-voltage power supply rises, and the input voltage of the CMOS inverter 808 becomes 2.
The voltage level of the low-voltage power supply that reverses from 3V to 0V is higher than in the case of the first embodiment. When the input voltage of the CMOS inverter 808 is inverted from 2.3 V to 0 V, the CMOS inverter 808 operates.
Since the gate and the drain of the channel type MOS transistor 811 are connected to each other, the source potential of the P-channel type MOS transistor 810 becomes 2.8 V.
The output of the OS inverter 808 is 2.8V. At the same time, the P-channel MOS transistor 823 shifts to the off state, and the L level (0 V) is output to the signal output terminal 815 via the CMOS inverter 812.

When the voltage level of the first power supply is higher than 2.8 V, the voltage level is lower than 2.8 V and higher than 1.8 V;
If it is lower than V, the operation is the same as that of the first embodiment shown in FIG. Also in the present embodiment, since almost no through current flows, the potential of the low-voltage power supply can be detected without increasing power consumption.

Further, as compared with the first embodiment, the number of elements is slightly increased, the area is increased, and the provision of the feedback circuit 801 makes it possible to determine whether the power supply has started at one switching level. Although sensitive detection is not possible, the input can have a Schmitt width.
Even if the voltage level of the low-voltage power supply becomes transiently unstable near the switching level, the output of the terminal 815 does not alternately change between the L level and the H level.

(Third Embodiment) FIG. 3 is a configuration diagram for explaining a circuit layout structure of a power supply voltage detection circuit according to a third embodiment of the present invention, and FIG. FIG. 2B is a schematic view of the entire device, and FIG. 2B is an enlarged view for explaining the configuration of the IO cell unit in FIG. Here, a configuration example is shown in which the internal logic circuit region of the semiconductor device operates at a low voltage and the interface voltage with the outside of the semiconductor device has a high voltage potential amplitude. In FIG. 3, reference numeral 901 denotes a low-voltage power supply line in the IO cell unit; 902, a line connected to the output terminal of the power supply voltage detection circuit of the first or second embodiment; 904, a high-voltage power supply line in the IO cell portion, and 905, a wire bonding pad.

A circuit for level-shifting the amplitude of the low-voltage operation circuit inside the LSI to the amplitude of the external high-voltage operation circuit is generally arranged in each IO cell unit, but is connected to the output terminal of the power supply voltage detection circuit. 902 is provided in each IO cell unit in advance, and wiring is connected only by arranging the cells, thereby preventing a through current in the level shift circuit when the power supply of the low voltage operation circuit is cut off. By inputting the output to the control terminal of a level shift circuit having a circuit for fixing the output, one power supply voltage detection circuit can be shared by each IO cell, thereby reducing the layout area and the development period. realizable.

[0045]

As described above, according to the power supply voltage detection circuit of the present invention, by arranging the power supply voltage detection circuit inside the LSI, the area of the LSI is slightly increased. To a control terminal of a level shift circuit having a circuit for preventing a through current in the level shift circuit and fixing its output when the power supply of the low voltage operation circuit is cut off, thereby providing a low voltage operation circuit. When the power supply of the LSI becomes unstable or cut off for some reason, there is an advantage that it is not necessary for the side using the LSI to consider a signal indicating that the power supply of the low-voltage operation circuit is cut off. . Not only that, since the operating voltage supply unit is connected to the high-voltage power supply through the voltage drop unit, a voltage of a lower level than the voltage level of the high-voltage power supply is configured to be supplied. , Through current flows in the level shift circuit without increasing power consumption,
In addition, there is an effect that it is possible to prevent a malfunction such as a malfunction occurring in another circuit due to an unstable output signal or a large current flowing in another circuit in some cases.

Further, according to the circuit layout structure of the present invention, in addition to the above-mentioned effects, the power supply voltage detection circuit is shared, so that the layout work can be saved and the area of the semiconductor device can be reduced. be able to.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power supply voltage detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a power supply voltage detection circuit according to a second embodiment of the present invention.

FIG. 3 is a view for explaining a third embodiment of the present invention;
FIG. 3 is a configuration diagram of a circuit layout structure of a power supply voltage detection circuit.

FIG. 4 is a circuit diagram showing an example of a configuration of a conventional level shift circuit.

FIG. 5 is a circuit diagram showing an example of a conventional power supply voltage detection circuit.

FIG. 6 is a circuit diagram showing another example of a conventional power supply voltage detection circuit.

[Explanation of symbols]

801 Low voltage power supply terminal 802 High voltage power supply terminal 803 CMOS inverter 804 N-channel type MOS transistor 805, 806, 807 P-channel type MOS transistor 821 Feedback circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G035 AA09 AA15 AB02 AC13 AC15 AD02 AD03 AD10 AD23 AD47 5F038 CD02 DF07 DF11 DT10 DT12 EZ20 5J056 AA00 BB17 BB18 DD13 DD29 EE07 EE11 EE12 FF08 KK02

Claims (3)

[Claims] 1. A circuit comprising a CMOS inverter for detecting a power supply voltage of a semiconductor device having a low-voltage power supply and a high-voltage power supply having a higher voltage level than the low-voltage power supply, When the input of the CMOS inverter is connected to the low-voltage power supply, a CMOS inverter output corresponding to the voltage level of the low-voltage power supply is output, whereby the voltage level of the low-voltage power supply can be detected. The operating voltage supply unit of the CMOS inverter is configured to be connected to the high voltage power supply via a voltage drop unit, so that an operation voltage of a level lower than the voltage level of the high voltage power supply is supplied. A power supply voltage detection circuit, comprising: 2. The CMOS inverter according to claim 1, wherein said CMOS inverter is a first CMOS inverter.
Second CM having an input connected to the output of the S inverter
An OS inverter is provided, and an input unit is connected to an output unit of the second CMOS inverter.
A third CMOS inverter having an output connected to the output of the MOS inverter and the input of the second CMOS inverter is provided, and a feedback circuit is formed by the third CMOS inverter. The voltage level of the low-voltage power supply connected to the input portion of the first CMOS inverter is higher than the voltage level of the low-voltage power supply when the output of the first CMOS inverter is inverted due to an increase in the voltage level of the low-voltage power supply. 2. The power supply voltage according to claim 1, wherein the voltage level of said low-voltage power supply when the output of said first CMOS inverter is inverted due to a decrease in the voltage level is lower. Detection circuit. 3. A semiconductor device having a plurality of input cells and output cells, wherein a wiring connected to an output terminal of the power supply voltage detection circuit according to claim 1 is provided in each cell, so that one power supply is provided. A circuit layout structure wherein a voltage detection circuit is configured to be shared by a plurality of cells.