JP4435790B2 - Semiconductor circuit and power-on reset device - Google Patents

Description

  The present invention relates to a semiconductor circuit of various portable devices using a secondary battery and a power-on reset device having the semiconductor circuit.

Conventionally, as a power-on reset circuit that automatically resets an electronic device when the power is turned on, a resistor and a capacitor are connected in series between the power source and the ground, and a reset output line is connected to the midpoint of the resistor and capacitor via a buffer. There is something to connect.
By turning on the power, the potential at the midpoint was raised based on the time constant of the resistor and capacitor, and when the potential became constant, a reset signal was output from the buffer to the output line. .

However, in order to increase the time constant, it is necessary to use a high resistance. In the case of a high resistance, there is a risk of malfunction if noise is present. In addition, the reset signal may become unstable due to power fluctuation.
Therefore, in order to stably generate the reset signal, for example, a power-on reset circuit described in Japanese Patent Application Laid-Open No. 2001-292854 has been proposed.

As shown in FIG. 2, the power-on reset circuit described in the above publication includes a detection circuit including transistors N1 and N2, a flip-flop circuit (inverters Np and Nm, and capacitors Cp and Cm) instead of resistors and capacitors. Consists of
In FIG. 2, when the power is turned on, the power supply voltage VDD rises and becomes a saturated value, the MOS transistor N1 is turned on, and the charge of the capacitor Cp is discharged to the ground VSS through the MOS transistors N1 and N2. The input voltage V1 of the flip-flop circuit decreases, and the output voltage Pr of the flip-flop is switched from the L level to the H level. As described above, the circuit shown in FIG. 2 can reliably obtain a reset signal because the stable state is inverted when the detection levels of the detection circuits N1 and N2 become constant values.

  However, in the circuit of FIG. 2, when the power supply voltage rises, the output is changed as in the prior art. Since it is initialized by the capacitors Cp and Cm, a layout area for the capacitors Cp and Cm is required.

Japanese Patent Laid-Open No. 2001-292054

As described above, in the conventional power-on reset device, the reset signal is not output until the voltage at which the transistor operates sufficiently, or the capacitor and the resistor are used as in the technique described in the above publication. In addition, there is a problem that a large layout area for resistors is required.
Therefore, if possible, it is desirable to reduce the number of constituent elements of the power-on reset device and reduce the layout area. In addition, it is necessary not to cause a malfunction even if noise is applied without using a high resistance.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve these conventional problems, and to provide a semiconductor circuit having a reduced number of constituent elements and a reduced layout area, without using capacitors and resistors, and a power-on reset device thereof. It is in.

In order to achieve the above object, a power-on reset device having a semiconductor circuit according to the present invention is characterized by notifying that a value of a power supply voltage at which a transistor is operable has been reached.
The semiconductor circuit of the present invention is characterized in that the characteristics of the power-on reset device are achieved without including a resistance element and a capacitance element.
Further, it is notified that the value of the power supply voltage at which the transistor can operate is notified, and specific control can be performed when the power supply voltage is zero.

In addition, the above characteristics are achieved without including a resistance element and a capacitor element.
Further, it is characterized by comprising P-channel MOS transistors M1 and MP, N-channel MOS transistors M3 and Mn, and a resistor ( depletion MOS transistor M2 ) (see FIG. 1).

  As described above, according to the present invention, it is possible to realize a semiconductor circuit and a power-on reset device thereof having a configuration in which the number of constituent elements is small and the layout area is reduced without using capacitors or resistors. Also, the power supply voltage can reset the circuit at a low voltage level that is insufficient to operate the circuit elements, so prepare an initial state when the power supply rises to a voltage sufficient to operate the transistor. This is advantageous in that it does not cause uncertain movements. In addition, since the above effect can be generated with a small number of transistor components, the layout area of the components can be reduced. Furthermore, in a semiconductor device that operates using a secondary battery as a power source, a predetermined initial state is generated even when the secondary battery is zero to a voltage at which the transistors that constitute the circuit of the semiconductor device can operate. There is an effect that can be.

Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a circuit diagram of a power-on reset device having a semiconductor circuit according to an embodiment of the present invention.
As shown in FIG. 1, the circuit configuration of this embodiment includes a series circuit including a P-channel MOS transistor M1, a depletion MOS transistor M2, and an N-channel MOS transistor M3 between a power source 2 and a ground 3, and a P-channel MOS. It has a configuration in which a transistor MP and an inverter circuit composed of an N-channel MOS transistor Mn are connected in parallel. A power-on reset output line 1 is provided on the source side of the P-channel MOS transistor MP and the source side of the N-channel MOS transistor Mn.

  In this embodiment, an inverter circuit of a P-channel MOS transistor MP and an N-channel MOS transistor Mn having a Pr0 voltage as a gate input, and a P-channel MOS transistor M1 and an N-channel having a Pr00 voltage and a Pr0 voltage as gate inputs, respectively. When a flip-flop is formed with the MOS transistor M3, and a P-channel MOS transistor M1 and an N-channel MOS transistor M3 connected in series with the depletion MOS transistor M2 are similar to a series connection of a resistance element and a capacitive element A constant operating element is formed.

The operation will be described below.
Since the gate of the P-channel MOS transistor M1 is the drain Pr00 of the depletion MOS transistor M2, and the gate of the N-channel MOS transistor M3 is the source Pr0 of the depletion MOS transistor M2 higher than the voltage of Pr00, a power-on reset is performed. The voltage level of Pr0 is an intermediate level between the power supply 2 and the ground 3 until the power supply voltage VDD reaches a specific level, and when the power supply voltage VDD higher than the specific level is supplied to the output line 1, Almost the same H ′ level is output.

  The inverter composed of the P-channel MOS transistor MP and the N-channel MOS transistor Mn receives the Pr0 as an input and uses a voltage higher than the intermediate level of Pr0 as a threshold of the input voltage so that the P-channel MOS transistor MP and the N-channel MOS The transistor size value of the transistor Mn is set. In other words, the output (Pr) 1 of the inverter outputs a 'H' level when the input Pr0 is at an intermediate level, and outputs an 'L' level when the input Pr0 is above the specified level.

Note that the depletion MOS transistor M2 is provided to reduce current consumption and cause a voltage drop, so that the transistor M2 can be replaced with a resistance element or the like.
When used in a power supply device having a standby mode, a transistor that is turned off during standby can be added as a component between the depletion MOS transistor M2 and the ground 3.

  As described above, the power-on reset output 1 can detect that the power supply voltage VDD has exceeded a specific level. Therefore, in the circuit of this embodiment, the number of constituent elements is small and the layout area is reduced. Thus, a power-on reset signal can be generated.

A first feature of the present invention is that, in a power-on reset device that generates a signal when the power supply of the power supply device rises, the value of the power supply voltage becomes a value that enables the P-channel MOS transistor and the N-channel MOS transistor to operate. It has an output means to inform.
According to the first feature, when the power supply voltage rises to a voltage sufficient to operate the transistor, the circuit can be reset at a low voltage level that is insufficient to operate the circuit element. The initial state can be prepared in the above, and as a result, there is an effect that an uncertain operation is not caused.

The second feature of the present invention is that in the semiconductor circuit described above, the power supply voltage can be operated by a P-channel MOS transistor and an N-channel MOS transistor without including a resistor element and a capacitor element, for example, by a transistor element or the like. The means for notifying that the value is reached is configured.
According to the second feature, since the effect of the first feature can be generated with a small number of transistor constituent elements without including a resistance element and a capacitor element, the layout area of the constituent elements can be reduced.

According to a third aspect of the present invention, in a semiconductor device that controls charging / discharging of a secondary battery, means for performing a specific control when the power supply voltage is zero, informing that the value of the power supply voltage at which the transistor is operable is reached. It is to have.
In a semiconductor device that operates using a secondary battery as a power source, a predetermined initial state is generated even when the voltage of the secondary battery is zero to a voltage at which a transistor constituting the circuit of the semiconductor device can operate. Can do.

A fourth feature of the present invention is that the semiconductor circuit having the third feature achieves the above characteristics without including a resistance element and a capacitance element.
A fifth feature of the present invention is that the above characteristics are achieved by the circuit configuration shown in FIG.
According to the 4th and 5th characteristic, there exists the completely same effect as the said matter.

It is a circuit block diagram of the power-on reset apparatus which has a semiconductor circuit which shows one Example of this invention. It is a circuit block diagram of the conventional power-on reset circuit.

Explanation of symbols

1: Power-on reset output line 2: Power supply 3: Ground M1, Mp: P channel MOS transistor M3, Mn: N channel MOS transistor M2: Depletion MOS transistor VDD: Power supply voltage VSS: Ground voltage Pr0: Inverter circuit input voltage Pr00: Gate input voltage of the P-channel MOS transistor M1

Claims (2)

A first P-channel MOS transistor, a resistor, and a first N-channel MOS transistor are connected in series between a power supply and a ground, and the gate of the first P-channel MOS transistor is connected to one terminal of the resistor. And the gate of the first N-channel MOS transistor is connected to the other terminal of the resistor, and the voltage of the other terminal of the resistor is maintained until the voltage of the power source reaches a predetermined voltage. When the voltage of the power supply becomes equal to or higher than the predetermined voltage, the voltage of the power supply is approximately the same as the voltage of the power supply,
The second P-channel MOS transistor comprises a second P-channel MOS transistor and a second N-channel MOS transistor having the drain output of the first P-channel MOS transistor and the voltage of the other terminal of the resistor as gate inputs. An inverter circuit having an output terminal between the drain of the MOS transistor and the drain of the second N-channel MOS transistor;
When the threshold value of the inverter circuit is set higher than the intermediate level voltage between the power supply voltage and the ground voltage, and the voltage at the other terminal of the resistor is the intermediate voltage between the power supply voltage and the ground voltage. Has a semiconductor circuit characterized in that the 'H' level is output from the output terminal of the inverter circuit when the voltage at the other terminal of the resistor is equal to or higher than the threshold value. Power-on reset device. 2. The power-on reset circuit according to claim 1, further comprising a transistor that is turned off during standby when used in a power supply device having a standby mode.

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