CN102291109B - Power-on reset circuit of digital integrated circuit supplied with power by chip internal regulator - Google Patents
Power-on reset circuit of digital integrated circuit supplied with power by chip internal regulator Download PDFInfo
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Abstract
The invention discloses a power-on reset circuit of a digital integrated circuit supplied with power by a chip internal regulator. The power-on reset circuit comprises a reference source generator, a regulator, a digital kernel, a hysteresis sampling voltage comparator, a filtering and shaping output circuit and a level shifter, wherein the hysteresis sampling voltage comparator, the filtering and shaping output circuit and the level shifter are connected with VDD-H (Voltage Drain Device-High); the reference source generator is used for generating a VREF (Voltage Reference) for the regulator through the VDD-H; the regulator is used for generating VDD-L (Voltage Drain Device-Low) which is proportional to the VREF for the digital kernel through the VDD-H; the hysteresis sampling voltage comparator is used for inputting connection VREF, VDD-L and PORB-H (Power-On Reset Bearer-High) and outputting connection VCMP (Virtual Clustered Multiprocessing); the filtering and shaping output circuit is used for inputting connection VCMP and outputting connection PORB-H; and the level shifter is used for inputting connection PORB-H and outputting connection PORB-L (Power-On Reset Bearer-Low) into the digital kernel. The power-on reset circuit is insensitive to the power-on speeds or gradients of the VDD-H and the VDD-L, and the voltage of the VDD-L can be accurately set at the end of power-on resetting.
Description
Technical field
The present invention relates to analog to digital composite signal integrated circuits design field, particularly relate to a kind of electrification reset (Power-On-Reset) circuit that passes through the digital integrated circuit of chip internal pressurizer power supply.
Background technology
In digital integrated circuit, the electronic circuit that has a large amount of trigger (Flip-Flop), register and so on, only after the supply voltage of chip reaches certain level, these digital sub-circuit could work, when chip power voltage was lower than certain normal voltage value, the logic of digital circuit just can cause confusion.
After the supply power voltage of chip loads, have a power up, in the middle of this process, the state of the electronic circuits such as the register in the digital circuit can't be determined, need to carry out reset operation, make digital circuit enter into default state after supply voltage reaches normal level, the initialized reset operation of this section needs electrify restoration circuit that the reseting logic signal is provided.
Present deep-submicron semiconductor fabrication process can provide multiple withstand voltage active device simultaneously, in order to improve integrated level, to reduce manufacturing cost, the digital core of general chip all adopts low-voltage device as much as possible, but the effects limit such as the outside environment for use of chip the power supply of chip interface can not arbitrarily reduce, therefore need pressurizer to do step-down and process.Present a large amount of integrated circuit, especially analog to digital composite signal integrated circuits, inside all is to adopt dual power supply, be that chip interface is the High Voltage Power Supplies such as 3.3V, chip internal is by a pressurizer (Regulator) or other step-down controller, produce 1.8V or other low-voltage, give the inner power supplies such as digital circuit (also claiming kernel).
Referring to shown in Figure 1, traditional electrify restoration circuit comprises resistance R 1, capacitor C 1, Schmidt trigger and inverter, resistance R 1 one ends connect power vd D, the other end links to each other with capacitor C 1 one ends, capacitor C 1 other end ground connection VSS, the tie point of resistance R 1 and capacitor C 1 connects the input of Schmidt trigger, and the output of Schmidt trigger connects the input of inverter, the output of inverter connects reset signal PORB, and Schmidt trigger is by power vd D and ground VSS power supply.
There is following shortcoming in traditional electrify restoration circuit:
(1) responsive to the speed that powers on or the slope of power vd D.This susceptibility is mainly decided by the time constant that 1 combination of resistance R 1-capacitor C produces.If the speed ratio that powers on of VDD is very fast, and the voltage on the capacitor C 1 has little time to follow the VDD variation, can produce so PORB signal (power-on reset signal herein all is Low level effective signals) as shown in Figure 2, finishes the electrification reset operation.If but it is slow to power on, and the area of chip defines and can't design larger resistance and electric capacity, so just might can't produce effective power-on reset signal PORB, that is to say that PORB can the always rising along with the rising of VDD.
(2) in power up, the vdd voltage (the electrification reset end voltage point among Fig. 2) when the power-on reset signal PORB of output finishes is uncontrollable, when power-on reset signal finishes, can't guarantee that supply voltage reaches predetermined normal level.If VDD does not reach normal level, power-on reset signal just finishes, and does not then mean successfully to reset.
Summary of the invention
The objective of the invention is in order to overcome the deficiency of above-mentioned background technology, a kind of electrify restoration circuit that passes through the digital integrated circuit of chip internal pressurizer power supply is provided, not only insensitive to the speed that powers on or the slope of power vd D_L, and the electrical voltage point Vthr of power vd D_L can accurately set electrification reset and finish the time.
The electrify restoration circuit that passes through the digital integrated circuit of chip internal pressurizer power supply provided by the invention, comprise a reference source generator, pressurizer and digital core, described a reference source generator produces reference voltage V REF and outputs to pressurizer by power vd D_H, pressurizer produces and the proportional power vd D_L of reference voltage V REF by power vd D_H, output to digital core, also comprise the sluggish sampled voltage comparator that all links to each other with power vd D_H, filter shape output circuit and level translator, the input of described sluggish sampled voltage comparator connects respectively reference voltage V REF, power vd D_L and reset signal PORB_H, output output signal VCMP; The input of described filter shape output circuit connects this signal VCMP, and output connects reset signal PORB_H; The input of described level translator connects reset signal PORB_H, and output connects power-on reset signal PORB_L, and described power-on reset signal PORB_L is input to digital core.
In technique scheme, described sluggish sampled voltage comparator comprises comparator, selector switch K1, the resistance R 2, R3 and the R4 that link to each other in turn, two inputs of described selector switch K1 are connected respectively to the tie point V2 of the tie point V1 of resistance R 2, R3 and resistance R 3, R4, output connects the negative input end of comparator, the positive input terminal of comparator connects reference voltage V REF, output output signal VCMP.
In technique scheme, described resistance R 2～R4 is connected between power vd D_L and the ground VSS, and described comparator is by power vd D_H and ground VSS power supply.
In technique scheme, it is reset signal PORB_H that the switch of described selector switch K1 is selected control end.
In technique scheme, described selector switch K1 adopts the alternative selector that is made of cmos transmission gate.
In technique scheme, described filter shape output circuit comprises PMOS pipe M4, NMOS pipe M5, capacitor C 2, Schmidt trigger and inverter, the grid of described PMOS pipe M4 all links to each other with described signal VCMP with the grid of NMOS pipe M5, the drain electrode of PMOS pipe M4 links to each other with the drain electrode of NMOS pipe M5, node is VCHG, and capacitor C 2 is connected between node VCHG and the ground VSS; The input of described Schmidt trigger links to each other with node VCHG, and output links to each other with the input of described inverter, and the output of inverter connects reset signal PORB_H.
In technique scheme, described filter shape output circuit also comprises constant-current source I1 and I2, the source electrode of described PMOS pipe M4 links to each other with power vd D_H by constant-current source I1, the source electrode of described NMOS pipe M5 links to each other with ground VSS by constant-current source I2, and described Schmidt trigger is by power vd D_H and ground VSS power supply.
In technique scheme, described filter shape output circuit also comprises two resistance, the source electrode of described PMOS pipe M4 links to each other with power vd D_H by a resistance in these two resistance, the source electrode of described NMOS pipe M5 links to each other with ground VSS by another resistance in these two resistance, and described Schmidt trigger is by power vd D_H and ground VSS power supply.In technique scheme, described level translator comprises PMOS pipe M1, NMOS pipe M2, M3 and resistance R 5, the grid of described PMOS pipe M1 all links to each other with reset signal PORB_H with the grid of NMOS pipe M2, the drain electrode of PMOS pipe M1 links to each other with the drain electrode of NMOS pipe M2, be connected to the grid of NMOS pipe M3, the drain electrode of NMOS pipe M3 links to each other with an end of resistance R 5, and node is power-on reset signal PORB_L.
In technique scheme, the source electrode of described PMOS pipe M1 links to each other with power vd D_H, the source grounding VSS of NMOS pipe M2, M3, and the other end of resistance R 5 links to each other with power vd D_L.
Compared with prior art, advantage of the present invention is as follows:
(1) all insensitive to the speed that powers on or the slope of power vd D_H and VDD_L.Generally in power up, VREF can follow soon VDD_H and rise, and reaches the burning voltage of VRFE, and VREF stablizes required minimum VDD_H electrical voltage point, and generally can to stablize required minimum VDD_H electrical voltage point than VDD_L low.VDD_L itself will produce as reference voltage by VREF, only has VREF to stablize, and VDD_L just may stablize; Secondly, VDD_L generally has digital core as load, also can extract electric current from VDD_L in power up, the speed that its voltage that slows down rises; In addition, VDD_L is produced by the pressurizer of chip internal or electric pressure converter, generally can be external to a large filter capacitor CLOAD at sheet, so the speed that VDD_L rises is very slow with respect to VREF, sluggish sampled voltage comparator can be worked reliably, detects VDD_L with respect to the height situation of change of VREF.
(2) the electrical voltage point Vthr of power vd D_L in the time of can accurately setting the electrification reset end, Vthr=VREF*[(R2+R3+R4)/(R4)], as long as the resistance of Rational choice resistance R 2, R3, R4, just can the required trouble free service voltage of Set arbitrarily digital core, thus guarantee that electrification reset is effective.
Description of drawings
Fig. 1 is the circuit diagram of powered reset circuit;
Fig. 2 is the waveform schematic diagram of powered reset circuit main signal;
Fig. 3 is the circuit diagram of the embodiment of the invention;
Fig. 4 is the circuit diagram of sluggish sampled voltage comparator in the embodiment of the invention;
Fig. 5 is the circuit diagram of filter shape output circuit in the embodiment of the invention;
Fig. 6 is the circuit diagram of level translator in the embodiment of the invention;
Fig. 7 is the waveform schematic diagram of embodiment of the invention main signal.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Referring to shown in Figure 3, the electrify restoration circuit of the digital integrated circuit that passes through the power supply of chip internal pressurizer that the embodiment of the invention provides comprises a reference source generator, pressurizer and the sluggish sampled voltage comparator, filter shape output circuit and the level translator that all link to each other with power vd D_H.
Dotted line frame among Fig. 3 shows the main supply power mode of present digital integrated circuit and digifax mix signal integrate circuit:
The a reference source generator produces reference voltage V REF and outputs to pressurizer by power vd D_H, and pressurizer produces and the proportional LVPS VDD_L of reference voltage V REF by power vd D_H, outputs to digital core.
Solid box among Fig. 3 shows the designed electrify restoration circuit of the embodiment of the invention: the input of sluggish sampled voltage comparator connects respectively reference voltage V REF, power vd D_L and reset signal PORB_H, (VCMP is the output of sluggish sampled voltage comparator to output output signal VCMP, sluggish sampled voltage comparator can compare its voltage anodal and negative input, makes logic and judges); The input of described filter shape output circuit connects signal VCMP, and output connects reset signal PORB_H; The input of described level translator connects reset signal PORB_H, and output connects power-on reset signal PORB_L, and described power-on reset signal PORB_L is input to digital core.CLOAD represents chip internal or the outside load capacitance that is connected on the power vd D_L.
Referring to shown in Figure 4, sluggish sampled voltage comparator comprises comparator, selector switch K1, the resistance R 2, R3 and the R4 that link to each other in turn, two inputs of described selector switch K1 are connected respectively to the tie point V2 of the tie point V1 of resistance R 2, R3 and resistance R 3, R4, output connects the negative input end of comparator, the positive input terminal of comparator connects reference voltage V REF, output output signal VCMP.Resistance R 2～R4 is connected between power vd D_L and the ground VSS, and described comparator is by power vd D_H and ground VSS power supply.Selector switch K1 adopts the alternative selector that is made of cmos transmission gate, and it is reset signal PORB_H that its switch is selected control end.
Referring to shown in Figure 5, the filter shape output circuit comprises PMOS pipe M4, NMOS pipe M5, constant-current source I1～I2, capacitor C 2, Schmidt trigger and inverter, the grid of PMOS pipe M4 all links to each other with signal VCMP with the grid of NMOS pipe M5, the drain electrode of PMOS pipe M4 links to each other with the drain electrode of NMOS pipe M5, node is VCHG, and capacitor C 2 is connected between node VCHG and the ground VSS.The source electrode of PMOS pipe M4 links to each other with power vd D_H by constant-current source I1, and the source electrode of NMOS pipe M5 links to each other with ground VSS by constant-current source I2, and Schmidt trigger is by power vd D_H and ground VSS power supply.The input of Schmidt trigger links to each other with node VCHG, and output links to each other with the input of inverter, and the output of inverter connects reset signal PORB_H.
Constant-current source I1～I2 in the above-mentioned filter shape output circuit can also replace to two resistance, the source electrode that is PMOS pipe M4 links to each other with power vd D_H by a resistance in these two resistance, and the source electrode of NMOS pipe M5 links to each other with ground VSS by another resistance in these two resistance.
Referring to shown in Figure 6, level translator comprises PMOS pipe M1, NMOS pipe M2, M3 and resistance R 5, the grid of described PMOS pipe M1 all links to each other with reset signal PORB_H with the grid of NMOS pipe M2, the source electrode of PMOS pipe M1 links to each other with power vd D_H, the drain electrode of PMOS pipe M1 links to each other with the drain electrode of NMOS pipe M2, be connected to the grid of NMOS pipe M3, the source grounding VSS of NMOS pipe M2, M3.The drain electrode of NMOS pipe M3 links to each other with an end of resistance R 5, and node is power-on reset signal PORB_L, and the other end of resistance R 5 links to each other with power vd D_L.
The principle of the embodiment of the invention is elaborated as follows:
Referring to shown in Figure 3, in the chip that has at present, generally all be integrated with a reference source generator and pressurizer (perhaps other electric pressure converters), their major function is as follows: a reference source generator can be powered by VDD_H, autonomous voltage reference source VREF or the current reference source of producing, VREF is not subjected to the impact of VDD_H, temperature and technique change substantially.Pressurizer is mainly used to the voltage VDD_H of chip exterior is converted into the voltage VDD_L that the chip internal digital core can work.General implementation has LDO and step-down controller etc.Pressurizer shown in Fig. 3 utilizes VREF as the voltage reference source, so that VDD_L=α * VREF, α is a constant, and is selected according to actual needs when design chips.
The waveform of the main signal of the embodiment of the invention in power up is referring to shown in Figure 7, and generally in power up, VREF can follow soon VDD_H and rise, and reaches the burning voltage of VRFE.Yet VDD_L itself will produce as reference voltage by VREF, only has VREF to stablize, and VDD_L just may stablize; Secondly, VDD_L generally has digital core as load, and digital circuit can extract electric current from VDD_L in power up, the speed that powers on of the VDD_L that slows down; In addition, VDD_L is produced by pressurizer or the electric pressure converter of chip internal, generally can be external to a large filter capacitor CLOAD at sheet, so the speed that VDD_L rises is very slow with respect to VREF.The embodiment of the invention is utilized this characteristics, (β is a constant with the proportional sampling voltage β * VDD_L of VREF and VDD_L, the minimum end voltage Vthr that resets calculates according to the digital circuit acceptable) compare, if β * VDD_L is lower than VREF, then require to carry out reset operation, produce a reset signal to digital circuit, be named power-on reset signal PORB_L for this signal, be the Low level effective logical signal.If β * VDD_L is higher than VREF, illustrate that VDD_L has risen to the level that can allow the normal operation of kernel digital circuit, then stop to reset, power-on reset signal PORB_L becomes high level (high level is VDD_L).
The generation of power-on reset signal PORB_L need to be used three main functional modules shown in Figure 3 in the embodiment of the invention: sluggish sampled voltage comparator, filter shape output circuit and level translator.
Referring to shown in Figure 4, the V1 in the sluggish sampled voltage comparator and V2 are the voltage signals that VDD_L is carried out proportional sampling by resistance R 2, R3 and R4, wherein,
V1＝[(R3+R4)/(R2+R3+R4)]*VDD_L；
V2＝[(R4)/(R2+R3+R4)]*VDD_L。
Selector switch K1 is the analog switch of alternative, selects V1 or V2 to be connected to the negative input end of comparator, and reset signal PORB_H (high level is VDD_H) comes this selector switch K1 is selected control.The positive input terminal of comparator is linked VREF.
The specific works principle of the embodiment of the invention in the electrification reset process is:
Power on the initial stage in initialization, VDD_L is also very low, and VREF is higher than the voltage of V1 and V2 in the sluggish sampled voltage comparator, and no matter PORB_H is high level or low level, and comparator all can be high level output VCMP.The VCMP of this high level can obtain one and be defined as low level PORB_H signal (this signal obtains the PORB_L signal through level translator) through follow-up filter shape output module.That at this moment link the comparator negative input end is V2.Rising along with VDD_L, V2 can be equal to or higher than VREF, thereby make the comparator upset, VCMP jumps low, referring to shown in Figure 7, the voltage of this VDD_L constantly is designated as Vthr, can obtains the value of Vthr by simple calculating: because [(R4)/(R2+R3+R4)] * Vthr=VREF, so Vthr=VREF*[(R2+R3+R4)/(R4)].VCMP jumps low, i.e. expression resets and can stop, and VDD_L has reached the level of normal operation.VCMP obtains the PORB_H signal of a high level again by the filter shape output circuit, and selector switch K1 is chosen to V1.Because V1 is also higher than V2, so the output VCMP of comparator has been locked onto low level firmly, can not judge by accident.
Referring to shown in Figure 5, in the filter shape output circuit, if VCMP is low level, NMOS pipe M5 closes so, and PMOS pipe M4 opens, and to capacitor C 2 chargings, the voltage of node VCHG raises VDD_H by constant-current source I1 (perhaps resistance); Otherwise if VCMP is high level, NMOS pipe M5 opens so, and PMOS pipe M4 closes, and capacitor C 2 is by over the ground VSS discharge of constant-current source I2 (perhaps resistance), the lower voltage of node VCHG.
Referring to shown in Figure 7, in the power up, VCMP is high level first, follows the VDD_L change in voltage, and node VCHG is discharged into ground VSS, Schmidt trigger output high level, and through the shaping of one-level inverter, reset signal PORB_H is output as low level, to resetting.Behind the trouble free service voltage that VDD_L has reached, signal VCMP jumps low, node VCHG begins to be recharged, voltage rises, when node VCHG reached the rising edge triggering level Vtr of Schmidt trigger, Schmidt trigger triggered output low level, through the shaping of one-level inverter, reset signal PORB_H exports high level, and end resets.
The filter function of filter shape output circuit is embodied in: in the time of near VDD_L rises to Vthr, V2 and VREF are similar, at this moment the comparator rollover states in the sluggish sampled voltage comparator may occur probabilistic fast repeatedly, therefore need the filter shape output circuit that filtering is carried out in the output of comparator and process, obtain one and determine and stable output.The characteristic of Schmidt trigger is that the rising edge triggering level Vtr of input signal is different with trailing edge triggering level Vtf, generally be that the rising edge triggering level is high, the trailing edge triggering level is low, the difference of these two triggering levels is exactly the filter range of node VCHG, that is to say, as long as node VCHG is in this scope, the state of trigger can not change.Referring to shown in Figure 5, if choose less constant-current source (perhaps larger resistance value), choose larger C2 capacitance, the charging step-length of C2 is just little, VCMP's is fast repeatedly limited to the change of the voltage of node VCHG so, generally can not exceed the scope of Vtr and Vtf.
Reset signal PORB_H is the logical signal that adopts the analog circuit generation of VDD_H power supply, is the operating voltage of VDD_H.The employed power supply of digital core is the VDD_L voltage that produces through pressurizer or electric pressure converter, therefore power-on reset signal also must be the signal of this voltage range, therefore need to convert reset signal PORB_H to power-on reset signal PORB_L by level translator.
Referring to shown in Figure 6, PMOS pipe M1 and NMOS pipe M2 consist of the CMOS inverter of a VDD_H power supply, the output of this CMOS inverter connects the grid of NMOS pipe M3, NMOS pipe M3 and resistance R 5 consist of the inverter of a VDD_L power supply, and output power-on reset signal PORB_L, concrete waveform is referring to shown in Figure 7.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
The content that is not described in detail in this specification belongs to the known prior art of this area professional and technical personnel.
Claims (10)
1. electrify restoration circuit by the digital integrated circuit of chip internal pressurizer power supply, comprise a reference source generator, pressurizer and digital core, described a reference source generator produces reference voltage V REF and outputs to pressurizer by power vd D_H, pressurizer produces and the proportional power vd D_L of reference voltage V REF by power vd D_H, output to digital core, it is characterized in that: also comprise the sluggish sampled voltage comparator that all links to each other with power vd D_H, filter shape output circuit and level translator, the input of described sluggish sampled voltage comparator connects respectively reference voltage V REF, power vd D_L and reset signal PORB_H, output output signal VCMP; The input of described filter shape output circuit connects this signal VCMP, and output connects reset signal PORB_H; The input of described level translator connects reset signal PORB_H, and output connects power-on reset signal PORB_L, and described power-on reset signal PORB_L is input to digital core.
2. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 1, it is characterized in that: described sluggish sampled voltage comparator comprises comparator, selector switch K1, the resistance R 2, R3 and the R4 that link to each other in turn, two inputs of described selector switch K1 are connected respectively to the tie point V2 of the tie point V1 of resistance R 2, R3 and resistance R 3, R4, output connects the negative input end of comparator, the positive input terminal of comparator connects reference voltage V REF, output output signal VCMP.
3. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 2, it is characterized in that: described resistance R 2～R4 is connected between power vd D_L and the ground VSS, and described comparator is by power vd D_H and ground VSS power supply.
4. pass through as claimed in claim 2 or claim 3 the electrify restoration circuit of the digital integrated circuit of chip internal pressurizer power supply, it is characterized in that: it is reset signal PORB_H that the switch of described selector switch K1 is selected control end.
5. pass through as claimed in claim 2 or claim 3 the electrify restoration circuit of the digital integrated circuit of chip internal pressurizer power supply, it is characterized in that: described selector switch K1 adopts the alternative selector that is made of cmos transmission gate.
6. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 1, it is characterized in that: described filter shape output circuit comprises PMOS pipe M4, NMOS pipe M5, capacitor C 2, Schmidt trigger and inverter, the grid of described PMOS pipe M4 all links to each other with described signal VCMP with the grid of NMOS pipe M5, the drain electrode of PMOS pipe M4 links to each other with the drain electrode of NMOS pipe M5, node is VCHG, and capacitor C 2 is connected between node VCHG and the ground VSS; The input of described Schmidt trigger links to each other with node VCHG, and output links to each other with the input of described inverter, and the output of inverter connects reset signal PORB_H.
7. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 6, it is characterized in that: described filter shape output circuit also comprises constant-current source I1 and I2, the source electrode of described PMOS pipe M4 links to each other with power vd D_H by constant-current source I1, the source electrode of described NMOS pipe M5 links to each other with ground VSS by constant-current source I2, and described Schmidt trigger is by power vd D_H and ground VSS power supply.
8. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 6, it is characterized in that: described filter shape output circuit also comprises two resistance, the source electrode of described PMOS pipe M4 links to each other with power vd D_H by a resistance in these two resistance, the source electrode of described NMOS pipe M5 links to each other with ground VSS by another resistance in these two resistance, and described Schmidt trigger is by power vd D_H and ground VSS power supply.
9. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 1, it is characterized in that: described level translator comprises PMOS pipe M1, NMOS pipe M2, M3 and resistance R 5, the grid of described PMOS pipe M1 all links to each other with reset signal PORB_H with the grid of NMOS pipe M2, the drain electrode of PMOS pipe M1 links to each other with the drain electrode of NMOS pipe M2, be connected to the grid of NMOS pipe M3, the drain electrode of NMOS pipe M3 links to each other with an end of resistance R 5, and node is power-on reset signal PORB_L.
10. the electrify restoration circuit of the digital integrated circuit by chip internal pressurizer power supply as claimed in claim 9, it is characterized in that: the source electrode of described PMOS pipe M1 links to each other with power vd D_H, the source grounding VSS of NMOS pipe M2, M3, the other end of resistance R 5 links to each other with power vd D_L.
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| CN102291109A (en) | 2011-12-21 |
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