CN110045774A - A kind of digital LDO circuit of fast transient response - Google Patents
A kind of digital LDO circuit of fast transient response Download PDFInfo
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- CN110045774A CN110045774A CN201910264898.6A CN201910264898A CN110045774A CN 110045774 A CN110045774 A CN 110045774A CN 201910264898 A CN201910264898 A CN 201910264898A CN 110045774 A CN110045774 A CN 110045774A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses a kind of digital LDO circuits of fast transient response, including capacitor in clocked comparator array, controller, array of power switches, sampling resistor network and piece, controller is for controlling the power switch number be connected in array of power switches, and then adjust the size of output voltage, when load jump leads to output voltage fluctuation, controller opens dichotomy adjustment for the stable state of the fast quick-recovery of output voltage to the rated output voltage for tending to circuit.Number LDO circuit of the invention all has faster transient response speed, and in transient response, by the quick adjustment period of early-fixed, so that output voltage is restored to rated value when output voltage caused by face of different loads variation jumps.Relative to other LDO circuits, present invention number LDO circuit uses the circuit structure of cardinar number word cell, can operate in the low supply voltage environment of sub- 1V, has the advantages that quiescent dissipation is low, integrated level is high, transient response is fast.
Description
Technical field
The present invention relates to ic power management and simulation and digital-to-analogue mixed signal Circuits and Systems (Analog and
Mixed-signal circuit and system, AMSCS) technical field, the number of specifically a kind of fast transient response
LDO circuit.
Background technique
In recent years, some electronic equipments such as mobile phone, electronics bracelet, tablet computer are made more frivolous, while internal piece
Upper system (SoC) integrated level is higher and higher, and energy consumption needed for this means that the operation of these equipment is significantly increased and battery capacity
Do not promoted therewith.In order to improve the cruising ability of these equipment and provide a good operating voltage, it is necessary in electricity
Power management chip is introduced between source and these modules, shoulders transformation, distribution, detection and pressure stabilizing to electric energy, noise reduction
Function, while these power management chips need to meet the low-power consumption requirement of itself, enable a device to the operation of longer time.
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) is since its circuit is simple, noise and power consumption
Low advantage, is widely applied in power management chip.Traditional simulation LDO (ALDO) needs a μ F amount outside piece
The decoupling capacitor of grade, to obtain good ripple immunity to interference and excellent transient response characteristic.And System-in-Package technology develops
Power consumption and size to LDO propose very high requirement, in order to reduce chip area and keep preferable stability, outside no piece
The ALDO of capacitor needs additional complicated compensation network.Simultaneously with the continuous reduction of CMOS technology size and low-power consumption
It is required that being continuously improved, super large-scale integration (Very Large Scale Integration Circuit, VLSI) is even
It is required work under low-voltage (0.5V) state, and this will lead to close to the operating voltage of metal-oxide-semiconductor threshold voltage level
ALDO is difficult to design.
In order to solve the problems, such as that low voltage environment can not work, digital LDO (DLDO) is suggested.Fig. 1 illustrates ALDO's
Simplified structure diagram mainly includes error amplifier and power tube.Fig. 2 illustrates the structural schematic diagram of DLDO, with ALDO phase
Than, DLDO clocked comparator instead of in ALDO error amplifier, with one group of array of power switches instead of single in ALDO
One high power tube, and change using the controller based on one group of bidirectional shift register the conducting of array of power switches
Number makes output voltage keep stablizing.Digital structure makes DLDO obtain lower operating voltage, higher technique can
Scalability and lower quiescent dissipation.Nevertheless, there are poor transient responses by DLDO, i.e., when the load of LDO occurs suddenly
When variation, output voltage will generate jump (hopping amplitude changes with load variation size).ALDO can pass through error
Amplifier and power tube adjust output voltage to nominal quickly, and DLDO can only be adjusted by the sampled result of sampling clock
Whole power switch number, resume speed are limited to the unit clock variable number of clock frequency and power switch.Due to earliest
DLDO each clock cycle can only tune a power switch, cause its transient response speed very slow.Improve sampling clock
Frequency, transient response speed can be increased, but the dynamic power consumption of LDO can be accordingly increased.And increase the wide length of power switch
Than can equally increase the speed of transient response, but it will affect the precision of the last burning voltage of LDO.Using coarse adjustment refinement phase modulation knot
The control mode of conjunction realizes that quickly adjustment, later period unit clock change by the power switch number that unit clock early period changes N times
Become 1 times of power switch number and realize precision controlling, is a kind of common DLDO control program.But this scheme has certain
Limitation optimizes bad possibility there are transient response speed when coping with different loads variation.
Summary of the invention
The present invention provides a kind of DLDO circuit of new fast transient response with more reusability, the number LDO circuit
Core control program as controller is adjusted using dichotomy, in transient response, by the quick adjustment of early-fixed
Period, so that output voltage is restored to rated value；The number LDO circuit uses the circuit structure of cardinar number word cell, can work
In the low supply voltage environment of sub- 1V, have the advantages that quiescent dissipation is low, integrated level is high, transient response is fast.
The technical scheme adopted by the invention is as follows: a kind of digital LDO circuit of fast transient response, including clocked comparator
Capacitor in array, controller, array of power switches, sampling resistor network and piece, the positive input of the clocked comparator array
End is connect with the output end of the sampling resistor network, the negative input end of the clocked comparator array and external reference electricity
Pressure connection, the signal output end of the clocked comparator array is connect with the signal input part of the controller, described
The clock enable end of clocked comparator array and the input end of clock of the controller are connect with external sampling clock respectively, institute
The signal output end for the controller stated is connect with the input terminal of the array of power switches, the array of power switches it is defeated
Outlet connects with the input electrode of capacitor in the input electrode of the sampling resistor network and the piece and output voltage respectively
It connects, the output electrode connect and ground of capacitor in the output electrode of the sampling resistor network and the piece, described is defeated
Voltage is connected with load out, the carrying ground, and the controller is used to control and be connected in the array of power switches
Power switch number, and then adjust the size of the output voltage, when load jump leads to output voltage fluctuation,
The controller opens dichotomy adjustment for the stabilization shape of the fast quick-recovery of output voltage to the rated output voltage for tending to circuit
State.
Preferably, the array of power switches is one group of quantity with the PMOS transistor battle array in parallel of binary distributed
Column, the signal output end of the controller are connect with each grid end of the PMOS transistor array, and the PMOS is brilliant
Each source of body pipe array is connect with external input voltage, each drain terminal of the PMOS transistor array respectively with it is described
The input electrode of sampling resistor network connected with the input electrode of capacitor in the piece and output voltage.
Preferably, the PMOS transistor array includes n column PMOS transistor group, according to binary distributed, jth column
PMOS transistor group by 2j-1A identical PMOS transistor parallel connection is constituted, wherein 1≤j≤n, j ∈ Z；Each column PMOS transistor
The breadth length ratio W/L of group is from small to large successively are as follows: δ, 2 δ, 22·δ、23·δ、…、2n-1δ, wherein δ is single PMOS transistor
Breadth length ratio；The controller exports the function be connected in array of power switches described in the binary signal control of one group of n-bit
Rate number of switches.PMOS transistor array includes 2nThe identical PMOS transistor that -1 breadth length ratio is δ, these PMOS transistors
Quantity be approximately 2n.PMOS transistor conducting is considered as binary " 1 ", shutdown is considered as " 0 ", then array of power switches is opened
The power switch number be connected in off status and array of power switches can indicate with the binary array of one group of n-bit, because
The binary signal that this controller generates one group of n-bit controls the power switch number be connected in array of power switches.With number
The change of the output voltage of word LDO circuit, the binary signal of n-bit can also be changed by controller, realize that digital LDO circuit is defeated
The dynamic regulation of voltage out, so that output voltage fast quick-recovery and is maintained at rated output voltage or more in transient response.Its
In, n determines that the transient response speed speed of digital LDO circuit, δ determine the precision of the output voltage of digital LDO circuit, n
The loading range of digital LDO circuit has been codetermined with δ.
Preferably, the sampling resistor network includes that concatenated first sampling resistor, the second sampling resistor, third are adopted
Sample resistance and the 4th sampling resistor, one end of first sampling resistor are each with the PMOS transistor array respectively
Drain terminal is connected with the input electrode of capacitor in the piece, the other end of first sampling resistor and second sampling
One end of resistance connects, and the other end of second sampling resistor is connect with one end of the third sampling resistor, described
The other end of third sampling resistor connect with one end of the 4th sampling resistor, the 4th sampling resistor it is another
The output electrode connect and ground at end and capacitor in the piece.
Preferably, the clocked comparator array includes the first clocked comparator, the second clocked comparator and third
Clocked comparator, the positive input terminal of first clocked comparator are connect with the other end of first sampling resistor, institute
The negative input end for the first clocked comparator stated is connect with the external reference voltage, and second clocked comparator is just
Input terminal is connect with the other end of second sampling resistor, the negative input end of second clocked comparator and described
The other end of external reference voltage connection, the positive input terminal of the third clocked comparator and the third sampling resistor connects
It connects, the negative input end of the third clocked comparator is connect with the external reference voltage, and first clock compares
The clock enable end of device, the second clocked comparator and third clocked comparator is connect with the external sampling clock respectively, institute
The signal output end of the first clocked comparator, the second clocked comparator and the third clocked comparator stated respectively with the control
The signal input part of device connects.When sampling clock rising edge arrives, the first clocked comparator, the second clocked comparator and third
Clocked comparator is respectively compared the voltage value of its positive and negative two input terminal, exports high level " 1 " or low electricity respectively according to comparison result
Flat " 0 ", the voltage value of the positive input terminal of even each clocked comparator are greater than the voltage value of negative input end, then each clock compares
Device exports high level " 1 " respectively；If the voltage value of the positive input terminal of each clocked comparator is less than the voltage value of negative input end,
Each clocked comparator exports low level " 0 " respectively.
Preferably, first clocked comparator is used to judge whether the output voltage reaches unlatching dichotomy
The high threshold voltage of adjustment, the third clocked comparator are used to judge whether the output voltage reaches unlatching dichotomy
The low threshold voltage of adjustment, second clocked comparator be used for by comparing the output voltage with it is described specified defeated
The size of voltage judges whether to need to increase and decrease the conducting number of power switch in each adjustment period out, and is sent out with signal form
The signal input part for giving the controller, after opening dichotomy adjustment, the controller is according to second clock
The signal for controlling comparator adjusts by n wheel within the n fixed clock cycle, the output voltage is quickly adjusted to becoming
In the rated output voltage.
Preferably, the controller takes turns the power switch number be connected in adjustment the 1st after opening dichotomy adjustment
Variable quantity be the array of power switches in power switch sum half, i.e., 2n-1；The controller is the 2nd
The variable quantity of the power switch number be connected in wheel adjustment is the variable quantity of the power switch number be connected in last round of adjustment
Half, i.e., 2n-2；And so on, the variable quantity for the power switch number that the controller is connected in the n-th wheel adjustment is
1, dichotomy adjustment terminates.
Preferably, triggering the first clocked comparator, the second clocked comparator and the third clocked comparator are turned over
The threshold voltage turned is denoted as V respectivelyOUT1、VOUT2 and VOUT3, the output voltage of circuit is denoted as VOUT, by the rated output of circuit
Voltage is denoted as VRATED, VOUT3 be the high threshold voltage, VOUT1 is the low threshold voltage, in which:
VRATED=VOUT2
In formula, VREFFor the external reference voltage, R1 is first sampling resistor, and R2 adopts for described second
Sample resistance, R3 are the third sampling resistor, and R4 is the 4th sampling resistor；
When circuit work is in stable state, in each clock cycle, output voltage VOUTSize in VOUTNear 2 up and down
Fluctuation, fluctuating range are that voltage amplitude caused by the increase and decrease of number is connected in single power switch；
When load jump, VOUTIt jumps therewith, if VOUT1<VOUT<VOUT3, then illustrate that load jump causes output voltage small
Amplitude wave is dynamic, then VOUTRestore output voltage to stabilization by the increase and decrease that number is connected in single power switch within n clock cycle
State；If VOUTBy VOUT1<VOUT<VOUT3 change to VOUT<VOUT1 or VOUT>VOUT3, then illustrate that load jump leads to output voltage
Fluctuation triggers the first clocked comparator or third clocked comparator to the controller and issues signal, the control
Device opens dichotomy adjustment, works as VOUT<VOUT2, second clocked comparator needs to increase to the controller sending
The signal of the conducting number of power switch；Work as VOUT>VOUT2, second clocked comparator is issued to the controller and is needed
Reduce the signal of the conducting number of power switch.
Judge the foundation of two kinds of load jumps are as follows: VOUT2-VOUT1=VOUT3-VOUT2≈n×Vδ, wherein VδFor single power
The voltage amplitude of switch change.Regardless of load jumps, the transient response recovery time of present invention number LDO circuit is all in n
Within a clock cycle, fast transient response is realized.
Preferably, in any one wheel adjustment during dichotomy adjustment, if the power switch number be connected after adjustment
Greater than power switch sum in the array of power switches or the function less than zero, then before the controller keeps the wheel to adjust
Rate number of switches is constant until next round adjusts.
Compared with the prior art, the advantages of the present invention are as follows:
(1) the digital LDO circuit of fast transient response disclosed by the invention adjusts the core as controller using dichotomy
Heart control program.When output voltage has big jump, starting dichotomy adjusts regulation power pipe number, can consolidate in shorter
Output voltage is adjusted to nominal in the fixed period；When output voltage has small jump, function is gradually adjusted using tradition
The mode of rate pipe number, is adjusted to nominal for output voltage.Therefore, the digital LDO circuit of the present invention is facing different loads
When output voltage caused by variation jumps, faster transient response speed is all had, and in transient response, by early-fixed
The quick adjustment period so that output voltage is restored to rated value.
(2) relative to other LDO circuits, the digital LDO circuit of fast transient response disclosed by the invention, using pure digi-tal
The circuit structure of unit can operate in the low supply voltage environment of sub- 1V, with quiescent dissipation is low, integrated level is high, transient state
Respond fast advantage.
Detailed description of the invention
Fig. 1 is the simplified structure diagram of existing simulation LDO circuit；
Fig. 2 is the simplified structure diagram of existing digital LDO circuit；
Fig. 3 is the structural schematic diagram of the digital LDO circuit of embodiment；
Fig. 4 is the working state schematic representation of clocked comparator array in embodiment；
Fig. 5 is the load transient response characteristic curve of the digital LDO circuit of embodiment；
Fig. 6 is the flow diagram of dichotomy adjustment in the present invention.
Specific embodiment
Present invention is further described in detail with reference to embodiments.
The digital LDO circuit of the fast transient response of embodiment, as shown in figure 3, including clocked comparator array, control
Capacitor in device, array of power switches, sampling resistor network and piece, the positive input terminal and sampling resistor network of clocked comparator array
Output end connection, the negative input end of clocked comparator array connect with external reference voltage, the signal of clocked comparator array
The connection of the signal input part of output end and controller, the clock enable end of clocked comparator array and the input end of clock of controller
It is connect respectively with external sampling clock, the signal output end of controller and the input terminal of array of power switches connect, power switch
The output end of array is connect with the input electrode of capacitor in the input electrode of sampling resistor network and piece and output voltage respectively, is adopted
The output electrode connect and ground of capacitor in the output electrode and piece of sample resistor network, output voltage are connected with load, and load connects
Ground, controller adjusts the size of output voltage for controlling the power switch number be connected in array of power switches, when negative
Jump is carried when leading to output voltage fluctuation, controller opens dichotomy adjustment for the fast quick-recovery of output voltage to tending to circuit
Rated output voltage stable state.
In the present embodiment, array of power switches is the PMOS transistor array of parallel connection of the one group of quantity with binary distributed,
The signal output end of controller is connect with each grid end of PMOS transistor array, each source of PMOS transistor array and outer
Portion's input voltage connection, each drain terminal of PMOS transistor array respectively with capacitor in the input electrode of sampling resistor network and piece
Input electrode and output voltage connection.
PMOS transistor array includes 7 column PMOS transistor groups, according to binary distributed, the PMOS transistor group of jth column
By 2j-1A identical PMOS transistor parallel connection is constituted, wherein 1≤j≤7, j ∈ Z；The breadth length ratio W/L of each column PMOS transistor group
From small to large successively are as follows: δ, 2 δ, 22·δ、23·δ、24·δ、25·δ、26δ, wherein δ is that the width of single PMOS transistor is long
Than；PMOS transistor conducting is considered as binary " 1 ", shutdown is considered as " 0 ", then the switch state and function of array of power switches
The power switch number be connected in rate switch arrays can indicate that is, controller exports one with the binary array of one group of 7-bit
The power switch number be connected in the binary signal control array of power switches of group 7-bit.
Sampling resistor network include concatenated first sampling resistor R1, the second sampling resistor R2, third sampling resistor R3 and
4th sampling resistor R4, one end of the first sampling resistor R1 respectively with capacitor in each drain terminal and piece of PMOS transistor array
Input electrode connection, the other end of the first sampling resistor R1 are connect with one end of the second sampling resistor R2, the second sampling resistor R2
The other end connect with one end of third sampling resistor R3, the one of the other end of third sampling resistor R3 and the 4th sampling resistor R4
End connects, the output electrode connect and ground of capacitor in the other end and piece of the 4th sampling resistor R4.
Clocked comparator array includes the first clocked comparator CP1, the second clocked comparator CP2 and third clocked comparator
CP3, the positive input terminal V of the first clocked comparator CP1HIt is connect with the other end of the first sampling resistor R1, the first clocked comparator
The negative input end of CP1 is connect with external reference voltage, the positive input terminal V of the second clocked comparator CP2MWith with the second sampling resistor
The other end of R2 connects, and the negative input end of the second clocked comparator CP2 is connect with external reference voltage, third clocked comparator
The positive input terminal V of CP3LIt is connect with the other end of third sampling resistor R3, the negative input end of third clocked comparator CP3 and outer
The connection of portion's reference voltage, the clock of the first clocked comparator CP1, the second clocked comparator CP2 and third clocked comparator CP3 make
Energy end is connect with external sampling clock respectively, and the first clocked comparator CP1, the second clocked comparator CP2 and third clock compare
The signal output end of device CP3 is connect with the signal input part of controller respectively.
First clocked comparator CP1 is used to judge whether output voltage to reach the high threshold voltage of unlatching dichotomy adjustment,
Third clocked comparator CP3 is used to judge whether output voltage reaches the low threshold voltage for opening dichotomy adjustment, the second clock
Comparator CP2 is used to judge whether need in each adjustment period by comparing the size of output voltage and rated output voltage
Increase and decrease the conducting number of power switch, and be sent to the signal input part of controller with signal form, opens dichotomy adjustment
Afterwards, controller will be exported according to the signal of the second clocked comparator CP2 by 7 wheel adjustment within 7 fixed clock cycle
Voltage is quickly adjusted to tending to rated output voltage.
After opening dichotomy adjustment, the variable quantity for the power switch number that controller is connected in the 1st wheel adjustment is power
The half of power switch sum in switch arrays, i.e., 26；The power switch number that controller is connected in the 2nd wheel adjustment
Variable quantity is the half of the variable quantity of power switch number be connected in last round of adjustment, i.e., 25；And so on, controller
The variable quantity of the power switch number be connected in the 7th wheel adjustment is 1, and dichotomy adjustment terminates.During dichotomy adjustment
In any one wheel adjustment, if the power switch number be connected after adjustment is greater than power switch sum in array of power switches or is less than
Zero, then the power switch invariable number before controller keeps the wheel to adjust is until next round adjustment.
As shown in figure 4, will the first clocked comparator CP1 of triggering, the second clocked comparator CP2 and third clocked comparator
The threshold voltage of CP3 overturning is denoted as V respectivelyOUT1、VOUT2 and VOUT3, the output voltage of circuit is denoted as VOUT, by the specified of circuit
Output voltage is denoted as VRATED, VOUT3 be high threshold voltage, VOUT1 is low threshold voltage, in which:
VRATED=VOUT2
In formula, VREFFor external reference voltage, R1 is that the first sampling resistor R1, R2 is that the second sampling resistor R2, R3 is third
Sampling resistor R3, R4 are the 4th sampling resistor R4；
When circuit work is in stable state, in each clock cycle, output voltage VOUTSize in VOUTNear 2 up and down
Fluctuation, fluctuating range are that voltage amplitude caused by the increase and decrease of number is connected in single power switch；
When load jump, VOUTIt jumps therewith, if VOUT1<VOUT<VOUT3, then illustrate that load jump causes output voltage small
Amplitude wave is dynamic, then VOUTRestore output voltage to stabilization by the increase and decrease that number is connected in single power switch within n clock cycle
State；If VOUTBy VOUT1<VOUT<VOUT3 change to VOUT<VOUT1 or VOUT>VOUT3, then illustrate that load jump leads to output voltage
The output that fluctuation, i.e. the output signal H of the first clocked comparator CP1 are become " 0 " or third clocked comparator CP3 from " 1 "
Signal L is become " 1 " from " 0 ", and triggering the first clocked comparator CP1 or third clocked comparator CP3 issues signal, control to controller
Device processed opens dichotomy adjustment, rapidly by V in the fixed adjustment periodOUTRestore to VOUTNear 2.Work as VOUT<VOUT2, i.e.,
The output signal M of second clocked comparator CP2 is " 0 ", and the second clocked comparator CP2 needs to increase power to controller sending and opens
The signal of the conducting number of pass；Work as VOUT>VOUT2, i.e. the output signal M of the second clocked comparator is " 1 ", the second clocked comparator
CP2 issues the signal for needing to reduce the conducting number of power switch to controller.
Specifically, which during the work time, if load changes, leads to the output voltage V of circuitOUTIt is low
In the low threshold voltage of dichotomy adjustment, i.e.,Then third clocked comparator CP3 is exported
Signal L starts dichotomy to controller and adjusts, it is clear thatThen in dichotomy
In 1 wheel adjustment, the conducting number of current PMOS power switch needs to increase by two score values (power switch knots modification) of the 1st wheel, should
Two score values be power switch sum half, i.e., 26, adder in controller is by the binary number phase of this two groups of 7-bit
It is output to PMOS array of power switches after adding, increases so that number is connected in it, therefore the output electric current of PMOS array of power switches
Increase, and then improves output voltage VOUT, later, according to the more updated output voltage V of the second clocked comparator CP2OUTWith
Rated output voltage VRATEDIf VOUT<VRATED, then the conducting number of PMOS power switch needs to increase by two score values of the 2nd wheel, instead
It, conducting number will reduce two score values of the 2nd wheel, wherein half of two score values of the 2nd wheel for the 1st wheel, i.e., 25, then again
According to updated VOUTInto the adjustment of the 3rd wheel, during adjustment, if the conducting number of the power switch after changing exceeds model
It encloses and (is greater than sum 127 or less than 0), then keep original switch state constant, adjusted into next round, and so on, the 7th wheel
Two score values are 1, and the knots modification of the power switch of circuit has almost traversed the total quantity of power switch, therefore, circuit at this time
Output voltage VOUTWith voltage rating VRATEDVery close to when the 7th wheel adjustment terminates, i.e., at the end of dichotomy adjustment, circuit will
Restore common adjustment modes, i.e., each adjustment period only changes 1 power switch, and output voltage VOUTIt will be in voltage rating
VRATEDApproach up and down, the output voltage V of circuitOUTRestore to stablize；If load variation, leads to the output voltage V of circuitOUTMore than two
The high threshold voltage of point-score adjustment, i.e.,Then the first clocked comparator CP1 output signal
H starts dichotomy to controller and adjusts, it is clear thatThen taken turns in dichotomy the 1st
In adjustment, the conducting number of current PMOS power switch need to reduce the 1st wheel two score values, i.e., 26, by this two groups in controller
The binary number of 7-bit is output to PMOS array of power switches after subtracting each other (subtraction can be by taking benefit to subtrahend, and the Calais Zai Xiang is real
It is existing) it is reduced so that number is connected in it, therefore the output electric current of PMOS array of power switches is reduced, and then reduce output voltage
VOUT, adjustment mode later is same as above.During dichotomy adjustment, the first clocked comparator CP1, third clocked comparator CP3
Output signal H, L is placed in dormant state, after dichotomy adjustment, just restores normal.
Set the input voltage V in the present embodimentINFor 0.6V, reference voltage VREFFor 0.5V, rated output voltage is
0.55V, sampling clock CLK are 10MHz, and capacitor is 100pF in piece, it is contemplated that internal circuit delay and load charge-discharge speed,
Frequency divider is added inside controller, so that the adjustment period of controller becomes 5 × 100ns.Digital LDO circuit in the present embodiment
Load transient response characteristic curve is as shown in Figure 5, it can be seen that when the load of the LDO circuit jumps to heavy duty from underloading (2mA)
(20mA) or when jumping to underloading (2mA) from heavily loaded (20mA), circuit is opened dichotomy and is adjusted, output voltage VOUTRestore specified
The horizontal required time is 3.3 μ s or so (7 × 5 × 100ns), the characteristic with fast transient response.
The flow diagram that dichotomy adjusts in the present invention is shown in Fig. 6.As shown in fig. 6, the working principle of dichotomy adjustment is such as
Under:
Firstly, setting power switch sum that array of power switches includes as N=1+2+4+8+ ...+2n-1≈2n, circuit work
In stable state, the number of switches be currently connected is about X, the value by one group of n-bit binary number representation.
Work as load jump, while the output signal H of the first clocked comparator becomes " 0 " or third clocked comparator from " 1 "
Output signal L " 1 " is become from " 0 ", by open dichotomy adjustment.At this point, setting needs to change in the 1st wheel adjustment period
Power switch number be master switch number half, i.e., the initial value of dichotomy factor i is set as 1, then the first round need
The power switch number of changeThe value is also by the binary number representation of one group of n-bit.
Then, the output voltage V of X power switch is currently connected according to the second clocked comparator comparison circuitOUT(X) with
Rated output voltage VRATEDSize reduce the power that K is connected still judging to need to increase the power switch of K conducting and open
It closes.If the output signal M of the second clocked comparator is " 0 ", the power switch be connected needs to increase, i.e. X=X+K；If second
The output signal M of clocked comparator is " 1 ", then the power switch be connected needs to reduce, i.e. X=X-K.
But there are bounds by X, it cannot be negative no more than power switch sum N.Therefore, work as X+K > N or X-
When K < 0, then the power switch of conducting is made to keep the power switch invariable number before wheel adjustment, until next round adjusts.
After X adjustment, the output voltage of circuit also can be adjusted dynamically therewith, enter the 2nd wheel adjustment later.The function of 2nd wheel
It is last round of half that rate, which switchs knots modification, therefore, dichotomy factor i=i+1, the knots modification of power switch
Adjusted Option later is consistent with last round of adjustment.
It is adjusted finally, being taken turns by n, the knots modification K=1 of power switch, i.e. i=log2N ≈ n, dichotomy adjustment terminate.This
When the entire dichotomy adjustment period in the variable quantity of power switch had stepped through power switch sum, output voltage VOUTAlso it weighs
Newly it is restored to rated output voltage VRATEDNear.
In dichotomy adjustment, the Initiated Mechanism of dichotomy will avoid being repeated triggering in a dormant state, until adjustment
Terminate, Initiated Mechanism just restores normal.
Claims (9)
1. a kind of digital LDO circuit of fast transient response, it is characterised in that including clocked comparator array, controller, power
Capacitor in switch arrays, sampling resistor network and piece, the positive input terminal of the clocked comparator array and sampling electricity
The output end connection of network is hindered, the negative input end of the clocked comparator array is connect with external reference voltage, the clock
The signal output end of control comparator array is connect with the signal input part of the controller, the clocked comparator array
The input end of clock of clock enable end and the controller is connect with external sampling clock respectively, the signal of the controller
Output end is connect with the input terminal of the array of power switches, the output end of the array of power switches respectively with it is described
The input electrode of sampling resistor network is connected with the input electrode of capacitor in the piece and output voltage, the sampling resistor
The output electrode connect and ground of capacitor in the output electrode of network and the piece, the output voltage are connected with load,
The carrying ground, the controller are used to control the power switch number be connected in the array of power switches, into
And the size of the output voltage is adjusted, when load jump leads to output voltage fluctuation, the controller is opened
Dichotomy is adjusted the stable state of the fast quick-recovery of output voltage to the rated output voltage for tending to circuit.
2. a kind of digital LDO circuit of fast transient response according to claim 1, it is characterised in that the power is opened
Closing array is one group of quantity with the PMOS transistor array in parallel of binary distributed, the signal output end of the controller with
Each grid end of the PMOS transistor array connects, each source and the external input electricity of the PMOS transistor array
Pressure connection, each drain terminal of the PMOS transistor array respectively with the input electrode of the sampling resistor network and described
Piece in capacitor input electrode and output voltage connection.
3. a kind of digital LDO circuit of fast transient response according to claim 2, it is characterised in that the PMOS is brilliant
Body pipe array includes n column PMOS transistor group, and according to binary distributed, the PMOS transistor group of jth column is by 2j-1It is a identical
PMOS transistor parallel connection is constituted, wherein 1≤j≤n, j ∈ Z；The breadth length ratio W/L of each column PMOS transistor group is from small to large successively
Are as follows: δ, 2 δ, 22·δ、23·δ、…、2n-1δ, wherein δ is the breadth length ratio of single PMOS transistor；The controller output one
The power switch number be connected in the binary signal control of the group n-bit array of power switches.
4. a kind of digital LDO circuit of fast transient response according to claim 3, it is characterised in that the sampling electricity
Resistance network includes concatenated first sampling resistor, the second sampling resistor, third sampling resistor and the 4th sampling resistor, and described the
One end of one sampling resistor is electric with the input of capacitor in each drain terminal and the piece of the PMOS transistor array respectively
Pole connection, the other end of first sampling resistor are connect with one end of second sampling resistor, and described second adopts
The other end of sample resistance is connect with one end of the third sampling resistor, the other end of the third sampling resistor with it is described
The 4th sampling resistor one end connection, the output electrode of capacitor in the other end of the 4th sampling resistor and the piece
Connect and ground.
5. a kind of digital LDO circuit of fast transient response according to claim 4, it is characterised in that the clock ratio
It include the first clocked comparator, the second clocked comparator and third clocked comparator compared with device array, first clock compares
The positive input terminal of device is connect with the other end of first sampling resistor, the negative input end of first clocked comparator with
The external reference voltage connection, the positive input terminal of second clocked comparator are another with second sampling resistor
One end connection, the negative input end of second clocked comparator are connect with the external reference voltage, the third clock
The positive input terminal of control comparator is connect with the other end of the third sampling resistor, and bearing for the third clocked comparator is defeated
Enter end to connect with the external reference voltage, first clocked comparator, the second clocked comparator and third clock ratio
It is connect respectively with the external sampling clock compared with the clock enable end of device, first clocked comparator, the second clock ratio
It is connect respectively with the signal input part of the controller compared with device and the signal output end of third clocked comparator.
6. a kind of digital LDO circuit of fast transient response according to claim 5, it is characterised in that first clock
Control comparator is used to judge whether the output voltage reaches the high threshold voltage for opening dichotomy adjustment, the third clock
Control comparator is used to judge whether the output voltage reaches the low threshold voltage for opening dichotomy adjustment, second clock
Control comparator is used to judge each adjustment week by comparing the size of the output voltage and the rated output voltage
The interim conducting number for whether needing to increase and decrease power switch, and it is sent to signal form the signal input of the controller
End, after opening dichotomy adjustment, the controller is according to the signal of second clocked comparator, at fixed n
By n wheel adjustment in clock cycle, the output voltage is quickly adjusted to tending to the rated output voltage.
7. a kind of digital LDO circuit of fast transient response according to claim 6, it is characterised in that open dichotomy tune
After whole, the variable quantity for the power switch number that the controller is connected in the 1st wheel adjustment is the array of power switches
The half of middle power switch sum, i.e., 2n-1；The power switch number that the controller is connected in the 2nd wheel adjustment
Variable quantity is the half of the variable quantity of power switch number be connected in last round of adjustment, i.e., 2n-2；And so on, it is described
The variable quantity of power switch number that is connected in the n-th wheel adjustment of controller be 1, dichotomy adjustment terminates.
8. a kind of digital LDO circuit of fast transient response according to claim 7, it is characterised in that triggering is described
The threshold voltage of first clocked comparator, the second clocked comparator and the overturning of third clocked comparator is denoted as V respectivelyOUT1、VOUT2
And VOUT3, the output voltage of circuit is denoted as VOUT, the rated output voltage of circuit is denoted as VRATED, VOUT3 be the height
Threshold voltage, VOUT1 is the low threshold voltage, in which:
VRATED=VOUT2
In formula, VREFFor the external reference voltage, R1 is first sampling resistor, and R2 is the second sampling electricity
Resistance, R3 are the third sampling resistor, and R4 is the 4th sampling resistor；
When circuit work is in stable state, in each clock cycle, output voltage VOUTSize in VOUTWave above and below near 2
Dynamic, fluctuating range is that voltage amplitude caused by the increase and decrease of number is connected in single power switch；
When load jump, VOUTIt jumps therewith, if VOUT1<VOUT<VOUT3, then illustrate that load jump leads to the small amplitude wave of output voltage
It moves, then VOUTRestore output voltage to stablizing shape by the increase and decrease that number is connected in single power switch within n clock cycle
State；If VOUTBy VOUT1<VOUT<VOUT3 change to VOUT<VOUT1 or VOUT>VOUT3, then illustrate that load jump causes output voltage big
Amplitude wave is dynamic, triggers the first clocked comparator or third clocked comparator to the controller and issues signal, the controller
Dichotomy adjustment is opened, V is worked asOUT<VOUT2, second clocked comparator needs to increase function to the controller sending
The signal of the conducting number of rate switch；Work as VOUT>VOUT2, second clocked comparator is issued to the controller to be needed
Reduce the signal of the conducting number of power switch.
9. a kind of digital LDO circuit of fast transient response according to claim 7, it is characterised in that adjusted in dichotomy
In any one wheel adjustment of period, if the power switch number be connected after adjustment is greater than power in the array of power switches and opens
It closes sum or less than zero, then the power switch invariable number before the controller keeps the wheel to adjust is until next round adjustment.
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| CN110647205A (en) * | 2019-09-27 | 2020-01-03 | 广东工业大学 | LDO (low dropout regulator) circuit without off-chip capacitor and power management system |
| CN110703843A (en) * | 2019-10-12 | 2020-01-17 | 佛山科学技术学院 | Digital-analog mixed low-voltage drop voltage stabilizer circuit |
| CN110780700A (en) * | 2019-11-07 | 2020-02-11 | 福州大学 | Novel digital LDO circuit adopting BF quantizer |
| CN111124025A (en) * | 2019-12-12 | 2020-05-08 | 芯创智（北京）微电子有限公司 | Low-noise linear voltage stabilizing circuit and implementation method thereof |
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| CN111555613B (en) * | 2020-04-30 | 2021-05-11 | 东南大学 | Digital LDO circuit of quick adjustment |
| CN111555613A (en) * | 2020-04-30 | 2020-08-18 | 东南大学 | Digital LDO circuit of quick adjustment |
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| CN114815945A (en) * | 2022-04-28 | 2022-07-29 | 西安交通大学 | Double-loop digital LDO structure with adjustable step length and control method |
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