CN110045774B - Digital LDO circuit with fast transient response - Google Patents

Digital LDO circuit with fast transient response Download PDF

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CN110045774B
CN110045774B CN201910264898.6A CN201910264898A CN110045774B CN 110045774 B CN110045774 B CN 110045774B CN 201910264898 A CN201910264898 A CN 201910264898A CN 110045774 B CN110045774 B CN 110045774B
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output voltage
sampling resistor
controller
adjustment
clock
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CN110045774A (en
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钱利波
励达
何锡涛
桑吉飞
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Ningbo University
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Ningbo University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Abstract

The invention discloses a digital LDO circuit with fast transient response, which comprises a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor, wherein the controller is used for controlling the number of conducted power switches in the power switch array so as to adjust the output voltage, and when the output voltage fluctuates greatly due to load jump, the controller starts bisection adjustment to quickly recover the output voltage to a stable state which tends to the rated output voltage of the circuit. The digital LDO circuit has higher transient response speed when facing the output voltage jump caused by different load changes, and the output voltage is recovered to the rated value through a nearly fixed quick adjustment period in the transient response. Compared with other LDO circuits, the digital LDO circuit adopts a pure digital unit circuit structure, can work in a sub-1V low power supply voltage environment, and has the advantages of low static power consumption, high integration level and fast transient response.

Description

Digital LDO circuit with fast transient response
Technical Field
The invention relates to the technical field of integrated circuit power management and Analog and digital-Analog Mixed Signal Circuits and Systems (AMSCS), in particular to a digital LDO circuit with fast transient response.
Background
In recent years, electronic devices such as mobile phones, electronic bracelets, tablet computers and the like are becoming more and more thin, and the integration level of internal systems on chip (SoC) is becoming higher and higher, which means that the energy consumption required by the operation of the devices is greatly increased and the battery capacity is not increased accordingly. In order to improve the endurance of these devices and provide a good working voltage, it is necessary to introduce a power management chip between the power supply and these modules, which plays roles of converting, distributing, detecting, stabilizing and reducing noise of electric energy, and at the same time, these power management chips need to meet their own low power consumption requirements, so that the devices can operate for a longer time.
A Low Dropout Regulator (LDO) has advantages of simple circuit, Low noise and Low power consumption, and is widely used in power management chips. The conventional Analog LDO (ALDO) requires a decoupling capacitor of the order of μ F off-chip to obtain good ripple immunity and excellent transient response characteristics. While the development of the system-in-package technology puts high requirements on the power consumption and the size of the LDO, the ALDO without the off-chip capacitor needs an additional complex compensation network in order to reduce the chip area and maintain better stability. Meanwhile, with the continuous reduction of the CMOS process size and the continuous increase of the requirement for low power consumption, Very Large Scale Integration (VLSI) circuits are even required to operate in a low voltage (0.5V) state, and the operating voltage close to the threshold voltage level of the MOS transistor will make the ALDO difficult to design.
To solve the problem of the inability to work in low voltage environments, Digital LDO (DLDO) was proposed. Fig. 1 shows a simplified schematic diagram of the ALDO, which mainly includes an error amplifier and a power transistor. Fig. 2 shows a schematic diagram of a DLDO, which replaces an error amplifier in the ALDO with a clocked comparator, replaces a single high power transistor in the ALDO with a set of power switch arrays, and uses a controller based on a set of bidirectional shift registers to change the turn-on number of the power switch arrays so as to keep the output voltage stable, compared with the ALDO. The all-digital architecture enables DLDO to achieve lower operating voltage, higher process scalability and lower static power consumption. However, DLDO has poor transient response, i.e. when the load of LDO changes suddenly, the output voltage will jump (the amplitude of the jump changes with the magnitude of the load change). ALDO can quickly adjust the output voltage to a rated level through an error amplifier and a power tube, while DLDO can only adjust the number of power switches through sampling results of a sampling clock, and the recovery speed of the DLDO is limited by the clock frequency and the unit clock change number of the power switches. Since the earliest DLDO can only tune one power switch per clock cycle, its transient response speed is very slow. Increasing the frequency of the sampling clock can increase the transient response speed, but will correspondingly increase the dynamic power consumption of the LDO. Increasing the width-to-length ratio of the power switch can also increase the speed of transient response, but can affect the accuracy of the final stable voltage of the LDO. The method adopts a control mode combining coarse tuning and fine tuning, realizes quick adjustment by changing the number of power switches by N times through the unit clock at the early stage, realizes precision control by changing the number of the power switches by 1 time through the unit clock at the later stage, and is a common DLDO control scheme. However, this solution has certain limitations, and there is a possibility that the transient response speed is not optimized well when dealing with different load changes.
Disclosure of Invention
The invention provides a new DLDO circuit with more reusability and fast transient response.A dichotomy adjustment is adopted as a core control scheme of a controller in the digital LDO circuit, and in the transient response, the output voltage is recovered to a rated value through a nearly fixed fast adjustment period; the digital LDO circuit adopts a circuit structure of a pure digital unit, can work in a sub-1V low power supply voltage environment, and has the advantages of low static power consumption, high integration level and fast transient response.
The technical scheme adopted by the invention is as follows: a digital LDO circuit with fast transient response comprises a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor, wherein the positive input end of the clock-controlled comparator array is connected with the output end of the sampling resistor network, the negative input end of the clock-controlled comparator array is connected with an external reference voltage, the signal output end of the clock-controlled comparator array is connected with the signal input end of the controller, the clock enable end of the clock-controlled comparator array and the clock input end of the controller are respectively connected with an external sampling clock, the signal output end of the controller is connected with the input end of the power switch array, the output end of the power switch array is respectively connected with the input electrode of the sampling resistor network, the input electrode of the on-chip capacitor and the output voltage, the output electrode of the sampling resistor network and the output electrode of the on-chip capacitor are connected and grounded, the output voltage is connected with a load, the load is grounded, the controller is used for controlling the number of the power switches conducted in the power switch array so as to adjust the output voltage, and when the output voltage fluctuates greatly due to load jump, the controller starts bisection adjustment to quickly recover the output voltage to a stable state which tends to the rated output voltage of the circuit.
Preferably, the power switch array is a group of PMOS transistor arrays distributed in binary in number and connected in parallel, a signal output end of the controller is connected to each gate end of the PMOS transistor array, each source end of the PMOS transistor array is connected to an external input voltage, and each drain end of the PMOS transistor array is connected to the input electrode of the sampling resistor network, the input electrode of the on-chip capacitor, and the output voltage.
Preferably, the PMOS transistor array comprises n columns of PMOS transistor groups, and the PMOS transistor group in the jth column consists of 2 according to binary distributionj-1The PMOS transistors are connected in parallel, wherein j is more than or equal to 1 and less than or equal to n, and j belongs to Z; the width-to-length ratio W/L of the PMOS transistor groups in each row is as follows from small to large: delta, 22·δ、23·δ、…、2n-1δ, where δ is the width-to-length ratio of a single PMOS transistor; the controller outputs a group of n-bit binary signals to control the number of the conducted power switches in the power switch array. The PMOS transistor array comprises 2n1 identical PMOS transistors with width-to-length ratio delta, the number of which is approximately 2n. When the PMOS transistor is turned on and is regarded as binary '1' and turned off and is regarded as '0', the switch state of the power switch array and the number of the power switches which are turned on in the power switch array can be represented by a group of n-bit binary numbers, so that the controller generates a group of n-bit binary signals to control the number of the power switches which are turned on in the power switch array. With the change of the output voltage of the digital LDO circuit, the n-bit binary signal can be changed by the controller, so that the dynamic regulation of the output voltage of the digital LDO circuit is realized, and the output voltage is quickly recovered in transient response and is kept above or below the rated output voltage. Wherein n determines the transient response speed of the digital LDO circuit, δ determines the accuracy of the output voltage of the digital LDO circuit, and n and δ together determine the load range of the digital LDO circuit.
Preferably, the sampling resistor network comprises a first sampling resistor, a second sampling resistor, a third sampling resistor and a fourth sampling resistor which are connected in series, one end of the first sampling resistor is connected with each drain terminal of the PMOS transistor array and the input electrode of the on-chip capacitor, the other end of the first sampling resistor is connected with one end of the second sampling resistor, the other end of the second sampling resistor is connected with one end of the third sampling resistor, the other end of the third sampling resistor is connected with one end of the fourth sampling resistor, and the other end of the fourth sampling resistor is connected with the output electrode of the on-chip capacitor and grounded.
Preferably, the clocked comparator array includes a first clocked comparator, a second clocked comparator and a third clocked comparator, a positive input terminal of the first clocked comparator is connected to the other end of the first sampling resistor, a negative input terminal of the first clocked comparator is connected to the external reference voltage, a positive input terminal of the second clocked comparator is connected to the other end of the second sampling resistor, a negative input terminal of the second clocked comparator is connected to the external reference voltage, a positive input terminal of the third clocked comparator is connected to the other end of the third sampling resistor, a negative input terminal of the third clocked comparator is connected to the external reference voltage, clock enable terminals of the first clocked comparator, the second clocked comparator and the third clocked comparator are respectively connected to the external sampling clock, and the signal output ends of the first clock-controlled comparator, the second clock-controlled comparator and the third clock-controlled comparator are respectively connected with the signal input end of the controller. When the rising edge of the sampling clock comes, the first clock-controlled comparator, the second clock-controlled comparator and the third clock-controlled comparator respectively compare the voltage values of the positive input end and the negative input end, and respectively output a high level 1 or a low level 0 according to the comparison result, namely, if the voltage value of the positive input end of each clock-controlled comparator is greater than the voltage value of the negative input end, each clock-controlled comparator respectively outputs a high level 1; if the voltage value of the positive input end of each clocked comparator is smaller than that of the negative input end, each clocked comparator outputs a low level "0" respectively.
Preferably, the first clocked comparator is configured to determine whether the output voltage reaches a high threshold voltage for turning on the bisection adjustment, the third clocked comparator is configured to determine whether the output voltage reaches a low threshold voltage for turning on the bisection adjustment, the second clocked comparator is configured to determine whether the number of power switches that are turned on needs to be increased or decreased in each adjustment cycle by comparing the output voltage with the rated output voltage, and send the determination result to the signal input terminal of the controller in a signal form, and after the bisection adjustment is turned on, the controller performs n-round adjustment in fixed n clock cycles according to a signal of the second clocked comparator, so as to quickly adjust the output voltage to approach the rated output voltage.
Preferably, after the bisection adjustment is turned on, the amount of change of the number of the power switches turned on by the controller in the 1 st adjustment is one half of the total number of the power switches in the power switch array, that is, 2n-1(ii) a The variation of the number of the power switches conducted by the controller in the 2 nd adjustment is one half of the variation of the number of the power switches conducted in the previous adjustment, namely 2n-2(ii) a In this way, the variation of the number of the power switches which are switched on by the controller in the nth adjustment is 1, and the dichotomy adjustment is finished.
Preferably, the threshold voltages triggering the inversion of the first clocked comparator, the second clocked comparator and the third clocked comparator are respectively recorded as V OUT1、V OUT2 and V OUT3, the output voltage of the circuit is denoted as VOUTLet the rated output voltage of the circuit be VRATED，V OUT3 is said high threshold voltage, V OUT1 is the low threshold voltage, wherein:
Figure BDA0002016476430000041
Figure BDA0002016476430000042
Figure BDA0002016476430000043
VRATED＝V OUT2
in the formula, VREFFor the external reference voltage, R1 is the first sampling resistor, R2 is the second sampling resistor, R3 is the third sampling resistor, and R4 is the fourth sampling resistor;
when the circuit is operated in a stable state, the output voltage V is in each clock cycleOUTIs in the size V OUT2, fluctuating up and down, wherein the fluctuation amplitude is the voltage amplitude generated by the increase and decrease of the conduction number of a single power switch;
when the load jumps, VOUTJump with it if V OUT1<VOUT<V OUT3, it shows that the load jump causes the output voltage to fluctuate slightly, then VOUTThe output voltage is recovered to a stable state through increasing and decreasing the conducting number of a single power switch in n clock cycles; if VOUTFrom V OUT1<VOUT<V OUT3 to VOUT<V OUT1 or VOUT>VOUTAnd 3, the output voltage is greatly fluctuated due to load jump, the first clocked comparator or the third clocked comparator is triggered to send a signal to the controller, the controller immediately starts dichotomy adjustment, and when V is regulatedOUT<V OUT2, the second clocked comparator sends a signal to the controller that the number of power switches to be turned on needs to be increased; when V isOUT>V OUT2, said second clocked comparator signals to said controller that a reduced number of power switch conductions is required.
The basis for judging the two load jumps is as follows: vOUT2-V OUT1＝VOUT3-V OUT2≈n×VδIn which V isδThe voltage amplitude that varies for a single power switch. No matter how the load jumps, the transient response recovery time of the digital LDO circuit is within n clock cycles, so that the rapid transient response is realized.
Preferably, in any round of adjustment during the bisection adjustment, if the number of the power switches turned on after adjustment is greater than the total number of the power switches in the power switch array or less than zero, the controller keeps the number of the power switches before the round of adjustment unchanged until the next round of adjustment.
Compared with the prior art, the invention has the advantages that:
(1) the invention discloses a digital LDO circuit with fast transient response, which adopts dichotomy adjustment as a core control scheme of a controller. When the output voltage has large jump, starting a dichotomy to adjust the number of the power tubes, and adjusting the output voltage to a rated level in a short fixed period; when the output voltage has small jump, the output voltage is regulated to a rated level by adopting a traditional mode of gradually regulating the number of power tubes. Therefore, the digital LDO circuit has higher transient response speed when the output voltage jumps caused by different load changes, and the output voltage is recovered to the rated value through a nearly fixed and quick adjustment period in the transient response.
(2) Compared with other LDO circuits, the digital LDO circuit with the fast transient response disclosed by the invention adopts a pure digital unit circuit structure, can work in a sub-1V low power supply voltage environment, and has the advantages of low static power consumption, high integration level and fast transient response.
Drawings
FIG. 1 is a simplified schematic diagram of a conventional analog LDO circuit;
FIG. 2 is a simplified schematic diagram of a conventional digital LDO circuit;
FIG. 3 is a schematic diagram of a digital LDO circuit according to an embodiment;
FIG. 4 is a diagram illustrating an operation state of a clocked comparator array according to an embodiment;
FIG. 5 is a load transient response characteristic of the digital LDO circuit of the embodiment;
FIG. 6 is a schematic flow chart of dichotomy adjustment in the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples.
The digital LDO circuit with fast transient response of the embodiment comprises a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an in-chip capacitor, wherein a positive input end of the clock-controlled comparator array is connected with an output end of the sampling resistor network, a negative input end of the clock-controlled comparator array is connected with an external reference voltage, a signal output end of the clock-controlled comparator array is connected with a signal input end of the controller, a clock enable end of the clock-controlled comparator array and a clock input end of the controller are respectively connected with an external sampling clock, a signal output end of the controller is connected with an input end of the power switch array, an output end of the power switch array is respectively connected with an input electrode of the sampling resistor network, an input electrode of the in-chip capacitor and an output voltage, an output electrode of the sampling resistor network and an output electrode of the in-chip capacitor are connected and grounded, the output voltage is connected with the load, the load is grounded, the controller is used for controlling the number of the conducted power switches in the power switch array, the output voltage is further adjusted, and when the output voltage fluctuates greatly due to load jumping, the controller starts dichotomy adjustment to quickly restore the output voltage to a stable state which tends to the rated output voltage of the circuit.
In this embodiment, the power switch array is a group of PMOS transistor arrays distributed in binary in parallel, a signal output end of the controller is connected to each gate end of the PMOS transistor array, each source end of the PMOS transistor array is connected to an external input voltage, and each drain end of the PMOS transistor array is connected to an input electrode of the sampling resistor network, an input electrode of the on-chip capacitor, and an output voltage.
The PMOS transistor array comprises 7 columns of PMOS transistor groups, and the PMOS transistor group in the jth column consists of 2 columns of PMOS transistor groups according to binary distributionj-1The PMOS transistors are connected in parallel, wherein j is more than or equal to 1 and less than or equal to 7, and j belongs to Z; the width-to-length ratio W/L of the PMOS transistor groups in each row is as follows from small to large: delta, 22·δ、23·δ、24·δ、25·δ、26δ, where δ is the width-to-length ratio of a single PMOS transistor; turning on the PMOS transistor is treated as a binary "1",if the turn-off is regarded as "0", the switch state of the power switch array and the number of the power switches turned on in the power switch array can be represented by a set of 7-bit binary signals, that is, the controller outputs a set of 7-bit binary signals to control the number of the power switches turned on in the power switch array.
The sampling resistor network comprises a first sampling resistor R1, a second sampling resistor R2, a third sampling resistor R3 and a fourth sampling resistor R4 which are connected in series, one end of the first sampling resistor R1 is connected with each drain terminal of the PMOS transistor array and an input electrode of an on-chip capacitor respectively, the other end of the first sampling resistor R1 is connected with one end of a second sampling resistor R2, the other end of the second sampling resistor R2 is connected with one end of the third sampling resistor R3, the other end of the third sampling resistor R3 is connected with one end of the fourth sampling resistor R4, and the other end of the fourth sampling resistor R4 is connected with an output electrode of the on-chip capacitor and grounded.
The clocked comparator array comprises a first clocked comparator CP1, a second clocked comparator CP2, and a third clocked comparator CP3, a positive input V of the first clocked comparator CP1HConnected with the other end of the first sampling resistor R1, the negative input end of the first clocked comparator CP1 is connected with an external reference voltage, and the positive input end V of the second clocked comparator CP2MIs connected with the other end of the second sampling resistor R2, the negative input end of the second clocked comparator CP2 is connected with an external reference voltage, and the positive input end V of the third clocked comparator CP3LThe negative input end of the third clocked comparator CP3 is connected to an external reference voltage, the clock enable ends of the first clocked comparator CP1, the second clocked comparator CP2 and the third clocked comparator CP3 are respectively connected to an external sampling clock, and the signal output ends of the first clocked comparator CP1, the second clocked comparator CP2 and the third clocked comparator CP3 are respectively connected to the signal input end of the controller.
The first clocked comparator CP1 is used for judging whether the output voltage reaches a high threshold voltage for starting the dichotomy adjustment, the third clocked comparator CP3 is used for judging whether the output voltage reaches a low threshold voltage for starting the dichotomy adjustment, the second clocked comparator CP2 is used for judging whether the conducting number of the power switch needs to be increased or decreased in each adjustment period by comparing the output voltage with the rated output voltage, the conducting number is sent to a signal input end of the controller in a signal form, and after the dichotomy adjustment is started, the controller conducts 7 rounds of adjustment in 7 fixed clock periods according to the signal of the second clocked comparator CP2, and the output voltage is quickly adjusted to be close to the rated output voltage.
After the bisection adjustment is started, the variable quantity of the number of the power switches conducted by the controller in the 1 st adjustment is one half of the total number of the power switches in the power switch array, namely 26(ii) a The variation of the number of the power switches conducted by the controller in the 2 nd adjustment is half of the variation of the number of the power switches conducted in the previous adjustment, that is, 25(ii) a In this way, the variation of the number of the power switches turned on by the controller in the 7 th adjustment is 1, and the bisection adjustment is finished. In any round of adjustment during the dichotomy adjustment, if the number of the power switches which are conducted after the adjustment is larger than the total number of the power switches in the power switch array or smaller than zero, the controller keeps the number of the power switches before the adjustment in the round unchanged until the adjustment in the next round.
As shown in fig. 4, the threshold voltages triggering the first, second, and third clocked comparators CP1, CP2, and CP3 to flip are respectively denoted as V OUT1、V OUT2 and V OUT3, the output voltage of the circuit is denoted as VOUTLet the rated output voltage of the circuit be VRATED，V OUT3 is the high threshold voltage, V OUT1 is the low threshold voltage, wherein:
Figure BDA0002016476430000071
Figure BDA0002016476430000072
Figure BDA0002016476430000073
VRATED＝V OUT2
in the formula, VREFFor external reference voltage, R1 is a first sampling resistor R1, R2 is a second sampling resistor R2, R3 is a third sampling resistor R3, and R4 is a fourth sampling resistor R4;
when the circuit is operated in a stable state, the output voltage V is in each clock cycleOUTIs in the size V OUT2, fluctuating up and down, wherein the fluctuation amplitude is the voltage amplitude generated by the increase and decrease of the conduction number of a single power switch;
when the load jumps, VOUTJump with it if V OUT1<VOUT<V OUT3, it shows that the load jump causes the output voltage to fluctuate slightly, then VOUTThe output voltage is recovered to a stable state through increasing and decreasing the conducting number of a single power switch in n clock cycles; if VOUTFrom V OUT1<VOUT<V OUT3 to VOUT<V OUT1 or VOUT>V OUT3, it indicates that the load jump causes a large fluctuation of the output voltage, i.e. the output signal H of the first clocked comparator CP1 changes from "1" to "0" or the output signal L of the third clocked comparator CP3 changes from "0" to "1", and triggers the first clocked comparator CP1 or the third clocked comparator CP3 to send a signal to the controller, and the controller starts the dichotomy adjustment, and quickly sets V in a fixed adjustment periodOUTIs restored to VOUTAround 2. When V isOUT<V OUT2, namely the output signal M of the second clocked comparator CP2 is "0", the second clocked comparator CP2 sends a signal to the controller that the on-number of the power switch needs to be increased; when V isOUT>V OUT2, i.e., the output signal M of the second clocked comparator is "1", the second clocked comparator CP2 signals to the controller that the number of conduction of the power switches needs to be reduced.
Specifically, the digital LDO circuit causes the output voltage V of the circuit to change if the load changes during the operationOUTLower than the low threshold voltage of the dichotomy adjustment, i.e.
Figure BDA0002016476430000081
The third clocked comparator CP3 outputs a signal L to the controller to initiate a divide-by-two adjustment, which is obvious
Figure BDA0002016476430000082
Then in the dichotomy round 1 adjustment, the number of conduction of the current PMOS power switches needs to be increased by a dichotomy value (power switch change amount) of round 1, which is one half of the total number of power switches, i.e. 26The adder in the controller adds the two groups of 7-bit binary numbers and outputs the binary numbers to the PMOS power switch array, so that the conduction number of the PMOS power switch array is increased, the output current of the PMOS power switch array is increased, and the output voltage V is further improvedOUTThen, the updated output voltage V is compared according to the second clocked comparator CP2OUTAnd rated output voltage VRATEDIf V isOUT<VRATEDThe number of conduction of the PMOS power switches needs to be increased by half for round 2, and conversely, the number of conduction will be decreased by two for round 2, where the two for round 2 is one half of that for round 1, i.e. 25And then again based on the updated VOUTEntering the adjustment of the 3 rd round, during the adjustment, if the conducting number of the changed power switch exceeds the range (is larger than the total number 127 or is smaller than 0), keeping the original switch state unchanged, entering the next round of adjustment, and so on, the second score of the 7 th round is 1, at this time, the change amount of the power switch of the circuit already approximately traverses the total number of the power switch, therefore, the output voltage V of the circuitOUTTo rated voltage VRATEDQuite close to each other, when the 7 th round of adjustment is finished, namely the dichotomy adjustment is finished, the circuit restores the common adjustment mode, namely only 1 power switch is changed in each adjustment period, and the output voltage V is outputOUTWill be at rated voltage VRATEDApproaching up and down, the output voltage V of the circuitOUTRecovering the stability; if the load changes, the output voltage V of the circuit is causedOUTHigh threshold voltages adjusted beyond dichotomy, i.e.
Figure BDA0002016476430000083
The first clocked comparator CP1 outputs a signal H to the controller to initiate a dichotomy adjustment, which is obvious
Figure BDA0002016476430000084
Then in the dichotomy round 1 adjustment, the number of conduction of the current PMOS power switches needs to be reduced by a dichotomy value of round 1, i.e. 26The binary numbers of the two groups of 7-bits are subtracted in the controller and then output to the PMOS power switch array (the subtraction can be realized by supplementing and then adding the subtracted numbers), so that the conduction number of the PMOS power switch array is reduced, the output current of the PMOS power switch array is reduced, and the output voltage V is further reducedOUTThe subsequent adjustment is the same as above. During the dichotomy adjustment, the output signals H, L of the first and third clocked comparators CP1 and CP3 are put into a sleep state, and the normal state is not restored until the dichotomy adjustment is completed.
Setting the input voltage V in the present embodimentINIs 0.6V, reference voltage VREFThe voltage is 0.5V, the rated output voltage is 0.55V, the sampling clock CLK is 10MHz, the on-chip capacitance is 100pF, and a frequency divider is added in the controller to change the adjusting period of the controller into 5 multiplied by 100ns in consideration of the delay of an internal circuit and the charge and discharge speed of a load. Fig. 5 shows a load transient response characteristic curve of the digital LDO circuit in this embodiment, and it can be seen that when the load of the LDO circuit jumps from a light load (2mA) to a heavy load (20mA) or from a heavy load (20mA) to a light load (2mA), the circuit is turned on for halving, and the output voltage V is outputOUTThe time required for restoring the rated level is about 3.3 mus (7 multiplied by 5 multiplied by 100ns), and the device has the characteristic of quick transient response.
The flow chart of the dichotomy adjustment in the invention is shown in figure 6. As shown in fig. 6, the operation principle of the dichotomy adjustment is as follows:
first, the total number of power switches included in the power switch array is set to N ═ 1+2+4+8+ … +2n-1≈2nWhen the circuit is operated in a steady state, the number of switches that are currently on is about X, which is represented by a set of n-bit binary numbers.
When the load jumps, the output signal H of the first clocked comparator changes from '1' to '0' or the output signal L of the third clocked comparator changes from '0' to '1', and the dichotomy adjustment is started. At this time, the process of the present invention,in the 1 st round of adjustment period, the number of the power switches to be changed is set to be one half of the total number of the switches, namely the initial value of the dichotomy factor i is set to be 1, and then the number of the power switches to be changed in the first round of adjustment period
Figure BDA0002016476430000091
This value is also represented by a set of n-bit binary numbers.
Then, the output voltage V of X power switches is switched on currently according to the comparison circuit of the second clocked comparatorOUT(X) and rated output voltage VRATEDTo determine whether K conducting power switches need to be increased or decreased. If the output signal M of the second clocked comparator is "0", the number of the turned-on power switches needs to be increased, that is, X is X + K; if the output signal M of the second clocked comparator is "1", the number of power switches that are turned on needs to be reduced, i.e. X-K.
There are upper and lower limits to X that must not exceed the total number of power switches N and must not be negative. Thus, when X + K > N or X-K <0, the conducting power switches are kept unchanged in number from the power switches before the round of adjustment until the next round of adjustment.
After the adjustment of X is completed, the output voltage of the circuit is also dynamically adjusted, and then the adjustment of 2 nd round is performed. The power switch change amount of the 2 nd round is one half of the previous round, so the dichotomy factor i is i +1, the change amount of the power switch
Figure BDA0002016476430000092
The subsequent adjustment scheme is consistent with the previous adjustment.
Finally, through n rounds of adjustment, the change K of the power switch is 1, i is log2N is approximately equal to N, and the dichotomy adjustment is finished. At this time, the variation of the power switches in the whole dichotomy adjusting period traverses the total number of the power switches, and the output voltage VOUTIs also restored to the rated output voltage VRATEDNearby.
In the dichotomy adjustment, the starting mechanism of the dichotomy is in a dormant state, repeated triggering is avoided, and the starting mechanism is not recovered to be normal until the adjustment is finished.

Claims (9)

1. A digital LDO circuit with fast transient response is characterized by comprising a clock-controlled comparator array, a controller, a power switch array, a sampling resistor network and an on-chip capacitor, wherein the positive input end of the clock-controlled comparator array is connected with the output end of the sampling resistor network, the negative input end of the clock-controlled comparator array is connected with an external reference voltage, the signal output end of the clock-controlled comparator array is connected with the signal input end of the controller, the clock enable end of the clock-controlled comparator array and the clock input end of the controller are respectively connected with an external sampling clock, the signal output end of the controller is connected with the input end of the power switch array, and the output end of the power switch array is respectively connected with the input electrode of the sampling resistor network, the input electrode of the on-chip capacitor and the output voltage of the on-chip capacitor, the output electrode of the sampling resistor network and the output electrode of the on-chip capacitor are connected and grounded, the output voltage is connected with a load, the load is grounded, the controller is used for controlling the number of the power switches conducted in the power switch array so as to adjust the output voltage, and when the output voltage fluctuates greatly due to load jump, the controller starts bisection adjustment to quickly recover the output voltage to a stable state which tends to the rated output voltage of the circuit.
2. The fast transient response digital LDO circuit of claim 1, wherein the power switch array is a set of binary distributed PMOS transistor arrays connected in parallel, the signal output terminal of the controller is connected to each gate terminal of the PMOS transistor array, each source terminal of the PMOS transistor array is connected to an external input voltage, and each drain terminal of the PMOS transistor array is connected to the input electrode of the sampling resistor network and the input electrode and the output voltage of the on-chip capacitor, respectively.
3. Root of herbaceous plantThe fast transient response digital LDO circuit of claim 2, wherein said PMOS transistor array comprises n columns of PMOS transistor groups, and the number of PMOS transistor groups in the jth column is 2 according to a binary distributionj-1The PMOS transistors are connected in parallel, wherein j is more than or equal to 1 and less than or equal to n, and j belongs to Z; the width-to-length ratio W/L of the PMOS transistor groups in each row is as follows from small to large: delta, 22·δ、23·δ、…、2n-1δ, where δ is the width-to-length ratio of a single PMOS transistor; the controller outputs a group of n-bit binary signals to control the number of the conducted power switches in the power switch array.
4. The fast transient response digital LDO circuit of claim 3, wherein said sampling resistor network comprises a first sampling resistor, a second sampling resistor, a third sampling resistor and a fourth sampling resistor connected in series, one end of said first sampling resistor is connected to each drain of said PMOS transistor array and said input electrode of said on-chip capacitor, the other end of said first sampling resistor is connected to one end of said second sampling resistor, the other end of said second sampling resistor is connected to one end of said third sampling resistor, the other end of said third sampling resistor is connected to one end of said fourth sampling resistor, and the other end of said fourth sampling resistor is connected to said output electrode of said on-chip capacitor and grounded.
5. The fast transient response digital LDO circuit of claim 4, wherein said clocked comparator array comprises a first clocked comparator, a second clocked comparator and a third clocked comparator, wherein a positive input of said first clocked comparator is connected to another terminal of said first sampling resistor, a negative input of said first clocked comparator is connected to said external reference voltage, a positive input of said second clocked comparator is connected to another terminal of said second sampling resistor, a negative input of said second clocked comparator is connected to said external reference voltage, a positive input of said third clocked comparator is connected to another terminal of said third sampling resistor, a negative input of said third clocked comparator is connected to said external reference voltage, and said first clocked comparator is connected to said first clocked comparator, The clock enable ends of the second clock-controlled comparator and the third clock-controlled comparator are respectively connected with the external sampling clock, and the signal output ends of the first clock-controlled comparator, the second clock-controlled comparator and the third clock-controlled comparator are respectively connected with the signal input end of the controller.
6. The fast transient response digital LDO circuit of claim 5, wherein said first clocked comparator is configured to determine whether said output voltage reaches a high threshold voltage that turns on a binary adjustment, the third clock-controlled comparator is used for judging whether the output voltage reaches a low threshold voltage for starting the dichotomy adjustment, the second clocked comparator is used for judging whether the conducting number of the power switch needs to be increased or decreased in each adjusting period by comparing the output voltage with the rated output voltage and sending the conducting number to the signal input end of the controller in a signal form, after the bisection adjustment is started, the controller controls the comparator to output a signal according to the signal of the second clocked comparator, and adjusting the output voltage to the rated output voltage quickly through n rounds of adjustment within fixed n clock cycles.
7. The fast transient response digital LDO circuit of claim 6, wherein after the binary adjustment is turned on, the controller turns on the number of power switches in the 1 st adjustment by an amount equal to one-half of the total number of power switches in the power switch array, i.e., 2n-1(ii) a The variation of the number of the power switches conducted by the controller in the 2 nd adjustment is one half of the variation of the number of the power switches conducted in the previous adjustment, namely 2n-2(ii) a In this way, the variation of the number of the power switches which are switched on by the controller in the nth adjustment is 1, and the dichotomy adjustment is finished.
8. The fast transient response digital LDO circuit of claim 7, wherein the threshold voltages triggering the first, second and third clocked comparators to flip are denoted as VOUT1、VOUT2 and VOUT3, the output voltage of the circuit is denoted as VOUTLet the rated output voltage of the circuit be VRATED，VOUT3 is said high threshold voltage, VOUT1 is the low threshold voltage, wherein:
Figure FDA0002016476420000021
Figure FDA0002016476420000022
Figure FDA0002016476420000023
VRATED＝VOUT2
in the formula, VREFFor the external reference voltage, R1 is the first sampling resistor, R2 is the second sampling resistor, R3 is the third sampling resistor, and R4 is the fourth sampling resistor;
when the circuit is operated in a stable state, the output voltage V is in each clock cycleOUTIs in the size VOUT2, fluctuating up and down, wherein the fluctuation amplitude is the voltage amplitude generated by the increase and decrease of the conduction number of a single power switch;
when the load jumps, VOUTJump with it if VOUT1<VOUT<VOUT3, it shows that the load jump causes the output voltage to fluctuate slightly, then VOUTThe output voltage is recovered to a stable state through increasing and decreasing the conducting number of a single power switch in n clock cycles; if VOUTFrom VOUT1<VOUT<VOUT3 to VOUT<VOUT1 or VOUT>VOUTAnd 3, the output voltage is greatly fluctuated due to load jump, the first clocked comparator or the third clocked comparator is triggered to send a signal to the controller, the controller immediately starts dichotomy adjustment, and when V is regulatedOUT<VOUT2, the second clocked comparator sends a signal to the controller that the number of power switches to be turned on needs to be increased; when V isOUT>VOUT2, said second clocked comparator signals to said controller that a reduced number of power switch conductions is required.
9. The fast transient response digital LDO circuit of claim 7, wherein in any round of adjustment during the binary adjustment, if the number of switches conducting after adjustment is greater than the total number of switches in said array of switches or less than zero, said controller keeps the number of switches before the round of adjustment unchanged until the next round of adjustment.
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