CN203054660U - Rapid power-cut controlling circuit applied to power supply managing circuit - Google Patents

Abstract

The utility model relates to a fast power-off control circuit applied in a power management circuit, comprising a POR falling edge detection circuit and a PMOS discharge tube Mp2, and the POR falling edge detection circuit includes a delay module, an inverter and an NAND Gate, the input end of the POR falling edge detection circuit is connected with the input end of the delay module and the input end of the inverter, and the output end of the delay module and the output end of the inverter are respectively connected with the two inputs of the NAND gate The output terminal of the POR falling edge detection circuit is connected to the output terminal of the NAND gate; the output terminal of the POR falling edge detection circuit is connected to the gate of the PMOS discharge tube Mp2, and the source of the PMOS discharge tube Mp2 is connected to the power supply voltage Vdd. The drain of the PMOS discharge transistor Mp2 is grounded. When the utility model is applied to the power management circuit, it is ensured that the hardware system is powered off in time during the power-off process of the power supply voltage, so as to avoid the unstable state of some circuits under low voltage conditions, causing the hardware system to issue wrong instructions or execute wrong commands. operate.

Description

A fast power-off control circuit applied in power management circuit

technical field

The utility model relates to a fast power-off control circuit applied in a power management circuit, which belongs to the technical field of power management control circuits.

Background technique

With the increasing role of power management circuits in electronic products, the performance of power circuits in electronic products is becoming more and more important. The power management circuit is used in almost every chip, which requires the power management circuit to have a high index to prolong the use time of electronic products. For example, Low Drop Voltage Regulator (LDO for short) is a commonly used power management circuit. Ordinary LDOs are often connected with a capacitor of several microfarads to ensure stable operation of the circuit. However, in some cases, when the chip is powered off, the power supply voltage drops very slowly due to the low current consumption of the circuit and the large voltage stabilizing capacitor at the power supply voltage terminal, as shown in Figure 1. As a result, during the power-off process of the power supply voltage, because the power supply voltage is already lower than the normal working voltage of the circuit, but it is not 0, some circuits will appear unstable, causing the hardware system to issue wrong instructions or execute wrong operation. Especially in application environments such as contactless smart cards, the power supply voltage is maintained by the charge stored on the capacitor in the chip, and the power-off process will be very slow, which may easily cause logic function or storage errors of the chip during the power-off process.

Contents of the invention

Terminology Explanation

1. LDO: The abbreviation of Low Drop Voltage Regulator, that is, low dropout linear voltage regulator circuit, is a commonly used power management circuit.

2. POR: The abbreviation of Power On Reset, that is, the power-on reset circuit.

Aiming at the deficiencies of the prior art, the utility model provides a fast power-off control circuit applied in a power management circuit, including a POR falling edge detection circuit and a PMOS discharge tube Mp2, and the POR falling edge detection circuit includes a delay module , an inverter and a NAND gate, the input terminal of the POR falling edge detection circuit is connected to the input terminal of the delay module and the input terminal of the inverter, and the output terminal (Delay_out) of the delay module is connected to the output of the inverter The terminal (INV_out) is respectively connected to the two input terminals of the NAND gate, the output terminal (Vctrl) of the POR falling edge detection circuit is connected to the output terminal of the NAND gate; the output terminal (Vctrl) of the POR falling edge detection circuit is connected to the PMOS discharge The gate of the transistor Mp2 is connected, the source of the PMOS discharge transistor Mp2 is connected to the power supply voltage Vdd, and the drain of the PMOS discharge transistor Mp2 is grounded.

When the utility model is applied to a power management circuit, the signal output terminal (POR_out) of the power-on reset circuit in the power management circuit is connected to the input terminal of the POR falling edge detection circuit.

The utility model has the advantages of:

When the utility model is applied to the power management circuit, it is ensured that the hardware system is powered off in time during the power-off process of the power supply voltage, so as to avoid the unstable state of some circuits under low voltage conditions, causing the hardware system to issue wrong instructions or execute wrong commands. operate. It also avoids technical problems such as logic function or storage errors during the power-off process of the chip.

Description of drawings

Fig. 1 is a waveform diagram in an existing power management circuit;

Fig. 2 is a schematic diagram of the POR falling edge detection circuit in the fast power-off control circuit of the present invention;

Figure 3 is a timing diagram of the POR falling edge detection circuit (Figure 2) in the fast power-off control circuit;

4 is a schematic diagram of a fast power-off control circuit in a power management circuit;

Fig. 5 is a waveform diagram of a fast power-off control circuit (Fig. 4) in a power management circuit described in the present invention;

Fig. 6 is the schematic circuit diagram of embodiment 1;

In the figure, 11. Delay module, 12. Inverter, 13. NAND gate, 10. Fast power-off control circuit, 20. POR falling edge detection circuit in the fast power-off control circuit, 30. Low dropout linear stable piezo circuit LDO.

Detailed ways

Below in conjunction with embodiment and accompanying drawing, the utility model is described in detail, but not limited thereto.

Embodiment 1,

The utility model is applied to a low-dropout linear regulator circuit LDO to realize fast power-off.

As shown in Figures 2 and 4, a fast power-off control circuit 10 applied to a power management circuit includes a POR falling edge detection circuit 20 and a PMOS discharge tube Mp2, and the POR falling edge detection circuit 20 includes a delay module 11, inverter 12 and NAND gate 13, the input end of described POR falling edge detection circuit 20 is connected with the input end of delay module 11 and the input end of inverter 12, the output end of delay module 11 (Delay_out ) and the output terminal (INV_out) of the inverter 12 are respectively connected to the two input terminals of the NAND gate 13, and the output terminal (Vctrl) of the POR falling edge detection circuit 20 is connected to the output terminal of the NAND gate 13; the POR falling edge The output terminal (Vctrl) of the detection circuit 20 is connected to the gate of the PMOS discharge transistor Mp2, the source of the PMOS discharge transistor Mp2 is connected to the power supply voltage Vdd, and the drain of the PMOS discharge transistor Mp2 is grounded.

As shown in Figure 6, in the low-dropout linear regulator circuit LDO30, the reference voltage is connected to the negative input terminal of the operational amplifier, the positive input terminal of the operational amplifier is connected to the series node of resistors R1 and R2, and the output terminal of the operational amplifier is connected to The gate of the PMOS transistor Mp1, the source of Mp1 is connected to the power supply voltage Vcc, the drain of Mp1 is connected to the resistor divider R1, R2, where R1 and R2 are connected in series, R2 is grounded, and the drain of Mp1 is connected to a capacitor CL (a few microns in size) method), the other end of the external capacitor CL is grounded, and the terminal voltage of the external capacitor CL is Vdd.

In the fast power-off control circuit 10, when Vdd is high level, the output POR_out signal is "1"; when Vdd is lower than the normal operating voltage, the output POR_out signal is "0".

Comparative example,

If the fast power-off control circuit 10 is not provided in the low-dropout linear regulator circuit 30 , the voltage power-off will become slow because the voltage of the capacitor cannot be changed suddenly, as shown in FIG. 1 .

After the fast power-off control circuit 10 is set in the low-dropout linear regulator circuit 30, as shown in FIG. 6, when the power supply voltage Vdd is lower than the threshold voltage (as shown by the dotted line in FIG. The level becomes low level, and the POR falling edge detection circuit 20 in the fast power-off control circuit 10 correspondingly outputs a low level pulse to turn on the PMOS discharge tube Mp2, and the voltage on the capacitor will be quickly pulled to 0, So as to achieve fast power off. The low-level pulse width (time) ensures that the power supply voltage is pulled down to 0 within this time.

Figure 2 is the falling edge detection circuit of the power-on reset circuit (Power On Reset POR) in the fast power-off control circuit. The delay module 11 generates a certain time delay for the rising edge or falling edge of the input signal. The POR output signal is output along the output terminal POR_out: when the output is low, the circuit is reset; when the output is high, the circuit works normally. 1) When the output terminal POR_out outputs a high level "1", the output of the inverter 12 is a low level "0", and the low level "0" is input to an input terminal of the NAND gate 13; at the same time delay The module 11 outputs the high level "1" to the other input terminal of the NAND gate 13 after a certain time delay, and the NAND gate 13 outputs a high level "1"; 2) When the POR output is switched from high to When the level "1" jumps to a low level "0", the output of the inverter 12 is a high level "1", and the delay module 11 still outputs a high level "1" due to the delay. The level "1" is sent to the NAND gate 13 and the output is a low level "0"; 3) When the POR output is a low level "0", the output of the inverter 12 is a high level "1", and the delay Module 11 also changes to low level "0" after a delay, and the two signals are sent to NAND gate 13 to output a high level "1"; 4) When POR jumps from low level "0" to high When the level is "1", the inverter 12 outputs a low level "0", while the delay module 11 still maintains a low level "0" due to the delay, and the two are sent to the NAND gate 13 to output a high level "1".

From the above analysis, it can be seen that for the falling edge of the POR output terminal POR_out, the NAND gate 13 will output a low level pulse to realize the POR falling edge detection. Figure 3 is a timing diagram of the POR falling edge detection circuit (Figure 2) in the fast power-off control circuit.

FIG. 4 is a fast power-off control circuit in a power management circuit. When the POR output terminal POR_out outputs a high level, it is known from the above analysis that the POR falling edge detection circuit 20 in the fast power-off control circuit outputs a high level, the PMOS discharge tube Mp2 is cut off, and the source keeps the original voltage; when the POR output terminal When POR_out outputs a falling edge, the POR falling edge detection circuit 20 in the fast power-off control circuit outputs a low-level pulse to turn on the PMOS discharge tube Mp2, and the source voltage is pulled to 0 to realize fast power-off. The power supply voltage must be pulled down to 0 within the pulse width of the low-level pulse.

FIG. 5 is a waveform diagram of a fast power-off control circuit ( FIG. 4 ) in a power management circuit described in the present invention. When the POR output terminal POR_out is high level, the circuit works normally, and the voltage Vdd is high level; when the POR output terminal POR_out outputs a falling edge and becomes low level, the utility model circuit will generate a low level pulse, PMOS The discharge tube Mp2 is turned on, and Vdd will be pulled to 0. The low-level pulse width (time) generated by the falling edge detection circuit in the fast power-off control circuit in Figure 2 should ensure that the power supply voltage is pulled down to 0 within this time.

Claims (1)

1. A fast power-off control circuit applied in a power management circuit, characterized in that, the fast power-off control circuit includes a POR falling edge detection circuit and a PMOS discharge tube Mp2, and the POR falling edge detection circuit includes a delay Time module, inverter and NAND gate, the input terminal of the POR falling edge detection circuit is connected with the input terminal of the delay module and the input terminal of the inverter, the output terminal (Delay_out) of the delay module and the inverter The output terminal (INV_out) of the NAND gate is respectively connected to the two input terminals of the NAND gate, and the output terminal (Vctrl) of the POR falling edge detection circuit is connected to the output terminal of the NAND gate; the output terminal (Vctrl) of the POR falling edge detection circuit is connected to the The gate of the PMOS discharge tube Mp2 is connected, the source of the PMOS discharge tube Mp2 is connected to the power supply voltage Vdd, and the drain of the PMOS discharge tube Mp2 is grounded.

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