CN104991113A - Zero cross detection circuit applied to high-frequency switching power supply - Google Patents
Zero cross detection circuit applied to high-frequency switching power supply Download PDFInfo
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- CN104991113A CN104991113A CN201510405927.8A CN201510405927A CN104991113A CN 104991113 A CN104991113 A CN 104991113A CN 201510405927 A CN201510405927 A CN 201510405927A CN 104991113 A CN104991113 A CN 104991113A
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Abstract
The invention provides a zero cross detection circuit applied to a high-frequency switching power supply. The zero cross detection circuit comprises a bias part, a detection part and an output part. The bias part provides bias current to each circuit branch of the a zero cross detection circuit. When a switching tube is disconnected, the detection part detects rectifier tube drain electrode voltage VX. When VX rises to 0V from a negative value, low level is outputted and the rectifier tube is disconnected so that generation of reverse current can be prevented. The output part is used for adjusting output waveform and increasing driving capacity of the detection circuit. The circuit form is simple, and the required static current is low and power consumption is low; and the jump points of zero cross detection can be adjusted according to the size of bias current so that use range is wide, and the zero cross detection circuit can be used for zero cross detection of a low-frequency switching power supply and can also be used for a high-frequency switching power supply.
Description
Technical field
The present invention relates to the power management module in analogue layout field, be specifically related to a kind of zero cross detection circuit be applied in high frequency switch power.
Background technology
Present portable type electronic product is more and more tending towards miniaturization, intellectuality and Highgrade integration, and Switching Power Supply (DC-DC) wants to realize Highgrade integration, switching frequency must be improved and narrow down to the size that can be integrated on sheet to make the sheet external components such as inductance capacitance, in the document about fully integrated DC-DC converter delivered at present, switching frequency is minimum is 50MHz, and switching frequency has been brought up to hundreds of MHz by some documents.And improve the complicacy that switching frequency must bring circuit design, and due to inductance value very little, so the current ripples on inductance is very large, be easy to enter DCM pattern, produce inverse current, if can not in time commutator tube be turned off, even if only have the delay of several nanosecond that generation also can be caused even more serious close to the negative-phase sequence curent of 100 milliamperes.Traditional zero cross detection circuit is the structure adopting comparer, as shown in Figure 2, by the voltage of VX point compared with 0V voltage, when zero crossing, commutator tube is turned off, but there is propagation delay in comparer, and propagation delay is very large for high frequency switch power impact, very large inverse current can be caused, as shown in Figure 3, and if the delay of comparer to be reduced, very large power consumption will inevitably be brought, occupy very large area.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of zero cross detection circuit be applied in high frequency switch power, it is characterized in that, comprise biased part, detecting portion and output;
Wherein said offset part is divided into each branch road of zero cross detection circuit to provide bias current;
Described detecting portion, when switching tube turns off, detects commutator tube drain voltage VX, and when VX rises to 0V from negative value, output low level, turns off commutator tube, prevent the generation of inverse current;
Output is for adjusting the driving force of output waveform and increase testing circuit.
Preferably, described offset part is divided and is comprised the first PMOS, the first NMOS tube and the second NMOS tube;
Described first PMOS source electrode connects power supply, described first NMOS tube grid, the first NMOS tube drain electrode, the second NMOS tube grid connect IBIAS port, described first NMOS tube source electrode, the second NMOS tube source electrode ground connection respectively, described first PMOS drain electrode, the first PMOS grid, the second NMOS tube drain electrode are connected.
Preferably, described detecting portion comprises the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube;
Described second PMOS drain electrode, second PMOS source electrode, 3rd PMOS source electrode, 4th PMOS source electrode, 5th PMOS source electrode connects power supply respectively, described second PMOS grid, 3rd PMOS grid, 4th PMOS grid, 5th PMOS grid is connected with the first PMOS grid respectively, 5th PMOS drain electrode drains with the 6th NMOS tube and is connected, described 3rd PMOS drain electrode, 3rd NMOS tube drain electrode, 3rd NMOS tube grid, 4th NMOS tube grid is connected, described 4th PMOS drain electrode, 4th NMOS tube drain electrode, 6th NMOS tube grid is connected,
Described 3rd NMOS tube source electrode, the 6th NMOS tube source electrode connect power supply respectively, and the 4th NMOS tube source electrode drains with the 5th NMOS tube and is connected, and the 5th NMOS tube grid meets port EN, and the 5th NMOS tube source electrode meets port VX.
Preferably, described output comprises the first phase inverter and second phase inverter of series connection, and described 5th PMOS drain electrode, the 6th NMOS tube drain electrode are connected with the input of described first phase inverter respectively.
Preferably, the equal ground connection of substrate of described each PMOS and NMOS tube.
Preferably, the channel length of described first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS is 2.5 ~ 2.8 times of minimum channel length under PMOS standard technology, the channel length of described first NMOS tube, the second NMOS tube is 5.5 ~ 5.6 times of minimum channel length under NMOS standard technology, and the channel length of described 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube is minimum channel length under NMOS standard technology.
The present invention has following beneficial effect:
1, circuit form is simple, the quiescent current needed is very low, so power consumption is very low, and the zero cross detection circuit of traditional comparer form will reach identical effect, the size that must improve bias current and metal-oxide-semiconductor, to improve the response speed of comparer, so not only increased power consumption but also increased cost;
2, the trip point of zero passage detection can adjust according to the size of bias current, makes usable range of the present invention very wide, both can be used for the zero passage detection in low-frequency switch power supply, and also may be used for high frequency switch power; During for high frequency switch power, as required trip point can be shifted to an earlier date, the impact that bucking circuit propagation delay is brought, prevent the generation of inverse current.
Certainly, implement arbitrary product of the present invention might not need to reach above-described all advantages simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, be briefly described describing the required accompanying drawing used to embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The zero cross detection circuit schematic diagram that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is the structural drawing of traditional zero cross detection circuit;
Fig. 3 is propagation delay and the inverse current of traditional zero cross detection circuit.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, a kind of zero cross detection circuit be applied in high frequency switch power, is characterized in that, comprises biased part 1, detecting portion 2 and output 3;
Each branch road that wherein said biased part 1 is zero cross detection circuit provides bias current;
Described detecting portion 2, when switching tube turns off, detects commutator tube drain voltage VX, and when VX rises to 0V from negative value, output low level, turns off commutator tube, prevent the generation of inverse current;
Output 3 is for adjusting the driving force of output waveform and increase testing circuit.
In the present embodiment, biased part 1 comprises the first PMOS PM1, the first NMOS tube NM1 and the second NMOS tube NM2;
Wherein the first PMOS PM1 source electrode connects power supply, first NMOS tube NM1 grid, the first NMOS tube NM1 drain electrode, the second NMOS tube NM2 grid connect IBIAS port, first NMOS tube NM1 source electrode, the second NMOS tube NM2 source electrode ground connection respectively, the first PMOS PM1 drain electrode, the first PMOS PM1 grid, the second NMOS tube NM2 drain electrode are connected.
Detecting portion 2 comprises the second PMOS PM2, the 3rd PMOS PM3, the 4th PMOS PM4, the 5th PMOS PM5, the 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6;
Described second PMOS PM2 drain electrode, second PMOS PM2 source electrode, 3rd PMOS PM3 source electrode, 4th PMOS PM4 source electrode, 5th PMOS PM5 source electrode connects power supply respectively, second PMOS PM2 grid, 3rd PMOS PM3 grid, 4th PMOS PM4 grid, 5th PMOS PM5 grid is connected with the first PMOS PM1 grid respectively, 5th PMOS PM5 drain electrode drains with the 6th NMOS tube NM6 and is connected, 3rd PMOS PM3 drain electrode, 3rd NMOS tube MN3 drain electrode, 3rd NMOS tube NM3 grid, 4th NMOS tube NM4 grid is connected, 4th PMOS PM4 drain electrode, 4th NMOS tube NM4 drain electrode, 6th NMOS tube NM6 grid is connected,
3rd NMOS tube NM3 source electrode, the 6th NMOS tube NM6 source electrode connect power supply respectively, and the 4th NMOS tube NM4 source electrode drains with the 5th NMOS tube NM5 and is connected, and the 5th NMOS tube NM5 grid meets port EN, and the 5th NMOS tube NM5 source electrode meets port VX.
Output 3 comprises the first phase inverter and second phase inverter of series connection, and the 5th PMOS PM5 drain electrode, the 6th NMOS tube NM6 drain electrode are connected with the input of described first phase inverter respectively.
The equal ground connection of substrate of described each PMOS and NMOS tube.The channel length of the first PMOS PM1, the second PMOS PM2, the 3rd PMOS PM3, the 4th PMOS PM4, the 5th PMOS PM5 is 2.5 ~ 2.8 times of minimum channel length under PMOS standard technology, the channel length of the first NMOS tube NM1, the second NMOS tube NM2 is 5.5 ~ 5.6 times of minimum channel length under NMOS standard technology, and the channel length of the 3rd NMOS tube NM3, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6 is minimum channel length under NMOS standard technology.
The present embodiment middle port IBIAS provides bias current for zero cross detection circuit, port EN is circuit enable signal, and VX drains with commutator tube and is connected, to this point voltage real-time sampling, N_SHUT is circuit output signal, is used for turning off commutator tube when inductive current zero crossing;
What the embodiment of the present invention provided the zero cross detection circuit course of work be applied in high frequency switch power is:
Port EN is connected with the drive singal of switching tube, and when switching tube conducting, inductive current rises, and now EN is low level, and zero cross detection circuit does not work; And when switching tube turns off, inductive current starts to decline, now EN is high level, and zero cross detection circuit is started working, the zero crossing of monitoring inductive current; VX is directly connected with the drain terminal of commutator tube, when inductive current declines from peak value, until drop in the process of 0A, VX is from negative magnitude of voltage to positive voltage gradual change, and when inductive current is close to zero point, the voltage of VX also close to zero point, that is: the zero crossing of inductive current is synchronous with the zero crossing of VX voltage, so the magnitude of voltage of VX can be used for detecting the zero crossing of inductive current;
When EN is high level, 5th NMOS tube NM5 conducting, if inductive current is larger, namely the magnitude of voltage of VX is more negative, now, the drain electrode of the 4th NMOS tube NM4 and the grid voltage of the 6th NMOS tube NM6 are drawn very low, and now the 6th NMOS tube NM6 turns off, so exporting N_SHUT is high level, commutator tube works on; If inductive current drops to close to zero point, namely the magnitude of voltage of VX rises to close to 0V, and the now drain electrode of the 4th NMOS tube NM4 can increase, when be elevated to make the 6th NMOS tube NM6 conducting time, exporting N_SHUT saltus step is low level, is turned off by commutator tube.And it is relevant to the electric current flow through during the conversion of the drain voltage of the 4th NMOS tube NM4, therefore trip point can be changed by adjusting the electric current flowing through the 4th NMOS tube NM4, in the present invention, trip point is adjusted at about-10mV, with the propagation delay of bucking circuit, prevent the generation of inverse current.
Circuit form of the present invention is simple, the quiescent current needed is very low, so power consumption is very low, and the zero cross detection circuit of traditional comparer form will reach identical effect, the size that must improve bias current and metal-oxide-semiconductor, to improve the response speed of comparer, so not only increased power consumption but also increased cost;
The trip point of zero passage detection can adjust according to the size of bias current, makes usable range of the present invention very wide, both can be used for the zero passage detection in low-frequency switch power supply, and also may be used for high frequency switch power; During for high frequency switch power, as required trip point can be shifted to an earlier date, the impact that bucking circuit propagation delay is brought, prevent the generation of inverse current.
The disclosed preferred embodiment of the present invention just sets forth the present invention for helping above.Preferred embodiment does not have all details of detailed descriptionthe, does not limit the embodiment that this invention is only described yet.Obviously, according to the content of this instructions, can make many modifications and variations.This instructions is chosen and is specifically described these embodiments, is to explain principle of the present invention and practical application better, thus makes art technician understand well and to utilize the present invention.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (6)
1. be applied to the zero cross detection circuit in high frequency switch power, it is characterized in that, comprise biased part, detecting portion and output;
Wherein said offset part is divided into each branch road of zero cross detection circuit to provide bias current;
Described detecting portion, when switching tube turns off, detects commutator tube drain voltage VX, and when VX rises to 0V from negative value, output low level, turns off commutator tube, prevent the generation of inverse current;
Output is for adjusting the driving force of output waveform and increase testing circuit.
2. be applied to the zero cross detection circuit in high frequency switch power as claimed in claim 1, it is characterized in that, described offset part is divided and is comprised the first PMOS, the first NMOS tube and the second NMOS tube;
Described first PMOS source electrode connects power supply, described first NMOS tube grid, the first NMOS tube drain electrode, the second NMOS tube grid connect IBIAS port, described first NMOS tube source electrode, the second NMOS tube source electrode ground connection respectively, described first PMOS drain electrode, the first PMOS grid, the second NMOS tube drain electrode are connected.
3. be applied to the zero cross detection circuit in high frequency switch power as claimed in claim 2, it is characterized in that, described detecting portion comprises the second PMOS, the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube;
Described second PMOS drain electrode, second PMOS source electrode, 3rd PMOS source electrode, 4th PMOS source electrode, 5th PMOS source electrode connects power supply respectively, described second PMOS grid, 3rd PMOS grid, 4th PMOS grid, 5th PMOS grid is connected with the first PMOS grid respectively, 5th PMOS drain electrode drains with the 6th NMOS tube and is connected, described 3rd PMOS drain electrode, 3rd NMOS tube drain electrode, 3rd NMOS tube grid, 4th NMOS tube grid is connected, described 4th PMOS drain electrode, 4th NMOS tube drain electrode, 6th NMOS tube grid is connected, described 3rd NMOS tube source electrode, 6th NMOS tube source electrode connects power supply respectively, 4th NMOS tube source electrode drains with the 5th NMOS tube and is connected, 5th NMOS tube grid meets port EN, 5th NMOS tube source electrode meets port VX.
4. be applied to the zero cross detection circuit in high frequency switch power as claimed in claim 3, it is characterized in that, described output comprises the first phase inverter and second phase inverter of series connection, and described 5th PMOS drain electrode, the 6th NMOS tube drain electrode are connected with the input of described first phase inverter respectively.
5. be applied to the zero cross detection circuit in high frequency switch power as claimed in claim 3, it is characterized in that, the equal ground connection of substrate of described each PMOS and NMOS tube.
6. be applied to the zero cross detection circuit in high frequency switch power as claimed in claim 3, it is characterized in that, described first PMOS, second PMOS, 3rd PMOS, 4th PMOS, the channel length of the 5th PMOS is 2.5 ~ 2.8 times of minimum channel length under PMOS standard technology, described first NMOS tube, the channel length of the second NMOS tube is 5.5 ~ 5.6 times of minimum channel length under NMOS standard technology, described 3rd NMOS tube, 4th NMOS tube, 5th NMOS tube, the channel length of the 6th NMOS tube is minimum channel length under NMOS standard technology.
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| CN201510405927.8A CN104991113B (en) | 2015-07-09 | 2015-07-09 | Applied to the zero cross detection circuit in high frequency switch power |
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| CN201510405927.8A CN104991113B (en) | 2015-07-09 | 2015-07-09 | Applied to the zero cross detection circuit in high frequency switch power |
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| CN107561434A (en) * | 2017-07-10 | 2018-01-09 | 北京时代民芯科技有限公司 | A kind of current detection circuit for PWM/PFM double mode DC DC Switching Power Supplies |
| CN108572274A (en) * | 2017-03-10 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of zero cross detection circuit and DC-DC converter |
| CN112557740A (en) * | 2020-12-07 | 2021-03-26 | 深圳市朗科智能电气股份有限公司 | Method and device for avoiding zero-crossing signal detection time deviation in zero-crossing detection circuit |
| CN112595886A (en) * | 2020-12-16 | 2021-04-02 | 合肥工业大学 | Low-power-consumption self-adaptive zero-crossing detection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106059553A (en) * | 2016-07-29 | 2016-10-26 | 珠海智融科技有限公司 | Implementation device of Ra resistor in USB Type-CEMCA cable |
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| CN107561434A (en) * | 2017-07-10 | 2018-01-09 | 北京时代民芯科技有限公司 | A kind of current detection circuit for PWM/PFM double mode DC DC Switching Power Supplies |
| CN107561434B (en) * | 2017-07-10 | 2020-01-14 | 北京时代民芯科技有限公司 | Current detection circuit for PWM/PFM dual-mode DC-DC switching power supply |
| CN112557740A (en) * | 2020-12-07 | 2021-03-26 | 深圳市朗科智能电气股份有限公司 | Method and device for avoiding zero-crossing signal detection time deviation in zero-crossing detection circuit |
| CN112557740B (en) * | 2020-12-07 | 2023-11-17 | 深圳市朗科智能电气股份有限公司 | Method and device for avoiding zero-crossing signal detection time deviation in zero-crossing detection circuit |
| CN112595886A (en) * | 2020-12-16 | 2021-04-02 | 合肥工业大学 | Low-power-consumption self-adaptive zero-crossing detection circuit |
| CN112595886B (en) * | 2020-12-16 | 2022-06-07 | 合肥工业大学 | Low-power-consumption self-adaptive zero-crossing detection circuit |
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