CN103904875A

CN103904875A - Digital soft start circuit in switching power source

Info

Publication number: CN103904875A
Application number: CN201410111315.3A
Authority: CN
Inventors: 张章; 宋明鑫; 王星; 韩旭; 王丽; 解光军
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2014-03-24
Filing date: 2014-03-24
Publication date: 2014-07-02

Abstract

The invention discloses a digital soft start circuit in a switching power source. The digital soft start circuit comprises a frequency divider composed of six D triggers. The of each D trigger is connected with the clock signal input end of the next D trigger, the of the sixth D trigger serves as the output end and generates a clock signal VA and the clock signal input end of the first D trigger is connected with a clock signal of a whole loop; the clock signal VA serves as an input signal, a rising delayed clock signal VC is generated through two phase inverters and an RC series loop, the clock signal VC is then shaped and filtered through a Schmitt trigger, and therefore a clock signal VB is obtained; a control clock signal VD is obtained by the clock signal VA and the clock signal VB through a NAND gate, the clock signal VD is connected with a grid electrode of an MOS tube M2 after clock absorption and controls the MOS tube M2 to be connected and disconnected, a source electrode and a drain electrode of the MOS tube M2 are connected with a constant current source I1 and a capacitor C2 respectively, the capacitor C2 is intermittently charged by the constant current source I1, and therefore a soft start voltage is obtained. The complexity of the circuit is reduced and the circuit is conveniently integrated in a chip.

Description

Digital soft start circuit in Switching Power Supply

Technical field

The present invention relates to the power management module in analog integrated circuit design field, be specifically related to the digital soft start circuit in a kind of Switching Power Supply.

Background technology

Along with the continuous growth of portable type electronic product in the fields such as communication, computer and consumer electronics, also in rising trend to the demand of power management IC.And DC-DC Switching Power Supply can realize boosting or step-down and have very high efficiency between direct voltage, is widely used.Switching Power Supply is worked by error signal being converted to duty cycle control signal power ratio control switching tube. just starting the electrifying startup stage, error amplifier is in nonequilibrium condition, make loop in 100% duty ratio work, therefore have very large surge current and flow into load, make output voltage produce larger overshoot, excessive surge current also likely damages power switch pipe and other devices.We have designed a kind of soft starting circuit for this reason, its design philosophy is to eliminate surge current by restriction duty ratio or limit switch electric current, avoid output voltage overshoot. along with electronic system is tending towards complicated, system has had higher requirement to the electrifying timing sequence of supply voltage and the smoothness powering on.The present invention has adopted a kind of digital soft start circuit of novelty.

Summary of the invention

In order to make up the deficiency of prior art, the invention provides in a kind of Switching Power Supply digital soft start circuit.

The present invention adopts following technical scheme to realize:

Digital soft start circuit in Switching Power Supply, is characterized in that: include the frequency divider being formed by six d type flip flops, each d type flip flop connect the clock signal input terminal of next d type flip flop, the 6th d type flip flop

as output clocking VA, the clock signal input terminal of first d type flip flop connects the clock signal of whole loop; The effect that adopts this kind of frequency divider is directly to utilize the clock signal that produced in circuit and by the cycle stretch-out of clock signal, increase the charging interval to electric capacity;

Clocking V _b: clock signal V _aproduce a rising delay clock signal V as input signal through two inverters and a RC series loop _c, clock signal V _cafter a Schmidt trigger shaping filter, obtain the clock signal V that a duty ratio is 50% again _b; Wherein RC series loop includes

resistance R

1,1, two inverter of capacitor C is connected successively with resistance R 1;

Produce control signal V _d: clock signal V _aand V _bthrough a controlled clock signal V of gate-NAND gate _d, clock receives rear clock signal V _dconnect metal-oxide-semiconductor M ₂grid and control metal-oxide-semiconductor M ₂conducting and shutoff, metal-oxide-semiconductor M ₂source electrode be connected respectively constant current source I with drain electrode ₁, capacitor C ₂thereby, constant-current source I ₁to capacitor C ₂carry out intermittent charge and obtain soft start voltage.

Soft-start signal produces circuit: constant current source I ₁with metal-oxide-semiconductor M ₂and capacitor C ₂, by switch MOS pipe M ₂conducting and shutoff, constant-current source I ₁to capacitor C ₂carry out intermittent charging and obtain the soft-start signal of climbing in a slope.

This technology has advantages of as follows compared with prior art:

1, produce control signal V _dcircuit diagram simple, and be the clock signal of utilizing whole DC-DC control loop to produce, particularly having used and can having obtained regular duty ratio after Schmidt trigger is 50% clock signal V _b, reduced the complexity of circuit.

2, by the formula that produces voltage

this traditional mode needs a very large charging capacitor, generally adopts the external method of chip, has increased chip periphery pin and cost, has adopted a kind of digital soft start mode of novelty, by control signal V in the present invention _delectric capacity is charged and obtains soft start voltage intermittently, can reduce the value of electric capacity, is convenient to be integrated in chip internal.

Accompanying drawing explanation

Fig. 1 is the soft starting circuit schematic diagram that the present invention adopts.

Fig. 2 is V _a, V _band V _dthree clock signal sequential charts.

Embodiment

As shown in Figure 1, the digital soft start circuit in a kind of Switching Power Supply, includes the frequency divider being made up of six d type flip flops 1, each d type flip flop 1

connect the clock signal input terminal of next d type flip flop 1, the 6th d type flip flop 1

as output clocking V _a, the clock signal input terminal of first d type flip flop 1 connects the clock signal of whole loop, and the effect that adopts this kind of frequency divider is directly to utilize the clock signal that produced in circuit and by the cycle stretch-out of clock signal, increase the charging interval to electric capacity.

Clock signal V _aproduce a rising time delayed signal V as input signal through two

inverters

2,3 and a RC series loop _c, clock signal V _cafter Schmidt trigger 4 shaping filters, obtain the clock signal V that a duty ratio is 50% again _b; Wherein RC series loop includes resistance R 1, capacitor C 1, two

inverter

2,3 is connected successively with resistance R 1.

Clock signal V _aand V _bthrough a controlled signal V of gate-NAND gate 5 _d, V _dcontrol metal-oxide-semiconductor M ₂conducting and shutoff, thereby to capacitor C ₂carry out intermittent charge and obtain soft start voltage.

Constant current source I ₁with metal-oxide-semiconductor M ₂and capacitor C ₂, by switch MOS pipe M ₂conducting and shutoff, constant-current source I ₁to capacitor C ₂carry out intermittent charging and obtain the soft-start signal of climbing in a slope.Operation principle of the present invention is exactly clock signal V _aand V _bthrough the controlled signal V of NAND gate _das shown in Figure 2, then according to formula

work as M ₂current source I when conducting ₁to capacitor C ₂charge, capacitor C ₂on voltage raise, work as M ₂capacitor C when shutoff ₂on voltage constant, so to C ₂carry out intermittent charging and just can obtain the soft-start signal of climbing in a slope.

Claims

1. the digital soft start circuit in Switching Power Supply, is characterized in that: include the frequency divider being formed by six d type flip flops, each d type flip flop

connect the clock signal input terminal of next d type flip flop, the 6th d type flip flop

as output clocking V _a, the clock signal input terminal of first d type flip flop connects the clock signal of whole loop; Clock signal V _aproduce a rising delay clock signal V as input signal through two inverters and a RC series loop _c, clock signal V _cafter a Schmidt trigger shaping filter, obtain the clock signal V that a duty ratio is 50% again _b; Wherein RC series loop includes resistance R 1,1, two inverter of capacitor C is connected successively with resistance R 1; Clock signal V _aand V _bthrough a controlled clock signal V of NAND gate _d, clock receives rear clock signal V _dconnect metal-oxide-semiconductor M ₂grid and control metal-oxide-semiconductor M ₂conducting and shutoff, metal-oxide-semiconductor M ₂source electrode be connected respectively constant current source I with drain electrode ₁, capacitor C ₂thereby, constant-current source I ₁to capacitor C ₂carry out intermittent charge and obtain soft start voltage.