CN104901534A - Slope compensating circuit and DC-DC conversion device - Google Patents
Slope compensating circuit and DC-DC conversion device Download PDFInfo
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- CN104901534A CN104901534A CN201510255200.6A CN201510255200A CN104901534A CN 104901534 A CN104901534 A CN 104901534A CN 201510255200 A CN201510255200 A CN 201510255200A CN 104901534 A CN104901534 A CN 104901534A
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Abstract
The invention discloses a slope compensating circuit and a DC-DC conversion device. The slope compensating circuit comprises a copy unit, a slope generating unit and a control unit. The copy unit copies and transmits the input fixed current to the slope generating unit. When every clock period begins, the slope generating unit generates corresponding slope voltage according to the fixed current and overlaps the slope voltage on an input current sampling signal so as to obtain a slope signal. The control unit controls the slope generating unit to be reset before every clock period begins. The circuit is simple and power consumption and area of the DC-DC conversion device are greatly reduced.
Description
Technical field
The present invention relates to switch power technology field, particularly a kind of slope compensation circuit and DC-DC conversion equipment.
Background technology
In the DC-DC converter of peak-current mode, when the duty ratio D of modulating pulse is greater than 50%, need to carry out slope compensation to avoid producing subharmonic oscillation to the inductive current sampled.The condition of slope compensation demand fulfillment is:
.Wherein,
for the descending slope of inductive current,
for the rate of rise of inductive current,
for compensating the slope on slope,
increase along with the increase of duty ratio.In order to ensure that when all duty ratios power-supply system can steady operation, standingly to put
.
The essence of slope compensation is exactly on inductive current, superpose a slope of rising, and this slope can be produced by oscillator.What the slope that oscillator produces and inductive current exported is all voltage, and the summation based on voltage is very complicated, and electric current summation is very simple.Therefore, prior art is, by V-I change-over circuit, ramp signal and inductor current signal are converted to current signal, then to two current signal summations.As shown in Figure 1, namely ramp signal Vramp and inductor current signal Vsense can be exchanged into voltage signal Vf through resistance Rf after being converted to corresponding current signal respectively through a V-I change-over circuit.
See also Fig. 2, arrange R1=R2=Rf in V-I change-over circuit, then Vf=Vsense+Vramp in circuit, can reach the object of slope compensation.But the complex structure of V-I change-over circuit, adopting this circuit structure to realize slope compensation needs to arrange two V-I change-over circuits respectively, and a conversion inductor current signal Vsense, a relay ramp signal Vramp, can increase power consumption and chip area like this.
In view of this, the invention provides a kind of slope compensation circuit and DC-DC conversion equipment.
Summary of the invention
In view of above-mentioned the deficiencies in the prior art part, the object of the present invention is to provide a kind of slope compensation circuit and DC-DC conversion equipment, to solve existing slope compensation circuit complex structure, the problem of power consumption and chip area can be increased.
In order to achieve the above object, this invention takes following technical scheme:
A kind of slope compensation circuit, it comprises: copied cells, slope generation unit and control unit;
The fixed current of input copies and is transferred to slope generation unit by described copied cells; Slope generation unit, when each clock cycle starts, produces corresponding ramp voltage according to described fixed current, obtains ramp signal on the current sampling signal described ramp voltage being superimposed upon input; Control unit controlled slope generation unit and resets before each clock cycle starts.
In described slope compensation circuit, described copied cells comprises the first current mirror and the second current mirror, be transferred to the second current mirror after fixed current copies by described first current mirror again to copy, the second current mirror exports the electric current after copying to slope generation unit.
In described slope compensation circuit, described first current mirror comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, described second current mirror comprises the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor connects the drain electrode of the first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor and the grid of the 3rd metal-oxide-semiconductor, the source electrode of the first metal-oxide-semiconductor and the source ground of the 3rd metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor connects the drain electrode of the second metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 4th metal-oxide-semiconductor connects the drain electrode of the 3rd metal-oxide-semiconductor, the drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of the 5th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 7th metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor connects the drain electrode of the 6th metal-oxide-semiconductor, the grid of the 6th metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor is all connected power end with the source electrode of the 8th metal-oxide-semiconductor, the drain electrode of the 8th metal-oxide-semiconductor connects the source electrode of the 7th metal-oxide-semiconductor, the drain electrode of the 7th metal-oxide-semiconductor connects slope generation unit and control unit, the drain electrode of the second metal-oxide-semiconductor is the first input end of slope compensation circuit.
In described slope compensation circuit, described slope generation unit comprises the first electric capacity, one end of described first electric capacity connects the 7th metal-oxide-semiconductor drain electrode and control unit, the other end connection control unit of the first electric capacity; One end of described first electric capacity is the output of slope compensation circuit, and the other end of the first electric capacity is the second input of slope compensation circuit.
In described slope compensation circuit, the capacitance of described first electric capacity meets
,
for the descending slope of current sampling signal,
for the slope of ramp voltage.
In described slope compensation circuit, described control unit comprises the 9th metal-oxide-semiconductor, and the drain electrode of described 9th metal-oxide-semiconductor connects one end of the first electric capacity and the drain electrode of the 7th metal-oxide-semiconductor, and the source electrode of the 9th metal-oxide-semiconductor connects the other end of the first electric capacity; The grid of the 9th metal-oxide-semiconductor is the 3rd input of slope compensation circuit.
A kind of DC-DC conversion equipment, comprise pulse-generating circuit and PWM circuit, it also comprises described slope compensation circuit;
Described pulse-generating circuit generates corresponding control signal and clock signal according to the oscillator signal of input and exports, described clock signal drive described PWM circuit to carry out Voltage Cortrol and feedback current sampled signal to slope compensation circuit; Described slope compensation circuit produces corresponding ramp voltage according to the fixed current of control signal and input and is superimposed on current sampling signal, obtains ramp signal and export to PWM circuit and carry out slope compensation.
In described DC-DC conversion equipment, described pulse-generating circuit comprises control electronic circuit and clock electronic circuit, duty ratio of carrying out the oscillator signal of described control electronic circuit to input reduces process and generates control signal and transmit, and clock electronic circuit carries out time delay to described control signal, duty ratio reduces process generated clock signal and transmits.
In described DC-DC conversion equipment, described control electronic circuit comprises the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor, the first inverter, the second inverter and first and door; Described clock electronic circuit comprises the first resistance, the 3rd inverter, the 4th inverter, the 3rd electric capacity and second and door;
Described tenth metal-oxide-semiconductor is all connected power end with the source electrode of the 11 metal-oxide-semiconductor, the grid of the tenth metal-oxide-semiconductor connects the drain electrode of the tenth metal-oxide-semiconductor and the grid of the 11 metal-oxide-semiconductor, the drain electrode of the 11 metal-oxide-semiconductor connects the drain electrode of the 12 metal-oxide-semiconductor, the input of the second inverter and one end of the second electric capacity, the grid of the 12 metal-oxide-semiconductor connects the output of the first inverter, the source electrode of the 12 metal-oxide-semiconductor connects the other end and the ground of the second electric capacity, first is connected the input of the first inverter with the first input end of door, first is connected the output of the second inverter with the second input of door, first is connected the 3rd input of slope compensation circuit and the input of the 3rd inverter with the output of door, the output of the 3rd inverter connects one end and second and the first input end of door of the first resistance, the other end of the first resistance is connected the input of the 4th inverter, is also connected source electrode and the ground of the 12 metal-oxide-semiconductor by the 3rd electric capacity, and the output connection second of the 4th inverter and the second input of door, second is connected PWM circuit with the output of door.
In described DC-DC conversion equipment, described PWM circuit comprises error amplifier, comparator, rest-set flip-flop, drive circuit, power tube, inductance, diode, the 4th electric capacity, the second resistance, the 3rd resistance, the 4th resistance and load;
The positive input input reference voltage of described error amplifier, the reverse input end of error amplifier connects one end of the second resistance and one end of the 3rd resistance, the output of error amplifier connects the inverting input of comparator, the normal phase input end of comparator connects the 3rd input of slope compensation circuit, the output of comparator connects the R end of rest-set flip-flop, the S end of rest-set flip-flop connects second of pulse-generating circuit and the output of door, the Q end of rest-set flip-flop connects the input of drive circuit, and the output of described drive circuit connects the grid of power tube; The drain electrode of power tube connect diode positive pole, also connect voltage input end by inductance; The source electrode of power tube connect slope compensation circuit the second input, also by the 4th grounding through resistance, the negative pole of described diode connect the other end of the second resistance and load one end, also by the 4th capacity earth, the other end ground connection of described 3rd resistance, the other end ground connection of load.
Compared to prior art, slope compensation circuit provided by the invention and DC-DC conversion equipment, slope compensation circuit comprises copied cells, slope generation unit and control unit; The fixed current of input copies and is transferred to slope generation unit by described copied cells; Slope generation unit, when each clock cycle starts, produces corresponding ramp voltage according to described fixed current, obtains ramp signal on the current sampling signal described ramp voltage being superimposed upon input; Control unit starts described slope generation unit and before each clock cycle starts, controls slope generation unit reset according to the control signal of input; Its circuit structure is simple, substantially reduces power consumption and the area of DC-DC conversion equipment.
Accompanying drawing explanation
Fig. 1 is existing slope compensation circuit figure;
Fig. 2 is the circuit diagram of the V-I change-over circuit in Fig. 1;
The structured flowchart of the slope compensation circuit that Fig. 3 provides for the embodiment of the present invention;
The circuit diagram of the slope compensation circuit that Fig. 4 provides for the embodiment of the present invention;
The structured flowchart of the DC-DC conversion equipment that Fig. 5 provides for the embodiment of the present invention;
The circuit diagram of pulse-generating circuit in the DC-DC conversion equipment that Fig. 6 provides for the embodiment of the present invention;
The circuit diagram of the DC-DC conversion equipment Application Example that Fig. 7 provides for the embodiment of the present invention.
Embodiment
The invention provides a kind of slope compensation circuit and DC-DC conversion equipment, described slope compensation circuit is applicable to boost booster circuit, is also applicable to buck reduction voltage circuit, is also applicable to LED drive circuit; It adopts fixed current to form ramp voltage to the first capacitor charging, is superimposed upon by ramp voltage on sample rate current, to reach the object of slope compensation; Its circuit structure is simple, can reduce power consumption and reduce chip area.For making object of the present invention, technical scheme and effect clearly, clearly, developing simultaneously referring to accompanying drawing, the present invention is described in more detail for embodiment.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Refer to Fig. 3, the slope compensation circuit 10 that the embodiment of the present invention provides comprises copied cells 110, slope generation unit 120 and control unit 130.Described copied cells 110 connects slope generation unit 120 and control unit 130, described slope generation unit 120 connection control unit 130.The fixed current Icharge of input copies and is transferred to slope generation unit 120 by described copied cells 110.Slope generation unit 120, when each clock cycle starts, produces corresponding ramp voltage according to described fixed current Icharge, obtains ramp signal Ramp on the current sampling signal ISW described ramp voltage being superimposed upon input.Control unit 130 starts described slope generation unit 120 and before each clock cycle starts, controls slope generation unit 120 reset according to the control signal Pulse of input.
In the present embodiment, slope generation unit 120 adopts capacitor charging principle to produce ramp voltage, utilizes fixed current Icharge to the first capacitor charging arranged in slope generation unit 120, makes the voltage linear on the first electric capacity increase, can produce ramp voltage; By resetting to slope generation unit 120, the voltage on the first electric capacity can be made to drop quickly to the magnitude of voltage equaling current sampling signal ISW, the voltage on the first electric capacity can be made when next time charges again linearly to increase.The starting voltage value of the ramp signal Ramp of such acquisition equals the magnitude of voltage of current sampling signal ISW, and the maximum voltage value of ramp signal Ramp equals the peak of ramp voltage.
See also Fig. 4, in the present embodiment, described copied cells 110 comprises the first current mirror 111 and the second current mirror 112, be transferred to the second current mirror 112 after fixed current copies by described first current mirror 111 again to copy, the second current mirror 112 exports the electric current after copying to slope generation unit.
Described first current mirror 111 comprises the first metal-oxide-semiconductor N1, the second metal-oxide-semiconductor N2, the 3rd metal-oxide-semiconductor N3 and the 4th metal-oxide-semiconductor N4, described second current mirror 112 comprises the 5th metal-oxide-semiconductor P1, the 6th metal-oxide-semiconductor P2, the 7th metal-oxide-semiconductor P3 and the 8th metal-oxide-semiconductor P4, the grid of described first metal-oxide-semiconductor N1 connects the drain electrode of the first metal-oxide-semiconductor N1, the source electrode of the second metal-oxide-semiconductor N2 and the grid of the 3rd metal-oxide-semiconductor N3, the source electrode of the first metal-oxide-semiconductor N1 and the source ground of the 3rd metal-oxide-semiconductor N3, the grid of the second metal-oxide-semiconductor N2 connects the drain electrode of the second metal-oxide-semiconductor N2 and the grid of the 4th metal-oxide-semiconductor N4, the source electrode of the 4th metal-oxide-semiconductor N4 connects the drain electrode of the 3rd metal-oxide-semiconductor N3, the drain electrode of the 4th metal-oxide-semiconductor N4 connects the drain electrode of the 5th metal-oxide-semiconductor P1, the grid of the 5th metal-oxide-semiconductor P1 and the grid of the 7th metal-oxide-semiconductor P3, the source electrode of the 5th metal-oxide-semiconductor P1 connects the drain electrode of the 6th metal-oxide-semiconductor P2, the grid of the 6th metal-oxide-semiconductor P2 and the grid of the 4th metal-oxide-semiconductor N4, the source electrode of the 6th metal-oxide-semiconductor P2 is all connected power end VDD with the source electrode of the 8th metal-oxide-semiconductor P4, the drain electrode of the 8th metal-oxide-semiconductor P4 connects the source electrode of the 7th metal-oxide-semiconductor P3, the drain electrode of the 7th metal-oxide-semiconductor P3 connects slope generation unit 120 and control unit 130.Wherein, the drain electrode of the second metal-oxide-semiconductor N2 is the first input end in1 of slope compensation circuit 10, input fixed current Icharge.
Described first metal-oxide-semiconductor N1, the second metal-oxide-semiconductor N2, the 3rd metal-oxide-semiconductor N3 and the 4th metal-oxide-semiconductor N4 are NMOS tube, form the first current mirror 111.Described fixed current Icharge inputs from the drain electrode of the second metal-oxide-semiconductor N2, flows into the drain electrode of the 5th metal-oxide-semiconductor P1 after this first current mirror 111 copies.5th metal-oxide-semiconductor P1, the 6th metal-oxide-semiconductor P2, the 7th metal-oxide-semiconductor P3 and the 8th metal-oxide-semiconductor P4 are PMOS, form the second current mirror 112, flow out after again being copied by the fixed current Icharge of inflow from the drain electrode of the 7th metal-oxide-semiconductor P3.The size (i.e. breadth length ratio) of 4 NMOS tube arranged in the present embodiment is identical, 4 PMOS measure-alike.The electric current that the drain electrode of the 7th metal-oxide-semiconductor P3 can be made to flow out is equal with fixed current Icharge, is equivalent to fixed current Icharge to input in slope generation unit 120 charge.
Described slope generation unit 120 comprises the first electric capacity C1, one end of described first electric capacity C1 connects the drain electrode of the 7th metal-oxide-semiconductor P3 and the other end connection control unit 130 of control unit 130, first electric capacity C1.Wherein, one end of described first electric capacity C1 is the output out of slope compensation circuit 10, exports ramp signal Ramp.The other end of the first electric capacity C1 is the second input in2 of slope compensation circuit 10, input current sampled signal ISW.
Described control unit 130 comprises the 9th metal-oxide-semiconductor N5, the drain electrode of described 9th metal-oxide-semiconductor N5 connects one end of the first electric capacity C1 and the drain electrode of the 7th metal-oxide-semiconductor P3, the source electrode of the 9th metal-oxide-semiconductor N5 connects the other end of the first electric capacity C1, the grid of the 9th metal-oxide-semiconductor N5 is the 3rd input in3 of slope compensation circuit 10, input control signal Pulse.The source electrode of the 9th metal-oxide-semiconductor N5 is also the second input in2 of slope compensation circuit 10, input current sampled signal ISW.9th metal-oxide-semiconductor N5 is NMOS tube.
Please continue to refer to Fig. 3 and Fig. 4, flow out from the drain electrode of the 7th metal-oxide-semiconductor P3 after the second current mirror of the first current mirror that fixed current Icharge forms through 4 NMOS tube and 4 PMOS compositions copies.When control signal Pulse is low level, 9th metal-oxide-semiconductor N5 ends, fixed current Icharge charges to the first electric capacity C1, the constant voltage linear of the first electric capacity C1 that makes of size because of fixed current Icharge rises, define the slope be superimposed upon on current sampling signal ISW, final output ramp signal Ramp.When control signal Pulse is high level, the 9th metal-oxide-semiconductor N5 conducting, the first electric capacity C1 is shorted, and the voltage drop of ramp signal Ramp, to equal with the voltage of current sampling signal ISW, realizes resetting.
In the present embodiment, the rising edge of control signal Pulse is before the rising edge of clock cycle CLK, and therefore, control signal Pulse can reset to ramp signal Ramp before each clock cycle CLK starts.After control signal Pulse becomes low level there is rising edge (or the rising edge of the trailing edge of control signal Pulse and clock cycle CLK occurs simultaneously) in clock cycle CLK again, therefore, fixed current Icharge can produce ramp voltage when each clock cycle starts to the first electric capacity C1 charging.
In order to ensure that when all duty ratios power-supply system can steady operation, reach the effect of slope compensation, the capacitance of described first electric capacity C1 need meet
,
for the descending slope of current sampling signal (i.e. inductive current),
for the slope (namely compensating the slope on slope) of ramp voltage.
Based on above-mentioned slope compensation circuit, the present embodiment also provides a kind of DC-DC conversion equipment, sees also Fig. 5, and described DC-DC conversion equipment comprises above-mentioned slope compensation circuit 10, pulse-generating circuit 20 and PWM circuit 30.Described slope compensation circuit 10 connects pulse-generating circuit 20 and PWM circuit 30, and described pulse-generating circuit 20 connects PWM circuit 30.Described pulse-generating circuit 20 becomes corresponding control signal Pulse and clock signal clk according to the raw OSC of the oscillator signal of input and exports, described clock signal clk drive described PWM circuit 30 to carry out Voltage Cortrol and feedback current sampled signal ISW to slope compensation circuit 10.Described slope compensation circuit 10 produce corresponding ramp voltage according to the fixed current Icharge of control signal Pulse and input and be superimposed to current sampling signal ISW on, acquisition ramp signal Ramp export to PWM circuit 30 and carry out slope compensation.
Described pulse-generating circuit 20 comprises control electronic circuit 201 and clock electronic circuit 202, duty ratio of carrying out the oscillator signal of described control electronic circuit 201 to input reduces process and generates control signal Pulse and be transferred to slope compensation circuit 10 and clock electronic circuit 202, and clock electronic circuit 202 carries out time delay to described control signal Pulse, duty ratio reduces process generated clock signal CLK and is transferred to PWM circuit 30.
See also Fig. 6, wherein, described control electronic circuit 201 comprises the tenth metal-oxide-semiconductor P5, the 11 metal-oxide-semiconductor P6, the 12 metal-oxide-semiconductor N6, the first inverter I1, the second inverter I2 and first and door AND1; Described clock electronic circuit 202 comprises the first resistance R1, the 3rd inverter I3, the 4th inverter I4, the 3rd electric capacity and second and door AND2.Tenth metal-oxide-semiconductor P5, the 11 metal-oxide-semiconductor P6 are PMOS, and the 12 metal-oxide-semiconductor N6 is NMOS tube.
Described tenth metal-oxide-semiconductor P5 is all connected power end VDD with the source electrode of the 11 metal-oxide-semiconductor P6, the grid of the tenth metal-oxide-semiconductor P5 connects the drain electrode of the tenth metal-oxide-semiconductor P5 and the grid of the 11 metal-oxide-semiconductor P6, the drain electrode of the 11 metal-oxide-semiconductor P6 connects the drain electrode of the 12 metal-oxide-semiconductor N6, the input of the second inverter I2 and one end of the second electric capacity C2, the grid of the 12 metal-oxide-semiconductor N6 connects the output of the first inverter I1, the source electrode of the 12 metal-oxide-semiconductor N6 connects the other end and the ground of the second electric capacity C2, first input being connected the first inverter I1 with the first input end of door AND1, first is connected the output of the second inverter I2 with second input of door AND1, first is connected the 3rd input in3 of slope compensation circuit 10 and the input of the 3rd inverter I3 with the output of door AND1, the output of the 3rd inverter I3 connects one end and second and the first input end of door AND2 of the first resistance R1, the other end of the first resistance R1 is connected the input of the 4th inverter I4, is also connected source electrode and the ground of the 12 metal-oxide-semiconductor N6 by the 3rd electric capacity C3, the output of the 4th inverter I4 connects second input of second and door AND2, and second is connected PWM circuit 30 with the output of door AND2.
The control signal Pulse that described pulse-generating circuit 20 produces and clock signal clk are all very narrow high impulses, and each high impulse of control signal Pulse first occurs than the high impulse of clock signal clk.The present embodiment arrange the tenth metal-oxide-semiconductor P5, the 11 metal-oxide-semiconductor P6 measure-alike.Bias current Ibias is after the current mirror that the tenth metal-oxide-semiconductor P5 and the 11 metal-oxide-semiconductor P6 forms copies, and the electric current flowing through the 11 metal-oxide-semiconductor P6 equals bias current Ibias.The oscillator signal OSC of input to be duty ratio be 50% clock, oscillator signal OSC controls the break-make of the 12 metal-oxide-semiconductor N6 after the first inverter I1 is anti-phase.When oscillator signal OSC is high level, the 12 metal-oxide-semiconductor N6 ends, and the 11 metal-oxide-semiconductor P6 starts to charge to the second electric capacity C2.When the voltage of the second electric capacity C2 is greater than the reversal voltage of the second inverter I2, the second inverter I2 output low level.The output of the second inverter I2 and oscillator signal OSC through first with door AND1 phase with after to export its high level lasting time of control signal Pulse(very short).Control signal Pulse gives a pin of second and door AND2 again through the 3rd inverter I3 output signal I3_out, this signal I3_out is contrary with control signal Pulse phase place, and duty ratio is very large.Very narrow based on the pulse duration of clock signal clk required in PWM circuit 30, signal I3_out also need into respective handling could generated clock signal CLK; Be specially: when signal I3_out is high level, the time delay of the RC circuit that need form through the first resistance R1 and the 3rd electric capacity C3.The voltage (as high level) of the 3rd electric capacity C3 exports another pin of second and door AND2 to after the 4th inverter I4 anti-phase (output low level), the output of the 4th inverter I4 through second with door AND2 and signal I3_out phase and, final i.e. clock signal CLK.
See also Fig. 7, the present embodiment is for the DC-DC conversion equipment of boosting, then described PWM circuit 30 adopts boosting mode, and it comprises error amplifier EA, comparator COMP, rest-set flip-flop G, drive circuit, power tube M0, inductance L, diode D, the 4th electric capacity C4, the second resistance R2, the 3rd resistance R3, the 4th resistance R4 and load RL.
The positive input input reference voltage VREF of described error amplifier EA, the reverse input end of error amplifier EA connects one end of the second resistance R2 and one end of the 3rd resistance R3, the output of error amplifier EA connects the inverting input of comparator COMP, the normal phase input end of comparator COMP connects the 3rd input in3 of slope compensation circuit 10, the output of comparator COMP connects the R end of rest-set flip-flop, the S end of rest-set flip-flop connects second of pulse-generating circuit 20 and the output of door AND2, the Q end of rest-set flip-flop connects the input of drive circuit, the output of described drive circuit connects the grid of power tube M0, the drain electrode of power tube M0 connect diode D positive pole, also connect voltage input end Vin by inductance L, the source electrode of power tube M0 connect slope compensation circuit 10 the second input in2, also by the 4th resistance R4 ground connection, the negative pole (i.e. voltage output end Vout) of described diode D connect the other end of the second resistance R2 and load RL one end, also by the 4th electric capacity C4 ground connection, the other end ground connection of described 3rd resistance R3, the other end ground connection of load RL.
It is to be appreciated that described PWM circuit 30, drive circuit are prior art, the present embodiment mainly sets forth the operation principle between slope compensation circuit 10 and pulse-generating circuit 20 that this PWM circuit 30 and the present embodiment provide.
Described error amplifier EA exports the anti-phase input of comparator COMP to after the voltage difference of the feedback voltage FB of the reference voltage V REF of its positive input and its negative input being amplified.Current sampling signal ISW inputs slope compensation circuit and produces corresponding ramp signal Ramp.The normal phase input end of ramp signal Ramp input comparator COMP.Oscillator signal OSC input pulse produces circuit and produces control signal Pulse and clock signal clk.When each clock cycle starts, when namely clock signal clk rising edge arrives, comparator COMP output low level, rest-set flip-flop exports high level, opens power tube M0 through overdrive circuit.Inductance L, power tube M0, the 4th resistance R4 is formed into earth-return, and electric current flows through the 4th R4, the voltage rise of current sampling signal ISW, and current sampling signal ISW produces the ramp signal Ramp of rising after slope compensation circuit.
When the voltage of ramp signal Ramp exceedes the voltage of error amplifier EA output, comparator COMP exports high level, rest-set flip-flop output low level, close power tube M0 through overdrive circuit, now electric current flows to load RL and the second resistance R2 and the 3rd resistance R3(sampling resistor by diode D).Because power tube M0 closes, the voltage drop of current sampling signal ISW, makes ramp signal Ramp decline.
When the voltage that the voltage of ramp signal Ramp exports lower than error amplifier EA, comparator COMP output low level, because the pulse duration of clock signal clk is very narrow, now clock signal clk has been low level, so rest-set flip-flop state keeps, output low level always.Power tube M0 closes always, until the rising edge of clock signal clk arrives just start the next clock cycle, so moves in circles, guarantees the voltage of voltage output end Vout stable output.
In sum, slope compensation circuit provided by the invention and DC-DC conversion equipment, adopt fixed current to form ramp voltage to the first capacitor charging, be superimposed upon by ramp voltage on current sampling signal, reach the object of slope compensation; Its structure is simple, substantially reduces power consumption and the area of DC-DC conversion equipment.
Be understandable that, for those of ordinary skills, can be equal to according to technical scheme of the present invention and inventive concept thereof and replace or change, and all these change or replace the protection range that all should belong to the claim appended by the present invention.
Claims (10)
1. a slope compensation circuit, is characterized in that, comprising: copied cells, slope generation unit and control unit;
The fixed current of input copies and is transferred to slope generation unit by described copied cells; Slope generation unit, when each clock cycle starts, produces corresponding ramp voltage according to described fixed current, obtains ramp signal on the current sampling signal described ramp voltage being superimposed upon input; Control unit controlled slope generation unit and resets before each clock cycle starts.
2. slope compensation circuit according to claim 1, it is characterized in that, described copied cells comprises the first current mirror and the second current mirror, be transferred to the second current mirror after fixed current copies by described first current mirror again to copy, the second current mirror exports the electric current after copying to slope generation unit.
3. slope compensation circuit according to claim 1, is characterized in that, described first current mirror comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor, described second current mirror comprises the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor connects the drain electrode of the first metal-oxide-semiconductor, the source electrode of the second metal-oxide-semiconductor and the grid of the 3rd metal-oxide-semiconductor, the source electrode of the first metal-oxide-semiconductor and the source ground of the 3rd metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor connects the drain electrode of the second metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 4th metal-oxide-semiconductor connects the drain electrode of the 3rd metal-oxide-semiconductor, the drain electrode of the 4th metal-oxide-semiconductor connects the drain electrode of the 5th metal-oxide-semiconductor, the grid of the 5th metal-oxide-semiconductor and the grid of the 7th metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor connects the drain electrode of the 6th metal-oxide-semiconductor, the grid of the 6th metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor is all connected power end with the source electrode of the 8th metal-oxide-semiconductor, the drain electrode of the 8th metal-oxide-semiconductor connects the source electrode of the 7th metal-oxide-semiconductor, the drain electrode of the 7th metal-oxide-semiconductor connects slope generation unit and control unit, the drain electrode of the second metal-oxide-semiconductor is the first input end of slope compensation circuit.
4. slope compensation circuit according to claim 3, is characterized in that, described slope generation unit comprises the first electric capacity, one end of described first electric capacity connects the 7th metal-oxide-semiconductor drain electrode and control unit, the other end connection control unit of the first electric capacity; One end of described first electric capacity is the output of slope compensation circuit, and the other end of the first electric capacity is the second input of slope compensation circuit.
5. slope compensation circuit according to claim 4, is characterized in that, the capacitance of described first electric capacity meets
,
for the descending slope of current sampling signal,
for the slope of ramp voltage.
6. slope compensation circuit according to claim 4, it is characterized in that, described control unit comprises the 9th metal-oxide-semiconductor, and the drain electrode of described 9th metal-oxide-semiconductor connects one end of the first electric capacity and the drain electrode of the 7th metal-oxide-semiconductor, and the source electrode of the 9th metal-oxide-semiconductor connects the other end of the first electric capacity; The grid of the 9th metal-oxide-semiconductor is the 3rd input of slope compensation circuit.
7. a DC-DC conversion equipment, comprises pulse-generating circuit and PWM circuit, it is characterized in that, also comprise slope compensation circuit as described in any one of claim 1-6;
Described pulse-generating circuit generates corresponding control signal and clock signal according to the oscillator signal of input and exports, described clock signal drive described PWM circuit to carry out Voltage Cortrol and feedback current sampled signal to slope compensation circuit; Described slope compensation circuit produces corresponding ramp voltage according to the fixed current of control signal and input and is superimposed on current sampling signal, obtains ramp signal and export to PWM circuit and carry out slope compensation.
8. DC-DC conversion equipment according to claim 7, it is characterized in that, described pulse-generating circuit comprises control electronic circuit and clock electronic circuit, duty ratio of carrying out the oscillator signal of described control electronic circuit to input reduces process and generates control signal and transmit, and clock electronic circuit carries out time delay to described control signal, duty ratio reduces process generated clock signal and transmits.
9. DC-DC conversion equipment according to claim 8, is characterized in that, described control electronic circuit comprises the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor, the 12 metal-oxide-semiconductor, the first inverter, the second inverter and first and door; Described clock electronic circuit comprises the first resistance, the 3rd inverter, the 4th inverter, the 3rd electric capacity and second and door;
Described tenth metal-oxide-semiconductor is all connected power end with the source electrode of the 11 metal-oxide-semiconductor, the grid of the tenth metal-oxide-semiconductor connects the drain electrode of the tenth metal-oxide-semiconductor and the grid of the 11 metal-oxide-semiconductor, the drain electrode of the 11 metal-oxide-semiconductor connects the drain electrode of the 12 metal-oxide-semiconductor, the input of the second inverter and one end of the second electric capacity, the grid of the 12 metal-oxide-semiconductor connects the output of the first inverter, the source electrode of the 12 metal-oxide-semiconductor connects the other end and the ground of the second electric capacity, first is connected the input of the first inverter with the first input end of door, first is connected the output of the second inverter with the second input of door, first is connected the 3rd input of slope compensation circuit and the input of the 3rd inverter with the output of door, the output of the 3rd inverter connects one end and second and the first input end of door of the first resistance, the other end of the first resistance is connected the input of the 4th inverter, is also connected source electrode and the ground of the 12 metal-oxide-semiconductor by the 3rd electric capacity, and the output connection second of the 4th inverter and the second input of door, second is connected PWM circuit with the output of door.
10. DC-DC conversion equipment according to claim 9, it is characterized in that, described PWM circuit comprises error amplifier, comparator, rest-set flip-flop, drive circuit, power tube, inductance, diode, the 4th electric capacity, the second resistance, the 3rd resistance, the 4th resistance and load;
The positive input input reference voltage of described error amplifier, the reverse input end of error amplifier connects one end of the second resistance and one end of the 3rd resistance, the output of error amplifier connects the inverting input of comparator, the normal phase input end of comparator connects the 3rd input of slope compensation circuit, the output of comparator connects the R end of rest-set flip-flop, the S end of rest-set flip-flop connects second of pulse-generating circuit and the output of door, the Q end of rest-set flip-flop connects the input of drive circuit, and the output of described drive circuit connects the grid of power tube; The drain electrode of power tube connect diode positive pole, also connect voltage input end by inductance; The source electrode of power tube connect slope compensation circuit the second input, also by the 4th grounding through resistance, the negative pole of described diode connect the other end of the second resistance and load one end, also by the 4th capacity earth, the other end ground connection of described 3rd resistance, the other end ground connection of load.
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| CN108649800A (en) * | 2018-05-31 | 2018-10-12 | 电子科技大学 | A kind of self-adaptable slop compensation circuit |
| CN109149931A (en) * | 2018-08-29 | 2019-01-04 | 北京机械设备研究所 | Slope-error compensation circuit for peak value comparison method BUCK converter |
| CN109412397A (en) * | 2018-09-12 | 2019-03-01 | 长安大学 | A kind of secondary slope compensation circuit of pulse-width-modulated current mode switch power supply |
| CN114285251A (en) * | 2021-12-24 | 2022-04-05 | 西安理工大学 | Circuit for improving carrying capacity of switching power supply |
| CN114812640A (en) * | 2022-03-14 | 2022-07-29 | 北京市农林科学院智能装备技术研究中心 | Sensing signal copying method and device |
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| CN106603012A (en) * | 2016-12-09 | 2017-04-26 | 重庆西南集成电路设计有限责任公司 | Broadband temperature-compensation voltage-controlled oscillator, temperature compensation method and voltage generation circuit |
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| CN108649800A (en) * | 2018-05-31 | 2018-10-12 | 电子科技大学 | A kind of self-adaptable slop compensation circuit |
| CN109149931A (en) * | 2018-08-29 | 2019-01-04 | 北京机械设备研究所 | Slope-error compensation circuit for peak value comparison method BUCK converter |
| CN109149931B (en) * | 2018-08-29 | 2019-10-11 | 北京机械设备研究所 | Slope-error compensation circuit for peak value comparison method BUCK converter |
| CN109412397A (en) * | 2018-09-12 | 2019-03-01 | 长安大学 | A kind of secondary slope compensation circuit of pulse-width-modulated current mode switch power supply |
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| CN114285251A (en) * | 2021-12-24 | 2022-04-05 | 西安理工大学 | Circuit for improving carrying capacity of switching power supply |
| CN114812640A (en) * | 2022-03-14 | 2022-07-29 | 北京市农林科学院智能装备技术研究中心 | Sensing signal copying method and device |
| CN114812640B (en) * | 2022-03-14 | 2023-09-19 | 北京市农林科学院智能装备技术研究中心 | Sensing signal copying method and device |
| CN115987068A (en) * | 2023-03-17 | 2023-04-18 | 苏州锴威特半导体股份有限公司 | Driving tube control circuit, control method and switching power supply |
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