CN104901534B - A kind of slope compensation circuit and DC DC conversion equipments - Google Patents
A kind of slope compensation circuit and DC DC conversion equipments Download PDFInfo
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- CN104901534B CN104901534B CN201510255200.6A CN201510255200A CN104901534B CN 104901534 B CN104901534 B CN 104901534B CN 201510255200 A CN201510255200 A CN 201510255200A CN 104901534 B CN104901534 B CN 104901534B
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Abstract
The invention discloses a kind of slope compensation circuit and DC DC conversion equipments, slope compensation circuit includes copied cells, slope generation unit and control unit；The fixed current of input is replicated and is transferred to slope generation unit by the copied cells；Slope generation unit the ramp voltage according to corresponding to producing the fixed current, the ramp voltage is superimposed upon on the current sampling signal of input and obtains ramp signal when each clock cycle starts；Control unit controls slope generation unit to be resetted before each clock cycle starts；Its circuit structure is simple, substantially reduces the power consumption and area of DC DC conversion equipments.
Description
Technical field
The present invention relates to switch power technology field, more particularly to a kind of slope compensation circuit and DC-DC conversion equipments.
Background technology
In the DC-DC converter of peak-current mode, when the dutycycle D for modulating pulse is more than 50%, it is necessary to sampling
To inductive current carry out slope compensation with avoid produce subharmonic oscillation.Slope compensation needs the condition that meets to be：.Wherein,For the descending slope of inductive current,For the rate of rise of inductive current,It is oblique to compensate
The slope on slope,Increase with the increase of dutycycle.In order to ensure that power-supply system can be steady in the case of all dutycycles
Fixed work, it is standing to put。
The essence of slope compensation is exactly that the slope of a rising is superimposed on inductive current, and the slope can pass through oscillator
Produce.What slope caused by oscillator and inductive current exported is all voltage, and the summation based on voltage is extremely complex, electric current summation
It is very simple.Therefore, prior art is that ramp signal and inductor current signal are converted into electric current by V-I change-over circuits to believe
Number, then two current signals are summed.As shown in figure 1, ramp signal Vramp and inductor current signal Vsense pass through one respectively
After individual V-I change-over circuits are converted to corresponding current signal, voltage signal Vf is can be exchanged into by resistance Rf.
Also referring to Fig. 2, R1=R2=Rf is set in V-I change-over circuits, then Vf=Vsense in circuit+
Vramp, you can reach the purpose of slope compensation.But V-I change-over circuits is complicated, slope is realized using the circuit structure
Compensation needs to set two V-I change-over circuits respectively, a conversion inductor current signal Vsense, a relay ramp signal
Vramp, it can so increase power consumption and chip area.
In view of this, the present invention provides a kind of slope compensation circuit and DC-DC conversion equipments.
The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of slope compensation circuit and DC-
DC conversion equipments, to solve the problems, such as that existing slope compensation circuit is complicated, can increase power consumption and chip area.
In order to achieve the above object, this invention takes following technical scheme：
A kind of slope compensation circuit, it includes：Copied cells, slope generation unit and control unit；
The fixed current of input is replicated and is transferred to slope generation unit by the copied cells；Slope generation unit is every
When the individual clock cycle starts, the ramp voltage according to corresponding to producing the fixed current, the ramp voltage is superimposed upon input
Current sampling signal on obtain ramp signal；Control unit controls slope generation unit before each clock cycle starts
Resetted.
In described slope compensation circuit, the copied cells includes the first current mirror and the second current mirror, and described first
Current mirror is transferred to the second current mirror and replicated again after fixed current is replicated, the electric current after the output duplication of the second current mirror
Give slope generation unit.
In described slope compensation circuit, first current mirror includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor
With the 4th metal-oxide-semiconductor；Second current mirror includes the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor；Described
The grid of one metal-oxide-semiconductor connects drain electrode, the source electrode of the second metal-oxide-semiconductor and the grid of the 3rd metal-oxide-semiconductor of the first metal-oxide-semiconductor, the first metal-oxide-semiconductor
The source ground of source electrode and the 3rd metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor connect drain electrode and the grid of the 4th metal-oxide-semiconductor of the second metal-oxide-semiconductor
Pole, the source electrode of the 4th metal-oxide-semiconductor connect the drain electrode of the 3rd metal-oxide-semiconductor, the drain electrode of drain electrode the 5th metal-oxide-semiconductor of connection of the 4th metal-oxide-semiconductor, the 5th
The grid of the grid of metal-oxide-semiconductor and the 7th metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor connect the drain electrode of the 6th metal-oxide-semiconductor, the grid of the 6th metal-oxide-semiconductor
Pole and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the source electrode of the 8th metal-oxide-semiconductor are all connected with power end, the 8th metal-oxide-semiconductor
The source electrode of drain electrode the 7th metal-oxide-semiconductor of connection, the drain electrode connection slope generation unit and control unit of the 7th metal-oxide-semiconductor；Second metal-oxide-semiconductor
Drain as the first input end of slope compensation circuit.
In described slope compensation circuit, the slope generation unit includes the first electric capacity, one end of first electric capacity
Connect drain electrode and the control unit of the 7th metal-oxide-semiconductor, the other end connection control unit of the first electric capacity；One end of first electric capacity
For the output end of slope compensation circuit, the other end of the first electric capacity is the second input of slope compensation circuit.
In described slope compensation circuit, the capacitance of first electric capacity meets,For current sample
The descending slope of signal,For the slope of ramp voltage.
In described slope compensation circuit, described control unit includes the 9th metal-oxide-semiconductor, and the drain electrode of the 9th metal-oxide-semiconductor connects
One end of the first electric capacity and the drain electrode of the 7th metal-oxide-semiconductor are connect, the source electrode of the 9th metal-oxide-semiconductor connects the other end of the first electric capacity；9th MOS
The grid of pipe is the 3rd input of slope compensation circuit.
A kind of DC-DC conversion equipments, including pulse-generating circuit and PWM circuit, it also includes described slope and mended
Repay circuit；
The pulse-generating circuit control signal and clock signal and exports according to corresponding to generating the oscillator signal of input,
The clock signal drives the PWM circuit to carry out, and voltage adjusts and feedback current sampled signal is to slope compensation circuit；
The slope compensation circuit ramp voltage and is superimposed to electric current and adopted according to corresponding to producing control signal and the fixed current of input
On sample signal, obtain ramp signal and export and give PWM circuit progress slope compensation.
In described DC-DC conversion equipments, the pulse-generating circuit includes control sub-circuit and clock sub-circuit, described
Control sub-circuit carries out dutycycle to the oscillator signal of input and reduces processing generation control signal and transmit, and clock sub-circuit is to institute
Control signal is stated to enter line delay, dutycycle diminution processing generation clock signal and transmit.
In described DC-DC conversion equipments, the control sub-circuit includes the tenth metal-oxide-semiconductor, the 11st metal-oxide-semiconductor, the 12nd
Metal-oxide-semiconductor, the first phase inverter, the second phase inverter and first and door；The clock sub-circuit include first resistor, the 3rd phase inverter,
4th phase inverter, the 3rd electric capacity and second and door；
The source electrode of tenth metal-oxide-semiconductor and the 11st metal-oxide-semiconductor is all connected with power end, the grid connection the tenth of the tenth metal-oxide-semiconductor
The drain electrode of metal-oxide-semiconductor and the grid of the 11st metal-oxide-semiconductor, it is the drain electrode of drain electrode the 12nd metal-oxide-semiconductor of connection of the 11st metal-oxide-semiconductor, second anti-
One end of the input of phase device and the second electric capacity, the output end of grid the first phase inverter of connection of the 12nd metal-oxide-semiconductor, the 12nd
The source electrode of metal-oxide-semiconductor connects the other end and ground of the second electric capacity, and first is connected the input of the first phase inverter with the first input end of door
End, first is connected the output end of the second phase inverter with the second input of door, and first is connected slope compensation electricity with the output end of door
3rd input on road and the input of the 3rd phase inverter, one end and second of the output end connection first resistor of the 3rd phase inverter
With the first input end of door；The other end of first resistor connects the input of the 4th phase inverter, also by the 3rd capacitance connection the
The source electrode and ground of 12 metal-oxide-semiconductors, output end connection second and the second input of door of the 4th phase inverter, second with the output of door
End connection PWM circuit.
In described DC-DC conversion equipments, the PWM circuit include error amplifier, comparator, rest-set flip-flop,
Drive circuit, power tube, inductance, diode, the 4th electric capacity, second resistance, 3rd resistor, the 4th resistance and load；
The positive input input reference voltage of the error amplifier, the reverse input end connection second of error amplifier
One end of resistance and one end of 3rd resistor, the inverting input of the output end connection comparator of error amplifier, comparator
Normal phase input end connects the 3rd input of slope compensation circuit, the R ends of the output end connection rest-set flip-flop of comparator, RS triggerings
The second of the S ends connection pulse-generating circuit of device connects the input of drive circuit with the output end of door, the Q ends of rest-set flip-flop,
The grid of the output end connection power tube of the drive circuit；The positive pole of the drain electrode connection diode of power tube, also pass through inductance
Connect voltage input end；Second input of the source electrode connection slope compensation circuit of power tube, also pass through the 4th resistance eutral grounding, institute
State the other end of the negative pole connection second resistance of diode and one end of load, also by the 4th capacity earth, the 3rd electricity
The other end ground connection of resistance, the other end ground connection of load.
Compared to prior art, slope compensation circuit and DC-DC conversion equipment provided by the invention, slope compensation circuit bag
Include copied cells, slope generation unit and control unit；The fixed current of input is replicated and is transferred to tiltedly by the copied cells
Slope generation unit；Slope generation unit is when each clock cycle starts, the slope electricity according to corresponding to producing the fixed current
Pressure, the ramp voltage is superimposed upon on the current sampling signal of input and obtains ramp signal；Control unit is according to input
Control signal starts the slope generation unit and controls slope generation unit to be answered before each clock cycle starts
Position；Its circuit structure is simple, substantially reduces the power consumption and area of DC-DC conversion equipments.
Brief description of the drawings
Fig. 1 is existing slope compensation circuit figure；
Fig. 2 is the circuit diagram of the V-I change-over circuits in Fig. 1；
Fig. 3 is the structured flowchart of slope compensation circuit provided in an embodiment of the present invention；
Fig. 4 is the circuit diagram of slope compensation circuit provided in an embodiment of the present invention；
Fig. 5 is the structured flowchart of DC-DC conversion equipments provided in an embodiment of the present invention；
Fig. 6 is the circuit diagram of pulse-generating circuit in DC-DC conversion equipments provided in an embodiment of the present invention；
Fig. 7 is the circuit diagram of DC-DC conversion equipments Application Example provided in an embodiment of the present invention.
Embodiment
The present invention provides a kind of slope compensation circuit and DC-DC conversion equipments, the slope compensation circuit and is applied to boost
Booster circuit, buck reduction voltage circuits are also applied for, apply also for LED drive circuit；It uses fixed current to fill the first electric capacity
Electric forming ramp voltage, ramp voltage is superimposed upon on sample rate current, to reach the purpose of slope compensation；The letter of its circuit structure
It is single, power consumption can be reduced and reduce chip area.To make the purpose of the present invention, technical scheme and effect clearer, clear and definite, below
The present invention is described in more detail for the embodiment that develops simultaneously referring to the drawings.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
Referring to Fig. 3, slope compensation circuit 10 provided in an embodiment of the present invention includes copied cells 110, slope produces list
Member 120 and control unit 130.The copied cells 110 connects slope generation unit 120 and control unit 130, the slope production
Raw unit 120 connects control unit 130.The fixed current Icharge of input is replicated and is transferred to tiltedly by the copied cells 110
Slope generation unit 120.Slope generation unit 120 produces when each clock cycle starts according to the fixed current Icharge
Corresponding ramp voltage, the ramp voltage is superimposed upon on the current sampling signal ISW of input and obtains ramp signal Ramp.
Control unit 130 starts the slope generation unit 120 and in each clock cycle according to the control signal Pulse of input
Control slope generation unit 120 is resetted before starting.
In the present embodiment, slope generation unit 120 produces ramp voltage using electric capacity charging principle, utilizes fixed current
Icharge charges to the first electric capacity set in slope generation unit 120, the voltage linear on the first electric capacity is increased, you can
Produce ramp voltage；By being resetted to slope generation unit 120, it can drop quickly to the voltage on the first electric capacity and be equal to
Current sampling signal ISW magnitude of voltage, you can make voltage on the first electric capacity linear rise again when charging next time.So obtain
The ramp signal Ramp obtained starting voltage value is equal to current sampling signal ISW magnitude of voltage, ramp signal Ramp highest electricity
Pressure value is equal to the peak of ramp voltage.
Also referring to Fig. 4, in the present embodiment, the copied cells 110 includes the first current mirror 111 and the second current mirror
112, first current mirror 111 is transferred to the second current mirror 112 and replicated again after fixed current is replicated, the second electric current
The electric current that mirror 112 exports after replicating gives slope generation unit.
First current mirror 111 includes the first metal-oxide-semiconductor N1, the second metal-oxide-semiconductor N2, the 3rd metal-oxide-semiconductor N3 and the 4th metal-oxide-semiconductor
N4；Second current mirror 112 includes the 5th metal-oxide-semiconductor P1, the 6th metal-oxide-semiconductor P2, the 7th metal-oxide-semiconductor P3 and the 8th metal-oxide-semiconductor P4；It is described
First metal-oxide-semiconductor N1 grid connects the first metal-oxide-semiconductor N1 drain electrode, the second metal-oxide-semiconductor N2 source electrode and the 3rd metal-oxide-semiconductor N3 grid,
First metal-oxide-semiconductor N1 source electrode and the 3rd metal-oxide-semiconductor N3 source ground, the second metal-oxide-semiconductor N2 grid connect the second metal-oxide-semiconductor N2 leakage
Pole and the 4th metal-oxide-semiconductor N4 grid, the 4th metal-oxide-semiconductor N4 source electrode connect the 3rd metal-oxide-semiconductor N3 drain electrode, the 4th metal-oxide-semiconductor N4 leakage
Pole connects the 5th metal-oxide-semiconductor P1 drain electrode, the 5th metal-oxide-semiconductor P1 grid and the 7th metal-oxide-semiconductor P3 grid, the 5th metal-oxide-semiconductor P1 source
Pole connects the 6th metal-oxide-semiconductor P2 drain electrode, the 6th metal-oxide-semiconductor P2 grid and the 4th metal-oxide-semiconductor N4 grid, the 6th metal-oxide-semiconductor P2 source
Pole and the 8th metal-oxide-semiconductor P4 source electrode are all connected with power end VDD, and the 8th metal-oxide-semiconductor P4 drain electrode connects the 7th metal-oxide-semiconductor P3 source electrode,
7th metal-oxide-semiconductor P3 drain electrode connection slope generation unit 120 and control unit 130.Wherein, the second metal-oxide-semiconductor N2 drain electrode is oblique
The first input end in1 of slope compensation circuit 10, input fixed current Icharge.
The first metal-oxide-semiconductor N1, the second metal-oxide-semiconductor N2, the 3rd metal-oxide-semiconductor N3 and the 4th metal-oxide-semiconductor N4 are NMOS tube, composition the
One current mirror 111.The fixed current Icharge inputs from the second metal-oxide-semiconductor N2 drain electrode, multiple by first current mirror 111
The 5th metal-oxide-semiconductor P1 drain electrode is flowed into after system.5th metal-oxide-semiconductor P1, the 6th metal-oxide-semiconductor P2, the 7th metal-oxide-semiconductor P3 and the 8th metal-oxide-semiconductor P4 are equal
For PMOS, the second current mirror 112 is formed, from the 7th metal-oxide-semiconductor P3 leakage after the fixed current Icharge of inflow is replicated again
Flow out pole.The size of 4 NMOS tubes set in the present embodiment（That is breadth length ratio）Identical, the size of 4 PMOSs is identical.
Make the electric current of the 7th metal-oxide-semiconductor P3 drain electrode outflow equal with fixed current Icharge, it is defeated equivalent to by fixed current Icharge
Enter and charged in slope generation unit 120.
The slope generation unit 120 includes the first electric capacity C1, one end of the first electric capacity C1 connects the 7th metal-oxide-semiconductor P3
Drain electrode and control unit 130, the first electric capacity C1 the other end connection control unit 130.Wherein, the one of the first electric capacity C1
Hold the output end out for slope compensation circuit 10, output ramp signal Ramp.The first electric capacity C1 other end is slope compensation electricity
The second input in2 on road 10, input current sampled signal ISW.
Described control unit 130 includes the 9th metal-oxide-semiconductor N5, the first electric capacity C1's of drain electrode connection of the 9th metal-oxide-semiconductor N5
One end and the 7th metal-oxide-semiconductor P3 drain electrode, the 9th metal-oxide-semiconductor N5 source electrode connect the first electric capacity C1 other end, the 9th metal-oxide-semiconductor N5's
Grid is the 3rd input in3 of slope compensation circuit 10, input control signal Pulse.9th metal-oxide-semiconductor N5 source electrode is also oblique
Second input in2 of slope compensation circuit 10, input current sampled signal ISW.9th metal-oxide-semiconductor N5 is NMOS tube.
Please continue to refer to Fig. 3 and Fig. 4, fixed current Icharge the first current mirror formed by 4 NMOS tubes and 4
Second current mirror of PMOS composition flows out after replicating from the 7th metal-oxide-semiconductor P3 drain electrode.When control signal Pulse is low level
When, the 9th metal-oxide-semiconductor N5 cut-offs, fixed current Icharge charges to the first electric capacity C1, because fixed current Icharge size not
Change can rise the first electric capacity C1 voltage linear, form the slope being superimposed upon on current sampling signal ISW, final output is oblique
Slope signal Ramp.When control signal Pulse is high level, the 9th metal-oxide-semiconductor N5 conductings, the first electric capacity C1 is short-circuited, slope letter
Number Ramp voltage drops to equal with current sampling signal ISW voltage, realizes and resets.
In the present embodiment, control signal Pulse rising edge is before clock cycle CLK rising edge, therefore, control letter
Number Pulse can reset before each clock cycle CLK starts to ramp signal Ramp.Control signal Pulse is changed into low level
There is rising edge again in clock cycle CLK afterwards（Or the rising edge of control signal Pulse trailing edge and clock cycle CLK goes out simultaneously
It is existing）, therefore, fixed current Icharge can charge when each clock cycle starts to the first electric capacity C1 to produce slope electricity
Pressure.
In order to ensure in the case of all dutycycles power-supply system can steady operation, reach the effect of slope compensation,
The capacitance of the first electric capacity C1 needs to meet,For current sampling signal（That is inductive current）Lower drop angle
Rate,For the slope of ramp voltage（Compensate the slope on slope）.
Based on above-mentioned slope compensation circuit, the present embodiment also provides a kind of DC-DC conversion equipments, please refer to fig. 5,
The DC-DC conversion equipments include above-mentioned slope compensation circuit 10, pulse-generating circuit 20 and PWM circuit 30.It is described
Slope compensation circuit 10 connects pulse-generating circuit 20 and PWM circuit 30, and the pulse-generating circuit 20 connects PWM
Circuit 30.The pulse-generating circuit 20 is given birth to OSC according to the oscillator signal of input and believed into corresponding control signal Pulse and clock
Number CLK is simultaneously exported, and the clock signal clk drives the PWM circuit 30 to carry out voltage adjustment and feedback current sampling letter
Number ISW is to slope compensation circuit 10.The slope compensation circuit 10 is according to control signal Pulse and the fixed current of input
Icharge produce corresponding to ramp voltage and be superimposed on current sampling signal ISW, obtain ramp signal Ramp and export to
PWM circuit 30 carries out slope compensation.
The pulse-generating circuit 20 includes control sub-circuit 201 and clock sub-circuit 202, the control sub-circuit 201
The oscillator signal of input is carried out dutycycle reduce processing generation control signal Pulse and be transferred to slope compensation circuit 10 and when
Clock sub-circuit 202, clock sub-circuit 202 enters line delay to the control signal Pulse, dutycycle reduces processing generation clock letter
Number CLK is simultaneously transferred to PWM circuit 30.
Also referring to Fig. 6, wherein, the control sub-circuit 201 includes the tenth metal-oxide-semiconductor P5, the 11st metal-oxide-semiconductor P6, the
12 metal-oxide-semiconductor N6, the first phase inverter I1, the second phase inverter I2 and first and door AND1；The clock sub-circuit 202 includes first
Resistance R1, the 3rd phase inverter I3, the 4th phase inverter I4, the 3rd electric capacity and second and door AND2.Tenth metal-oxide-semiconductor P5, the 11st MOS
Pipe P6 is PMOS, and the 12nd metal-oxide-semiconductor N6 is NMOS tube.
The source electrode of the tenth metal-oxide-semiconductor P5 and the 11st metal-oxide-semiconductor P6 is all connected with power end VDD, the tenth metal-oxide-semiconductor P5 grid
The tenth metal-oxide-semiconductor P5 drain electrode and the 11st metal-oxide-semiconductor P6 grid is connected, the 11st metal-oxide-semiconductor P6 drain electrode connects the 12nd metal-oxide-semiconductor
One end of N6 drain electrode, the second phase inverter I2 input and the second electric capacity C2, the 12nd metal-oxide-semiconductor N6 grid connection first are anti-
Phase device I1 output end, the 12nd metal-oxide-semiconductor N6 source electrode connect the second electric capacity C2 other end and ground, and first and the of door AND1
One input connects the first phase inverter I1 input, and first is connected the defeated of the second phase inverter I2 with door AND1 the second input
Go out end, first is connected the defeated of the 3rd input in3 and the 3rd phase inverter I3 of slope compensation circuit 10 with door AND1 output end
Enter end, the 3rd phase inverter I3 output end connection first resistor R1 one end and second and door AND2 first input end；First
The resistance R1 other end connects the 4th phase inverter I4 input, also passes through the metal-oxide-semiconductor N6 of the 3rd electric capacity C3 connections the 12nd source
Pole and ground, the 4th phase inverter I4 output end connection second and door AND2 the second input, second and door AND2 output end
Connect PWM circuit 30.
Control signal Pulse and clock signal clk are very narrow high impulses caused by the pulse-generating circuit 20, and
Control signal Pulse each high impulse first occurs than the high impulse of clock signal clk.The tenth metal-oxide-semiconductor P5 of the present embodiment setting,
11st metal-oxide-semiconductor P6 size is identical.The electric current that bias current Ibias forms by the tenth metal-oxide-semiconductor P5 and the 11st metal-oxide-semiconductor P6
After mirror replicates, the electric current for flowing through the 11st metal-oxide-semiconductor P6 is equal to bias current Ibias.The oscillator signal OSC of input is that dutycycle is
50% clock, oscillator signal OSC control the 12nd metal-oxide-semiconductor N6 break-make after the first phase inverter I1 is anti-phase.Work as oscillator signal
OSC is high level, and the 12nd metal-oxide-semiconductor N6 ends, and the 11st metal-oxide-semiconductor P6 starts to charge to the second electric capacity C2.As the second electric capacity C2
Voltage be more than the second phase inverter I2 reversal voltage when, the second phase inverter I2 output low level.Second phase inverter I2 output
With oscillator signal OSC by first with door AND1 phases with after output control signal Pulse（Its high level lasting time is very short）.Control
Signal Pulse processed is again by a pin of the 3rd phase inverter I3 output signals I3_out to second and door AND2, signal I3_out
It is very big with control signal Pulse opposite in phase, dutycycle.Arteries and veins based on the clock signal clk required in PWM circuit 30
It is very narrow to rush width, signal I3_out also need into respective handling could generate clock signal clk；Specially：As signal I3_
When out is high level, the delay for the RC circuits that first resistor R1 and the 3rd electric capacity C3 is formed need to be passed through.3rd electric capacity C3 voltage
（Such as high level）It is anti-phase by the 4th phase inverter I4（Export low level）Another pin to second and door AND2 is exported afterwards, and the 4th is anti-
Phase device I4 output is by second and door AND2 and signal I3_out phases and final i.e. output clock signal clk.
Also referring to Fig. 7, the present embodiment is by taking the DC-DC conversion equipments to boost as an example, then the PWM circuit 30 is adopted
With boosting mode, it includes error amplifier EA, comparator COMP, rest-set flip-flop G, drive circuit, power tube M0, inductance L, two
Pole pipe D, the 4th electric capacity C4, second resistance R2,3rd resistor R3, the 4th resistance R4 and load RL.
The positive input input reference voltage VREF of the error amplifier EA, error amplifier EA reverse input end
Second resistance R2 one end and 3rd resistor R3 one end are connected, error amplifier EA output end connection comparator COMP's is anti-
Phase input, the 3rd input in3 of comparator COMP normal phase input end connection slope compensation circuit 10, comparator COMP's
Output end connects the R ends of rest-set flip-flop, second and door AND2 of the S ends connection pulse-generating circuit 20 of rest-set flip-flop output
End, the input of the Q ends connection drive circuit of rest-set flip-flop, the output end connection power tube M0 of drive circuit grid；
Power tube M0 drain electrode connection diode D positive pole, also pass through inductance L connection voltage input ends Vin；Power tube M0 source electrode connects
Meet the second input in2 of slope compensation circuit 10, be also grounded by the 4th resistance R4, the negative pole of the diode D（That is voltage
Output end vo ut）Connect the second resistance R2 other end and load RL one end, be also grounded by the 4th electric capacity C4, the described 3rd
Resistance R3 other end ground connection, load RL other end ground connection.
It is to be appreciated that the PWM circuit 30, drive circuit are prior art, the present embodiment mainly illustrates this
Operation principle between slope compensation circuit 10 and pulse-generating circuit 20 that PWM circuit 30 and the present embodiment provide.
The error amplifier EA is by the feedback voltage of the reference voltage V REF of its positive input and its negative input
Exported after FB voltage difference amplification to comparator COMP anti-phase input.Current sampling signal ISW input slope compensation circuit productions
Ramp signal Ramp corresponding to life.Ramp signal Ramp input comparators COMP normal phase input end.Oscillator signal OSC inputs arteries and veins
Rush generation circuit and produce control signal Pulse and clock signal clk.When each clock cycle starts, i.e., on clock signal clk
Rise along when arriving, comparator COMP output low levels, rest-set flip-flop output high level, power tube M0 is opened through overdrive circuit.
Inductance L, power tube M0, the 4th resistance R4, which is formed, arrives earth-return, and electric current flows through the 4th R4, on current sampling signal ISW voltage
Rise, current sampling signal ISW produces the ramp signal Ramp of rising after slope compensation circuit.
When ramp signal Ramp voltage exceedes the voltage of error amplifier EA outputs, the high electricity of comparator COMP outputs
It is flat, rest-set flip-flop output low level, power tube M0 is closed through overdrive circuit, now electric current flows to load RL by diode D
With second resistance R2 and 3rd resistor R3（Sampling resistor）.Because power tube M0 has been switched off, current sampling signal ISW voltage
Decline, decline ramp signal Ramp.
When ramp signal Ramp voltage is less than the voltage that error amplifier EA is exported, comparator COMP exports low electricity
Flat, because the pulse width of clock signal clk is very narrow, now clock signal clk has been low level, so rest-set flip-flop state
Keep, export low level always.Power tube M0 is closed always, until clock signal clk rising edge arrive just start it is next
Clock cycle, so move in circles, it is ensured that the stable voltage of voltage output end Vout outputs.
In summary, slope compensation circuit and DC-DC conversion equipment provided by the invention, using fixed current to the first electricity
Capacity charge forms ramp voltage, and ramp voltage is superimposed upon on current sampling signal, reaches the purpose of slope compensation；Its structure
Simply, the power consumption and area of DC-DC conversion equipments are substantially reduced.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and its hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.
Claims (10)
- A kind of 1. slope compensation circuit, it is characterised in that including：Copied cells, slope generation unit and control unit；The fixed current of input is replicated and is transferred to slope generation unit by the copied cells；Slope generation unit is when each When the clock cycle starts, the ramp voltage according to corresponding to producing the fixed current, the ramp voltage is superimposed upon to the electricity of input Ramp signal is obtained on stream sampled signal；Control unit controls slope generation unit to carry out before each clock cycle starts Reset；The slope generation unit includes the first electric capacity, the first end Connection-copy unit of first electric capacity and control unit, The second end connection control unit of first electric capacity；The first end of first electric capacity be slope compensation circuit output end, first Second end of electric capacity is the second input of slope compensation circuit；Described control unit includes the 9th metal-oxide-semiconductor, and the first end of drain electrode the first electric capacity of connection of the 9th metal-oxide-semiconductor and duplication are single Member, the source electrode of the 9th metal-oxide-semiconductor connect the second end of the first electric capacity；The grid of 9th metal-oxide-semiconductor is the 3rd defeated for slope compensation circuit Enter end；The starting voltage value of ramp signal is equal to the magnitude of voltage of current sampling signal, and the maximum voltage value of ramp signal is equal to slope The peak of voltage；The voltage of current sampling signal rises, and current sampling signal produces what is risen after slope compensation circuit Ramp signal；The voltage of current sampling signal declines, and declines ramp signal.
- 2. slope compensation circuit according to claim 1, it is characterised in that the copied cells include the first current mirror and Second current mirror, first current mirror are transferred to the second current mirror after fixed current is replicated and replicated again, the second electricity The electric current that stream mirror is exported after replicating gives slope generation unit.
- 3. slope compensation circuit according to claim 2, it is characterised in that first current mirror include the first metal-oxide-semiconductor, Second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor；Second current mirror includes the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th MOS Pipe and the 8th metal-oxide-semiconductor；The grid of first metal-oxide-semiconductor connects the drain electrode of the first metal-oxide-semiconductor, the source electrode and the 3rd MOS of the second metal-oxide-semiconductor The source ground of the grid of pipe, the source electrode of the first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid of the second metal-oxide-semiconductor connect the second metal-oxide-semiconductor Drain electrode and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 4th metal-oxide-semiconductor connect the drain electrode of the 3rd metal-oxide-semiconductor, the drain electrode connection of the 4th metal-oxide-semiconductor Drain electrode, the grid of the 5th metal-oxide-semiconductor and the grid of the 7th metal-oxide-semiconductor of 5th metal-oxide-semiconductor, the source electrode of the 5th metal-oxide-semiconductor connect the 6th metal-oxide-semiconductor Drain electrode, the grid of the 6th metal-oxide-semiconductor and the grid of the 4th metal-oxide-semiconductor, the source electrode of the 6th metal-oxide-semiconductor and the source electrode of the 8th metal-oxide-semiconductor connect Connect power end, the source electrode of drain electrode the 7th metal-oxide-semiconductor of connection of the 8th metal-oxide-semiconductor, the drain electrode connection slope generation unit of the 7th metal-oxide-semiconductor and Control unit；The drain electrode of second metal-oxide-semiconductor is the first input end of slope compensation circuit.
- 4. slope compensation circuit according to claim 3, it is characterised in that the first end connection the 7th of first electric capacity The drain electrode of metal-oxide-semiconductor and control unit.
- 5. slope compensation circuit according to claim 4, it is characterised in that the capacitance of first electric capacity meets,For the descending slope of current sampling signal,For the slope of ramp voltage.
- 6. slope compensation circuit according to claim 4, it is characterised in that the drain electrode connection first of the 9th metal-oxide-semiconductor The drain electrode of the first end of electric capacity and the 7th metal-oxide-semiconductor.
- 7. a kind of DC-DC conversion equipments, including pulse-generating circuit and PWM circuit, it is characterised in that also include such as right It is required that any one of 1-6 slope compensation circuits；The pulse-generating circuit control signal and clock signal and exports according to corresponding to generating the oscillator signal of input, described Clock signal drives the PWM circuit to carry out, and voltage adjusts and feedback current sampled signal is to slope compensation circuit；It is described Slope compensation circuit according to control signal and input fixed current produce corresponding to ramp voltage and be superimposed to current sample letter On number, obtain ramp signal and export and give PWM circuit progress slope compensation.
- 8. DC-DC conversion equipments according to claim 7, it is characterised in that the pulse-generating circuit includes control Circuit and clock sub-circuit, the control sub-circuit carry out dutycycle to the oscillator signal of input and reduce processing generation control signal And transmit, clock sub-circuit enters line delay to the control signal, dutycycle reduces processing generation clock signal and transmits.
- 9. DC-DC conversion equipments according to claim 8, it is characterised in that the control sub-circuit includes the tenth MOS Pipe, the 11st metal-oxide-semiconductor, the 12nd metal-oxide-semiconductor, the first phase inverter, the second phase inverter and first and door；The clock sub-circuit includes First resistor, the 3rd phase inverter, the 4th phase inverter, the 3rd electric capacity and second and door；The source electrode of tenth metal-oxide-semiconductor and the 11st metal-oxide-semiconductor is all connected with power end, and the grid of the tenth metal-oxide-semiconductor connects the tenth metal-oxide-semiconductor Drain electrode and the 11st metal-oxide-semiconductor grid, the drain electrode connection drain electrode of the 12nd metal-oxide-semiconductor of the 11st metal-oxide-semiconductor, the second phase inverter One end of input and the second electric capacity, the grid of the 12nd metal-oxide-semiconductor connect the output end of the first phase inverter, the 12nd metal-oxide-semiconductor Source electrode connects the other end and ground of the second electric capacity, and first is connected the input of the first phase inverter with the first input end of door, and first The output end of the second phase inverter is connected with the second input of door, first is connected the 3rd of slope compensation circuit with the output end of door The input of input and the 3rd phase inverter, one end and second and the of door of the output end connection first resistor of the 3rd phase inverter One input；The other end of first resistor connects the input of the 4th phase inverter, also passes through the metal-oxide-semiconductor of the 3rd capacitance connection the 12nd Source electrode and ground, output end connection second and the second input of door of the 4th phase inverter, second is connected PWM with the output end of door Modulation circuit.
- 10. DC-DC conversion equipments according to claim 9, it is characterised in that the PWM circuit is put including error Big device, comparator, rest-set flip-flop, drive circuit, power tube, inductance, diode, the 4th electric capacity, second resistance, 3rd resistor, 4th resistance and load；The positive input input reference voltage of the error amplifier, the reverse input end connection second resistance of error amplifier One end and 3rd resistor one end, error amplifier output end connection comparator inverting input, the positive of comparator Input connects the 3rd input of slope compensation circuit, and the output end of comparator connects the R ends of rest-set flip-flop, rest-set flip-flop The second of S ends connection pulse-generating circuit is described with the output end of door, the input of the Q ends connection drive circuit of rest-set flip-flop The grid of the output end connection power tube of drive circuit；The positive pole of the drain electrode connection diode of power tube, also pass through inductance connection Voltage input end；Second input of the source electrode connection slope compensation circuit of power tube, also by the 4th resistance eutral grounding, described two The other end of the negative pole connection second resistance of pole pipe and one end of load, also by the 4th capacity earth, the 3rd resistor The other end is grounded, the other end ground connection of load.
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| CN201510255200.6A CN104901534B (en) | 2015-05-19 | 2015-05-19 | A kind of slope compensation circuit and DC DC conversion equipments |
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| CN106603012B (en) * | 2016-12-09 | 2020-06-30 | 重庆西南集成电路设计有限责任公司 | Broadband temperature compensation voltage-controlled oscillator, temperature compensation method and voltage generation circuit |
| CN106953508B (en) * | 2017-04-19 | 2024-03-08 | 上海晶丰明源半导体股份有限公司 | Total harmonic distortion optimization circuit and method, driving controller and switching power supply system |
| CN108649800B (en) * | 2018-05-31 | 2020-01-10 | 电子科技大学 | Self-adaptive slope compensation circuit |
| CN109149931B (en) * | 2018-08-29 | 2019-10-11 | 北京机械设备研究所 | Slope-error compensation circuit for peak value comparison method BUCK converter |
| CN109412397B (en) * | 2018-09-12 | 2021-03-23 | 长安大学 | Secondary ramp compensation circuit of pulse width modulation current mode switching power supply |
| CN114285251B (en) * | 2021-12-24 | 2024-05-17 | 西安理工大学 | Circuit for improving load capacity of switching power supply |
| CN114812640B (en) * | 2022-03-14 | 2023-09-19 | 北京市农林科学院智能装备技术研究中心 | Sensing signal copying method and device |
| CN115987068A (en) * | 2023-03-17 | 2023-04-18 | 苏州锴威特半导体股份有限公司 | Driving tube control circuit, control method and switching power supply |
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| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
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| US7176668B2 (en) * | 2004-07-08 | 2007-02-13 | Matsushita Electric Industrial Co., Ltd. | Switching regulator with advanced slope compensation |
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| CN101882871A (en) * | 2008-12-30 | 2010-11-10 | 东部高科股份有限公司 | Slope compensation circuit |
| CN101964587A (en) * | 2009-04-06 | 2011-02-02 | 成都芯源系统有限公司 | Direct current converter and control circuit and method for direct current converter |
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