CN103401420B - Be applied to the self adaptation turn-on time generation circuit in dc-dc - Google Patents

Abstract

The invention discloses a kind of self adaptation turn-on time generation circuit be applied in dc-dc, the weak and fixing ON time control model of the transient response ability of existing electric current and voltage mode control of mainly solving brings the problem of electromagnetic interference.The present invention includes input voltage sampling unit (1), output voltage current sample compensating unit (2) and comparing and logical time generation unit (3).Input voltage sampling unit (1) is to the input voltage V of transducer _iNsampling, output voltage signal V _c; Output voltage current sample compensating unit (2), to the voltage sample of dual switch interface point in transducer, exports the output voltage sampled signal V after compensating _oUT1; Compare with logical time generation unit (3) voltage signal V _cwith the output voltage sampled signal V after compensation _oUT1compare union, export the pulse signal DR controlling main switch conducting.Invention increases the transient response ability of transducer, avoid the impact of electromagnetic interference on late-class circuit, can be used for dc-dc.

Description

Be applied to the self adaptation turn-on time generation circuit in dc-dc

Technical field

The invention belongs to electronic circuit technology field, relate to analog integrated circuit, particularly a kind of self adaptation turn-on time generation circuit, can be used for the dc-dc of ON time control model.

Background technology

Along with high-speed digital system becomes increasingly complex as CPU processor, DSP etc. become, also more and more higher to the requirement of the load transient response ability of power management chip, traditional current control mode and voltage mode control are due to needs error amplifier and compensating network, and the fixed frequency signal produced by oscillator is to trigger the unlatching of main switch, greatly have impact on the transient response ability of chip.

Fixing ON time control model, owing to not needing error amplifier and compensating circuit, has good transient response ability.The system configuration of typical fixing ON time control model dc-dc as shown in Figure 1.As output feedack voltage V _fBbe less than reference voltage V _rEFtime, rear class comparator produces high level and triggers main switch MN ₁conducting, inductive current I _lrise, output voltage V _oUTraise, main switch MN ₁oN time control by fixing turn-on time generation circuit; After fixing ON time terminates, main switch MN ₁turn off, lock-in tube MN ₂open, inductive current I _ldecline, output voltage V _oUTreduce, as output feedack voltage V _fBagain be less than reference voltage V _rEFtime, main switch MN ₁conducting again, main switch MN after fixed duration ₁turn off, repeat with this.Fixing ON time control model dc-dc has superior transient response characteristic, but when input and output voltage changes, because the ON time of each work period main switch is fixed, so chip switch frequency with change in duty cycle, can bring larger electromagnetic interference (EMI) interference to rear class system.

For typical dc-dc, according to its basic functional principle, formula 1 can be obtained).

$T_{\mathrm{SW}}=\frac{V_{\mathrm{IN}}}{V_{\mathrm{OUT}}}{T}_{\mathrm{ON}}---1)$

Wherein, T _sWthe switch periods of dc-dc, T _oNthe ON time of main switch, according to formula 1) can find out, as input voltage V _iNwith output voltage V _oUTwhen any one changes, due to main switch ON time T _oNfixing, the switch periods T of dc-dc _sWwill change thereupon, thus carry out the problem of electromagnetic interference (EMI) to rear class system band.

Summary of the invention

More weak and the tradition of the transient response ability for conventional current and voltage mode control DC-DC chip of the object of the invention is to fixes the problem that ON time control model can bring electromagnetic interference (EMI), a kind of self adaptation turn-on time generation circuit be applied in dc-dc is proposed, by sampling input and output voltage and load information, produce and output voltage V _oUTbe directly proportional, with input voltage V _iNbe inversely proportional to, increase with load current and the main switch ON time that increases simultaneously, avoid the electromagnetic interference (EMI) brought to rear class system with change in duty cycle due to chip switch frequency, improve transient response speed.

For achieving the above object, the present invention includes:

Input voltage sampling unit 1, for dc-dc input voltage V _iNinformation is sampled, and produces and input voltage V _iNwith the voltage signal V that main switch ON time in dc-dc is directly proportional _c, input to comparator and temporal logic generation unit 3;

Output voltage current sample compensating unit 2, for the voltage V of main switch in dc-dc of sampling and synchro switch pipe interface point SW _sW, and the output voltage V of dc-dc that sampled result is added to _oUTon, the output voltage sampled signal V after being compensated _oUT1, input to comparator and temporal logic generation unit 3;

Comparator and temporal logic generation unit 3, for the voltage signal V inputted input voltage sampling unit 1 _cwith the output voltage sampled signal V after the compensation of output voltage current sample compensating unit 2 input _oUT1compare, and the comparison signal PWM that comparative result and dc-dc internal comparator produce is carried out comprehensively, produce the inverted signal controlling main switch open-interval pulse signal DR and DR in dc-dc the inverted signal of this DR be connected to input voltage sampling unit 1.

The present invention compared with prior art has the following advantages:

1. the present invention directly triggers main switch open by comparing output feedack voltage and reference voltage signal, and do not need error amplifier and feedback network, therefore compare with voltage mode control with traditional current control mode, there is better transient response ability.

2. the self adaptation turn-on time generation circuit proposed in the present invention, by sampling input and output voltage and load current information, can produce and output voltage V _oUTbe directly proportional, with input voltage V _iNbe inversely proportional to, increase and the main switch ON time of increase with load current simultaneously, this ensures that there chip switch frequency substantially not with duty ratio and load current change, avoid the fixing ON time control model of tradition and carry out electromagnetic interference to rear class system band.

Accompanying drawing explanation

Fig. 1 is the system block diagram of the fixing ON time control model dc-dc of tradition;

Fig. 2 is structured flowchart of the present invention;

Fig. 3 is input voltage sampling unit in first embodiment of the invention and compares and temporal logic generation unit circuit theory diagrams;

Fig. 4 is output voltage current sample compensating unit circuit theory diagrams in first embodiment of the invention;

Fig. 5 is the input voltage sampling unit circuit theory diagrams in second embodiment of the invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment, the invention will be further described.

Embodiment 1:

With reference to Fig. 2, self adaptation turn-on time generation circuit of the present invention comprises: input voltage sampling unit 1, output voltage current sample compensating unit 2 and comparing and temporal logic generation unit 3.

Described input voltage sampling unit 1, is provided with three inputs a, b, c and an output d; Wherein first input end a and the second input b are connected the input voltage V of dc-dc respectively _iNwith dc-dc internal reference voltage V _r, to the input voltage V of dc-dc _iNsample; 3rd input c connects and compares the pulse inverted signal exported with temporal logic generation unit 3 ; Output d output voltage signal V _cto comparing and temporal logic generation unit 3, this voltage signal V _cbe proportional to the input voltage V of dc-dc _iNwith the ON time of main switch in dc-dc.

Described output voltage current sample compensating unit 2, is provided with four inputs e, f, g, h and an output i; The wherein output voltage V of first input end e and dc-dc _oUTbe connected; Second input f is connected with synchro switch pipe interface point SW with main switch in dc-dc, for the voltage V of this interface point SW that samples _sW, and the output voltage V of dc-dc that it is added to _oUTon; 3rd input g and four-input terminal h are connected two Non-overlapping clock signal S that dc-dc inside produces respectively ₁and S ₂; Output i exports the output voltage sampled signal V after compensating _oUT1to comparing and temporal logic generation unit 3.

Describedly to compare and temporal logic generation unit 3, be provided with three inputs j, k, p and two outputs m, n; The voltage signal V that first input end j and the 3rd input p inputs with input voltage sampling unit 1 respectively _cwith the output voltage sampled signal V after the compensation of output voltage current sample compensating unit 2 input _oUT1be connected, for voltage signal V _cwith the output voltage sampled signal V after compensation _oUT1compare; The comparison signal PWM that second input k and dc-dc internal comparator produce is connected, and its first output m exports pulse inverted signal ; Second output n output pulse signal DR.

With reference to Fig. 3, input voltage sampling unit 1 of the present invention, comprises error amplifier 101, two PMOS M ₁₀₁, M ₁₀₂, 3 NMOS tube M ₁₀₃~ M ₁₀₅, the first resistance R ₁with the first electric capacity C ₁; Of the present inventionly to compare and temporal logic generation unit 3, comprise comparator 301 and rest-set flip-flop 302.

Described error amplifier 101, its in-phase input end is connected to NMOS tube M ₁₀₃drain electrode; Its anti-phase input termination dc-dc internal reference voltage V _r; Its output is connected to NMOS tube M ₁₀₃and M ₁₀₄grid; NMOS tube M ₁₀₃drain electrode by the first resistance R ₁be connected to the input voltage V of dc-dc _iN, its source electrode receives ground; NMOS tube M ₁₀₄drain electrode and PMOS M ₁₀₁source drain be connected, its source electrode receive ground; Due to NMOS tube M ₁₀₃, M ₁₀₄pipe number identical with breadth length ratio, therefore flow through NMOS tube M ₁₀₃and M ₁₀₄electric current equal, i.e. I ₁=I ₂.

Described PMOS M ₁₀₁with M ₁₀₂, form current-mirror structure, its source electrode receives dc-dc internal electric source VDD; PMOS M ₁₀₂drain electrode by the first electric capacity C ₁be connected to ground, simultaneously as the output of input voltage intelligence sample circuit 1, output voltage signal V _c; Due to PMOS M ₁₀₁, M ₁₀₂pipe number identical with breadth length ratio, therefore flow through PMOS M ₁₀₁and M ₁₀₂electric current equal, i.e. I ₂=I ₃.

Described NMOS tube M ₁₀₅, its drain electrode and PMOS M ₁₀₂drain electrode be connected; Its source electrode receives ground; Its grid connects and compares the pulse inverted signal exported with temporal logic generation unit 3

Can be obtained by above-mentioned voltage-current relationship: $I_3=I_2=I_1\frac{V_{\mathrm{IN}}-V_R}{R_1}---2).$

Described comparator 301, the voltage signal V that its homophase and input voltage sampling unit 1 input _cbe connected; Output voltage sampled signal V after the compensation that its inverting input and output voltage current sample compensating circuit 2 input _oUT1be connected; Its output is connected to rest-set flip-flop 302;

Described rest-set flip-flop 302, is provided with two inputs, is respectively and puts 1 end S and clear 0 end R; Its clear 0 end R is connected with the output of comparator 301; It is put 1 end S and is connected with the pwm signal that dc-dc inside produces; Its forward output Q output pulse signal DR; Reversed-phase output the inverted signal of output pulse signal

As the output voltage V of DC-DC controller _oUTduring reduction, the comparison signal PWM that dc-dc inside produces is uprised by low, the pulse signal DR that the positive output end of rest-set flip-flop 302 exports is uprised by low, and the main switch in dc-dc is opened, the inverted signal of the pulse signal of the reversed-phase output output of rest-set flip-flop 302 simultaneously by high step-down, NMOS tube M ₁₀₅turn off.Flow through PMOS M ₁₀₂electric current I ₃charge to the first electric capacity C1, the voltage signal V that input voltage sampling unit 1 exports _crise from zero with fixed slope.As voltage signal V _crise to the output voltage sampled signal V after compensation _oUT1time, the signal that comparator 301 exports is uprised by low, and the pulse signal DR that triggered RS flip-flop 302 exports is by high step-down, and the main switch controlled in dc-dc turns off, so the opening time T of main switch _oNformula 3 can be expressed as)

$T_{\mathrm{ON}}=\frac{V_{\mathrm{OUT}1}{C}_1}{I_3}=\frac{V_{\mathrm{OUT}1}}{(V_{\mathrm{IN}}-V_R)}{C}_1{R}_1---3)$

With reference to Fig. 4, output voltage current sample compensating unit 2 of the present invention, comprises sampling module 21, sampling keeps module 22 and Voltage to current transducer module 23;

Described sampling module 21, comprises 5 PMOS M ₂₀₁~ M ₂₀₅, 2 NMOS tube M ₂₀₈, M ₂₀₉with 3 resistance, i.e. the second resistance R ₂, the 3rd resistance R ₃with the 4th resistance R ₄.Wherein PMOS M ₂₀₁source electrode be connected with the internal electric source VDD of dc-dc, its drain and gate is connected and forms diode structure, and is connected, for late-class circuit provides bias current with the bias current IBIAS that produces of dc-dc inside.PMOS M ₂₀₂with M ₂₀₃grid and PMOS M ₂₀₁grid be connected, its source electrode is connected to dc-dc internal electric source VDD, and its drain electrode is connected respectively to NMOS tube M ₂₀₈and M ₂₀₉drain electrode.NMOS tube M ₂₀₈with M ₂₀₉grid connect together.NMOS tube M ₂₀₈grid and self drain electrode be connected form diode structure, source electrode pass through the second resistance R ₂receive ground.NMOS tube M ₂₀₉source electrode by the 3rd resistance R ₃be connected to main switch and synchro switch pipe interface point SW in dc-dc.PMOS M ₂₀₄with M ₂₀₅grid connect together, and receive PMOS M ₂₀₂drain electrode, its source electrode receives internal electric source VDD.PMOS M ₂₀₄drain electrode receive the 3rd resistance R ₃one end, PMOS M ₂₀₅drain electrode by the 4th resistance R ₄receive ground, PMOS M ₂₀₅drain electrode output voltage difference signal V _bmodule 22 is kept to sampling.

When lock-in tube is opened, the voltage V of main switch and synchro switch pipe interface point SW in dc-dc _sWcan be expressed as:

V _SW＝-R _D2I _LOAD4)

Wherein R _d2for the conducting resistance of synchro switch pipe, I _lOADrepresent the load current of dc-dc.

Now, the voltage V of sampling module 21 couples of interface point SW _sWand the voltage difference between ground is sampled, and convert this voltage difference to current signal I _a, the second resistance R ₂with the 3rd resistance R ₃resistance identical, PMOS M ₂₀₄breadth length ratio and PMOS M ₂₀₅identical, and both pipe numbers are also identical, so the current signal I of sampling module 21 _awith the voltage differential signal V exported _bbe expressed as:

$I_A=\frac{0-V_{\mathrm{SW}}}{R_2}=\frac{R_{D2}{I}_{\mathrm{LOAD}}}{R_2}---5)$

$V_B=I_A{R}_4=\frac{R_4{R}_{D2}{I}_{\mathrm{LOAD}}}{R_2}---6).$

Described sampling keeps module 22, comprises 2 NMOS tube M ₂₁₀and M ₂₁₁, the 5th resistance R ₅with the second electric capacity C2; Wherein NMOS tube M ₂₁₀grid and the clock signal S that produces of dc-dc inside ₁be connected, the voltage differential signal V that its drain electrode inputs with sampling module 21 _bbe connected; 5th resistance R ₅with the second electric capacity C ₂after series connection, be connected across NMOS tube M ₂₁₀source electrode and ground between; 5th resistance R ₅with the second electric capacity C ₂common port export sampling or inhibit signal V _ato Voltage to current transducer module 23; NMOS tube M ₂₁₁grid and the clock signal S that produces of dc-dc inside ₂be connected, its drain electrode and sampling or inhibit signal V _aconnect, its source electrode is connected to ground.

When the lock-in tube in dc-dc is opened, the clock signal S that dc-dc inside produces ₁for high level, S ₂for low level, voltage differential signal V _bbe sampled the in-phase end of error amplifier 201, when the lock-in tube in dc-dc turns off, when main switch is opened, the clock signal S that dc-dc inside produces ₁and S ₂be low level, sample the sampled signal V obtained _abe kept.5th resistance R ₅with the second electric capacity C ₂simultaneously also to sampled signal V _acarry out RC filtering.The clock signal S that DC-DC inside produces ₂main switch shutdown moment in dc-dc can produce a high level burst pulse, discharges the second electric capacity C ₂the electric charge of upper maintenance, for sampling is prepared next time.

Described negative feedback module 23, comprises error amplifier 201,2 PMOS M ₂₀₆, M ₂₀₇, 1 NMOS tube M ₂₁₂with 4 resistance, i.e. the 6th resistance R ₆, the 7th resistance R ₇, the 8th resistance R ₈with the 9th resistance R ₉.The output of error amplifier 201 receives NMOS tube M ₂₁₂grid, its in-phase input end with sample keep module 22 to input sampling or inhibit signal V _abe connected, its inverting input is connected to NMOS tube M ₂₁₂source electrode.6th resistance R6 is connected across NMOS tube M ₂₁₂source electrode and ground between.PMOS M ₂₀₆with M ₂₀₇form current-mirror structure, its source electrode receives dc-dc internal electric source VDD jointly.PMOS M ₂₀₆drain electrode and NMOS tube M ₂₁₂drain electrode be connected.PMOS M ₂₀₇drain electrode by the 7th resistance R ₇be connected to ground.8th resistance R ₈with the 9th resistance R ₉, series connection is connected across the output and PMOS M that connect dc-dc ₂₀₇drain electrode between.8th resistance R ₈with the 9th resistance R ₉common port export compensate after output voltage sampled signal V _oUT1.

In this example, the second resistance R ₂, the 3rd resistance R ₃, the 4th resistance R ₄, the 6th resistance R ₆with the 7th resistance R ₇resistance identical, PMOS M ₂₀₆breadth length ratio and PMOS M ₂₀₇identical, and both pipe numbers are also identical.If flow through the 9th resistance R ₉electric current be I _c, therefore flow through PMOS M ₂₀₇the electric current I of drain terminal _bwith the output voltage V of DC-DC converter _oUTcan be expressed as respectively:

$I_B=\frac{V_A}{R_6}=\frac{V_B}{R_6}=\frac{R_{D2}{I}_{\mathrm{LOAD}}}{R_2}---7)$

V _OUT＝I _C(R ₉+R ₈+R ₇)+I _BR ₇8)。

In this example, get the 9th resistance R ₉resistance equal the 7th resistance R ₇with the 8th resistance R ₈sum, the output voltage sampled signal V after the compensation of therefore output voltage current sample compensating unit 2 output _oUT1can be expressed as:

$V_{\mathrm{OUT}1}=I_C(R_8+R_7)+I_8{R}_7=\frac{V_{\mathrm{OUT}}-I_B{R}_7}{2}+I_B{R}_7=\frac{V_{\mathrm{OUT}}+I_B{R}_7}{2}---9)$

By formula 7) substitute into formula 9), can obtain:

$V_{\mathrm{OUT}1}=\frac{V_{\mathrm{OUT}}+I_B{R}_7}{2}=\frac{V_{\mathrm{OUT}}+\frac{R_{D2}}{R_2}{R}_7{I}_{\mathrm{LOAD}}}{2}=\frac{V_{\mathrm{OUT}}+R_{D2}{I}_{\mathrm{LOAD}}}{2},---10)$

According to formula 10) V that output voltage intelligence sample compensating circuit 2 is exported _oUT1signal list is shown as K (V _oUT+ I _lOADr _d2), K is 1/2 in the present embodiment.In physical circuit design, by changing the second resistance R ₂to the 4th resistance R ₄, the 6th resistance R ₆to the 9th resistance R ₉ratio and PMOS M ₂₀₄, M ₂₀₅and M ₂₀₆, M ₂₀₇proportionate relationship, obtain need K value.

Due to the conducting resistance R of the main switch in dc-dc and lock-in tube _d1, R _d2, and on the series equivalent resistance of inductance, generation has extra voltage drop; Adopt the switching frequency f of the dc-dc of self adaptation ON time control model _sWslightly can change with the change of load current, the wherein conducting resistance R of main switch and lock-in tube _d1, R _d2play a major role.

According to volt-second equilibrium principle, formula 11 can be obtained):

(V _IN-V _OUT-I _LOADR _D1)D＝(1-D)(V _OUT+I _LOADR _D2) 11)

Wherein I _lOADrepresent load current, D represents the duty ratio of dc-dc breaker in middle signal.

By formula 11):

$D=\frac{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{V_{\mathrm{IN}}-(R_{D1}-R_{D2})I_{\mathrm{LOAD}}}---12)$

By formula 12) and formula 3) substitute into formula 1), the switch periods T of dc-dc _sWcan be expressed as;

$T_{\mathrm{SW}}=\frac{V_{\mathrm{IN}}-(R_{D1}-R_{D2})I_{\mathrm{LOAD}}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{T}_{\mathrm{ON}}=\frac{V_{\mathrm{IN}}-(R_{D1}-R_{D2})I_{\mathrm{LOAD}}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}\frac{V_{\mathrm{OUT}1}}{V_{\mathrm{IN}}-V_R}{R}_1{C}_1---13)$

Due to the reference voltage V that dc-dc inside produces _r(R _d1-R _d2) I _lOADvalue much smaller than the input voltage V of dc-dc _iN, therefore, formula 13) can be reduced to:

$T_{\mathrm{SW}}=\frac{V_{\mathrm{OUT}1}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{R}_1{C}_1---14)$

By formula 10) substitute into formula 14), the switch periods T of dc-dc _sWcan be expressed as:

$T_{\mathrm{SW}}=\frac{V_{\mathrm{OUT}1}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{R}_1{C}_1=\frac{\frac{V_{\mathrm{OUT}}+R_{D2}{I}_{\mathrm{LOAD}}}{2}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{R}_1{C}_1=\frac{R_1{C}_1}{2}---15)$

By formula 15) switching frequency f can be obtained _sWfor:

$f_{\mathrm{SW}}=\frac{1}{T_{\mathrm{SW}}}=\frac{2}{R_1{C}_1},---16)$

Visible, the switching frequency f of the dc-dc of application the present embodiment _sWonly with the first resistance R ₁with the first electric capacity C ₁value relevant, completely not with duty ratio and load current change and change.

Embodiment 2:

Output voltage current sample compensating unit 2 of the present invention with compare identical with embodiment 1 with temporal logic generation unit 3.

With reference to Fig. 5, input voltage sampling unit 1 of the present invention comprises: operational amplifier 401,2 PMOS M ₄₀₁, M ₄₀₂, 2 NMOS tube M ₄₀₄, M ₄₀₅, the 3rd electric capacity C ₃with 3 resistance, i.e. the tenth resistance R ₁₀, the 11 resistance R ₁₁with the 12 resistance R ₁₂;

Described 11 resistance R ₁₁with the 12 resistance R ₁₂series connection, is connected across the input voltage V of dc-dc _iNand between ground;

Described operational amplifier 401, its in-phase input end is connected to the 11 resistance R ₁₁with the 12 resistance R ₁₂common port; Its inverting input and NMOS tube M ₄₀₄source electrode be connected; Its output is connected to NMOS tube M ₄₀₄grid;

Described NMOS tube M ₄₀₄, its drain electrode and PMOS M ₄₀₁source drain be connected; Its source electrode is connected to ground by the 12 resistance;

Described PMOS M ₄₀₁with M ₄₀₂, its grid is connected, and forms current-mirror structure; Its source electrode receives dc-dc internal electric source VDD; PMOS M ₄₀₂drain electrode by the 3rd electric capacity C ₃be connected to ground, simultaneously as the output of input voltage sampling unit 1, output voltage signal V _c;

Described NMOS tube M ₄₀₅, its drain electrode and PMOS M ₄₀₂drain electrode be connected; Its source electrode receives ground; Its grid with compare the pulse inverted signal with the input of temporal logic generation unit 3 be connected.

PMOS M can be flow through by above-mentioned voltage-current relationship ₄₀₂electric current I ₃' be:

$I_3^{\′}=\frac{V_{\mathrm{IN}}{R}_{11}}{(R_{10}+R_{11})R_{12}}---17)$

Convolution 3) can obtain corresponding to the present embodiment dc-dc in the ON time T of main switch _o' _nfor:

$T_{\mathrm{ON}}^{\′}=\frac{V_{\mathrm{OUT}1}{C}_3}{I_3^{\′}}=\frac{V_{\mathrm{OUT}1}(R_{10}+R_{11})R_{12}{C}_3}{V_{\mathrm{IN}}{R}_{11}}---18)$

By formula 12) and formula 18) substitute into formula 1), the switch periods T of the dc-dc in the present embodiment _s' _wcan be expressed as:

$T_{\mathrm{SW}}^{\′}=\frac{V_{\mathrm{IN}}-(R_{D1}-R_{D2})I_{\mathrm{LOAD}}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2}}{T}_{\mathrm{ON}}^{\′}=\frac{V_{\mathrm{IN}}-(R_{D1}-R_{D2})I_{\mathrm{LOAD}}}{V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}+R_{D2}}\frac{V_{\mathrm{OUT}1}(R_{10}+R_{11})R_{12}{C}_3}{V_{\mathrm{IN}}{R}_{11}}$

19）

Due to (R _d1-R _d2) I _lOADvalue much smaller than the input voltage V of dc-dc _iN, therefore, formula 19) can be reduced to:

$T_{\mathrm{SW}}^{\′}=\frac{V_{\mathrm{OUT}1}(R_{10}+R_{11})R_{12}{C}_3}{(V_{\mathrm{OUT}}+I_{\mathrm{LOAD}}{R}_{D2})R_{11}},---20)$

By formula 10) substitute into formula 20), the switch periods T of dc-dc _s' _wcan be expressed as:

$T_{\mathrm{SW}}^{\′}=\frac{(R_{10}+R_{11})R_{12}{C}_3}{{2R}_{11}},---21)$

By formula 21) switching frequency f can be obtained _s' _wfor:

$f_{\mathrm{SW}}^{\′}=\frac{1}{T_{\mathrm{SW}}^{\′}}=\frac{{2R}_{11}}{(R_{10}+R_{11})R_{12}{C}_3},---22)$

Visible, the switching frequency f of the dc-dc of application the present embodiment _s' _walso only with the tenth resistance R ₁₀, the 11 resistance R ₁₁, the 12 resistance R ₁₂with the 3rd electric capacity C ₃value relevant, completely not with duty ratio and load current change and change.

By the switching frequency f of the dc-dc of above two embodiments _sWand f _s' _wcan find out, adopt the switching frequency of dc-dc of the present invention only relevant with fixing capacitance with fixing resistance value, not change with the change of duty ratio and load current completely.Overcoming the fixing ON time control model of tradition due to switching frequency to carry out the problem of electromagnetic interference to rear class system band with change in duty cycle.Adopt dc-dc of the present invention simultaneously, directly trigger main switch open by comparing output feedack voltage and reference voltage signal, and do not need error amplifier and feedback network, therefore compare with voltage mode control with traditional current control mode, there is better transient response ability.

Below be only two preferred example of the present invention, do not form any limitation of the invention, obviously under design of the present invention, different changes and improvement can be carried out to its circuit, but these are all at the row of protection of the present invention.

Claims (7)

1. be applied to a self adaptation turn-on time generation circuit for dc-dc, comprise:

Input voltage sampling unit (1), for dc-dc input voltage V _iNinformation is sampled, and produces and input voltage V _iNwith the voltage signal V that main switch ON time in dc-dc is directly proportional _c, input to and compare and temporal logic generation unit (3);

Output voltage current sample compensating unit (2), for the voltage V of main switch in dc-dc of sampling and synchro switch pipe interface point SW _sW, and the output voltage V of dc-dc that sampled result is added to _oUTon, the output voltage sampled signal V after being compensated _oUT1, input to and compare and temporal logic generation unit (3); Output voltage current sample compensating unit comprises sampling module (21), sampling keeps module (22) and Voltage to current transducer module (23);

Described sampling module (21), for the voltage V of main switch in dc-dc and synchro switch pipe interface point SW _sWand the voltage difference between ground is sampled, and export the voltage differential signal V be directly proportional to this voltage difference _bkeep module (22) to sampling;

Described sampling keeps module (22), when opening for the lock-in tube in dc-dc, to the voltage differential signal V that sampling module (21) inputs _bsample, when the lock-in tube in dc-dc turns off, to the voltage differential signal V that sampling module (21) inputs _bkeep, and export sampling or inhibit signal V _ato potential circuit modular converter (23);

Described Voltage to current transducer module (23), for keeping module (22) sampling that inputs or inhibit signal V by sampling _awith the output signal V of dc-dc _oUTsuperpose, the output voltage sampled signal V after being compensated _oUT1;

Relatively with temporal logic generation unit (3), for the voltage signal V inputted input voltage sampling unit (1) _cwith the output voltage sampled signal V after the compensation that output voltage current sample compensating unit (2) inputs _oUT1compare, and the comparison signal PWM that comparative result and dc-dc internal comparator produce is carried out comprehensively, produce and control main switch open-interval pulse signal DR and pulse inverted signal in dc-dc this pulse inverted signal be connected to input voltage sampling unit (1).

2. self adaptation turn-on time generation circuit according to claim 1, is characterized in that input voltage sampling unit (1), comprises error amplifier (101), 2 PMOS M ₁₀₁, M ₁₀₂, 3 NMOS tube M ₁₀₃~ M ₁₀₅, the first resistance R ₁with the first electric capacity C ₁;

Described error amplifier (101), its in-phase input end receives NMOS tube M ₁₀₃drain electrode, its anti-phase input termination dc-dc internal reference voltage V _r; Its output is connected to NMOS tube M ₁₀₃and M ₁₀₄grid;

Described NMOS tube M ₁₀₃, its drain electrode is by the first resistance R ₁be connected to the input voltage V of dc-dc _iN, its source electrode receives ground;

Described NMOS tube M ₁₀₄, its drain electrode and PMOS M ₁₀₁source drain be connected, its source electrode receive ground;

Described PMOS M ₁₀₁with M ₁₀₂, its grid is connected, and form current-mirror structure, its source electrode receives dc-dc internal electric source VDD; PMOS M ₁₀₂drain electrode by the first electric capacity C ₁be connected to ground, simultaneously as the output of input voltage sampling unit (1), output voltage signal V _c;

Described NMOS tube M ₁₀₅, its drain electrode and PMOS M ₁₀₂drain electrode be connected, its source electrode receive ground, its grid with compare the pulse inverted signal with the input of temporal logic generation unit (3) be connected.

3. self adaptation turn-on time generation circuit according to claim 1, is characterized in that the sampling module (21) in output voltage current sample compensating unit (2), comprises 5 PMOS M ₂₀₁~ M ₂₀₅, 2 NMOS tube M ₂₀₈, M ₂₀₉with 3 resistance, i.e. the second resistance R ₂, the 3rd resistance R ₃with the 4th resistance R ₄;

Described PMOS M ₂₀₁, its source electrode is connected with the internal electric source VDD of dc-dc, and its drain and gate is connected and forms diode structure, and the bias current I that produce inner with dc-dc _bIASbe connected, for late-class circuit provides bias current;

Described PMOS M ₂₀₂with M ₂₀₃, its grid and PMOS M ₂₀₁grid be connected, its source electrode is connected to dc-dc internal electric source VDD, and its drain electrode is connected respectively to NMOS tube M ₂₀₈and M ₂₀₉drain electrode;

Described NMOS tube M ₂₀₈with M ₂₀₉, its grid connects together; NMOS tube M ₂₀₈grid and self drain electrode be connected form diode structure, source electrode pass through the second resistance R ₂receive ground, NMOS tube M ₂₀₉source electrode by the 3rd resistance R ₃be connected to main switch and synchro switch pipe interface point SW in dc-dc;

Described PMOS M ₂₀₄with M ₂₀₅, its grid connects together, and receives PMOS M ₂₀₂drain electrode, its source electrode receives internal electric source VDD; PMOS M ₂₀₄drain electrode receive the 3rd resistance R ₃one end, PMOS M ₂₀₅drain electrode by the 4th resistance R4 receive ground, PMOS M ₂₀₅drain electrode output voltage difference signal V _bmodule (22) is kept to sampling.

4. self adaptation turn-on time generation circuit according to claim 1, is characterized in that the sampling in output voltage current sample compensating unit (2) keeps module (22), comprises 2 NMOS tube M ₂₁₀, M ₂₁₁, the 5th resistance R ₅with the second electric capacity C ₂;

Described NMOS tube M ₂₁₀, the clock signal S that its grid and dc-dc inside produce ₁be connected, the voltage differential signal V that its drain electrode inputs with sampling module (21) _bbe connected;

Described 5th resistance R ₅with the second electric capacity C ₂after series connection, be connected across NMOS tube M ₂₁₀source electrode and ground between, the 5th resistance R ₅with the second electric capacity C ₂common port export sampling or inhibit signal V _ato Voltage to current transducer module (23);

Described NMOS tube M ₂₁₁, the clock signal S that its grid and dc-dc inside produce ₂be connected, its drain electrode and sampling or inhibit signal V _aconnect, its source electrode is connected to ground.

5. self adaptation turn-on time generation circuit according to claim 1, it is characterized in that the Voltage to current transducer module (23) in output voltage current sample compensating unit (2), comprise error amplifier (201), 2 PMOS M ₂₀₆, M ₂₀₇, 1 NMOS tube M ₂₁₂with 4 resistance, i.e. the 6th resistance R ₆, the 7th resistance R ₇, the 8th resistance R ₈with the 9th resistance R ₉;

Described error amplifier (201), its output receives NMOS tube M ₂₁₂grid, its in-phase input end with sample keep module (22) to input sampling or inhibit signal V _abe connected, its inverting input is connected to NMOS tube M ₂₁₂source electrode;

Described 6th resistance R6 is connected across NMOS tube M ₂₁₂source electrode and ground between;

Described PMOS M ₂₀₆with M ₂₀₇form current-mirror structure, its source electrode receives dc-dc internal electric source VDD jointly, PMOS M ₂₀₆drain electrode and NMOS tube M ₂₁₂drain electrode be connected, PMOS M ₂₀₇drain electrode by the 7th resistance R ₇be connected to ground;

Described 8th resistance R ₈with the 9th resistance R ₉, series connection is connected across the output and PMOS M that connect dc-dc ₂₀₇drain electrode between, the 8th resistance R ₈with the 9th resistance R ₉common port export compensate after output voltage sampled signal V _oUT1.

6. self adaptation turn-on time generation circuit according to claim 1, is characterized in that comparator and temporal logic generation unit (3), comprises comparator (301) and rest-set flip-flop (302);

Described comparator (301), the voltage signal V that its in-phase input end and input voltage sampling unit (1) input _cbe connected, the output voltage sampled signal V after the compensation that its inverting input and output voltage current sample compensating circuit (2) input _oUT1be connected, its output is connected to rest-set flip-flop (302);

Described rest-set flip-flop (302), is provided with two inputs, is respectively and puts 1 end S and clear 0 end R; Its clear 0 end R is connected with the output of comparator (301), it is put 1 end S and is connected with the comparison signal PWM that dc-dc inside produces, its forward output Q is as the second output of comparator and temporal logic generation unit (3), output pulse signal DR, reversed-phase output the first output of circuit (3) is produced, the inverted signal of output pulse signal DR as comparator and temporal logic

7. self adaptation turn-on time generation circuit according to claim 1, is characterized in that input voltage sampling unit (1), comprises operational amplifier (401), 2 PMOS M ₄₀₁, M ₄₀₂, 2 NMOS tube M ₄₀₄, M ₄₀₅, the 3rd electric capacity C ₃with 3 resistance, i.e. the tenth resistance R ₁₀, the 11 resistance R ₁₁with the 12 resistance R ₁₂;

Described 11 resistance R ₁₁with the 12 resistance R ₁₂series connection, is connected across the input voltage V of dc-dc _iNand between ground;

Described operational amplifier (401), its in-phase input end is connected to the 11 resistance R ₁₁with the 12 resistance R ₁₂common port, its inverting input and NMOS tube M ₄₀₄source electrode be connected, its output is connected to NMOS tube M ₄₀₄grid;

Described NMOS tube M ₄₀₄, its drain electrode and PMOS M ₄₀₁source drain be connected, its source electrode by the 12 resistance be connected to ground;

Described PMOS M ₄₀₁with M ₄₀₂, its grid is connected, and form current-mirror structure, its source electrode receives dc-dc internal electric source VDD, PMOS M ₄₀₂drain electrode by the 3rd electric capacity C ₃be connected to ground, simultaneously as the output of input voltage sampling unit (1), output voltage signal V _c;

Described NMOS tube M ₄₀₅, its drain electrode and PMOS M ₄₀₂drain electrode be connected, its source electrode receive ground, its grid with compare the pulse inverted signal with the input of temporal logic generation unit (3) be connected.