CN108282084B - BUCK converter and its frequency locking control circuit - Google Patents
BUCK converter and its frequency locking control circuit Download PDFInfo
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- CN108282084B CN108282084B CN201810073962.8A CN201810073962A CN108282084B CN 108282084 B CN108282084 B CN 108282084B CN 201810073962 A CN201810073962 A CN 201810073962A CN 108282084 B CN108282084 B CN 108282084B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/072—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate an output voltage whose value is lower than the input voltage
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention provides a kind of BUCK converter and its frequency locking control circuit, the frequency locking control circuit includes: frequency and phase discrimination logic circuit, generates the first control logic signal and the second control logic signal with frequency error information according to the duty cycle signals of Buck converter and the frequency error signal of reference frequency；Charge pump, it is connected with the frequency and phase discrimination logic circuit, being turned on and off for electric current and fan-in electric current is fanned out to according to the first control logic signal and the second control logic signal control respectively, and exports the voltage signal comprising frequency error information to the adaptive turn-on time generation circuit；Current source is fanned out to electric current and the fan-in electric current described in generation.The present invention is by introducing frequency locking control circuit, so that the good switching frequency fluctuation problem for solving the wide wide output of input in practical application of the BUCK converter based on ACOT framework, also greatly improves the EMI characteristic of system.
Description
Technical field
The invention belongs to power electronics fields, more particularly to a kind of BUCK converter and its frequency locking control circuit.
Background technique
Buck converter is also referred to as decompression transducer, is that a kind of output voltage is less than the single tube of input voltage not isolated DC
Converter.Constant on-time (COT) controls the BUCK converter of framework, as the extension of sluggish control framework, has system
Structure is simple, and fast linear response and load response may be implemented.It is constant but for the input and output voltage demand of wide scope
Turn-on time controls meeting so that BUCK converter is when PWM mode is run, the very big frequency variation of generation, system EMI characteristic compared with
Difference.
Aiming at the problem that frequency variation, traditional way is to generate the adaptive conducting changed with input and output voltage
Time (ACOT) is charged using an electric current directly proportional to VIN to a timing capacitor, then by capacitance voltage and VOUT
It is compared and generates an adaptive turn-on time.In the ideal case, adaptive turn-on time Ton=RtCt (Vout/
Vin), wherein Rt is the biasing resistor for generating electric current directly proportional to Vin, and Ct is timing capacitor.And by the voltage of BUCK converter
Transfer characteristic can obtain Ton=(Vout/Vin) Tsw.Thus, can obtain Tsw=RtCt, the switching frequency of PWM loop just mainly by
The setting of RtCt constant.
Silicon Cenda patent " a kind of frequency locking circuit and switching power source control circuit " (publication number: CN201410629335) benefit
Control turn-on time is removed with control information is generated after being divided PWM DUTY CYCLE compared with a benchmark CLK phase demodulation
Charging current controls the frequency locking of PWM loop.Core source system patent " constant on-time control circuit and its direct current-of control
DC converter " (publication number: CN201610979146) is then to generate mistake compared with synchronous base frequency phase demodulation using Ton pulse
Poor information goes the charging current of control turn-on time to control the frequency locking of PWM loop.
The patent formula of silicon Cenda and core source, the two thinking are all the DUTY CYCLE and base of first real-time detection PWM loop
Then frequency error is obtained voltage letter by charge pump control and low-pass filtering by the frequency error of punctual clock or synchronised clock
Number.An error current is converted by this voltage signal finally by current error amplifier or generation circuit, is added to and leads
Logical time charging current to adjust the turn-on time Ton of PWM loop in real time, achievees the purpose that frequency locking.
For adaptive turn-on time control program, in practical applications, as the comparison for generating adaptive turn-on time
Device can have response delay, and PWM control loop can also have transmission delay.In addition, the power MOS conduction impedance of BUCK converter
Pressure drop, the reasons such as the PCB layout resistance drop and inductance DCR resistance drop of power path, can all lead to actual PWM ring
Road turn-on time deviates ideal formula.Therefore, the BUCK converter that ACOT controls framework can also have biggish frequency fluctuation.
And for the patent formula of silicon Cenda and core source, due to finally needing DUTY CYCLE and reference frequency or together
The frequency error for walking clock, is gradually converted to error current information, conversion process compares by way of current error amplifier
It is complicated.The error current amplifier of introducing can also introduce additional pole in frequency-locked loop, frequency-locked loop stabiloity compensation also compared with
It is complicated.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of BUCK converter and its frequency lockings
Control circuit, there are larger frequency fluctuation or frequency locking ring for the BUCK converter for solving ACOT control framework in the prior art
The problem of road stabiloity compensation complexity.
In order to achieve the above objects and other related objects, the present invention provides a kind of frequency locking control circuit of BUCK converter,
The frequency locking control circuit includes: frequency and phase discrimination logic circuit, according to the duty cycle signals of Buck converter and reference frequency
Frequency error signal generates the first control logic signal and the second control logic signal with frequency error information；Charge pump,
It is connected with the frequency and phase discrimination logic circuit, respectively according to the first control logic signal and the second control logic signal
Control is fanned out to being turned on and off for electric current and fan-in electric current, and exports the voltage signal comprising frequency error information to described adaptive
Answer turn-on time generation circuit；Current source is fanned out to electric current and the fan-in electric current described in generation.
In one embodiment of the invention, the frequency and phase discrimination logic circuit includes: the first d type flip flop, receives Buck and becomes
The duty cycle signals of parallel operation；Second d type flip flop receives the frequency error signal of reference frequency；Logic circuit, including by most the
One d type flip flop and second d type flip flop carry out logic and operation with door, the first d type flip flop speed is gone out to carry out reversely
First NOT gate of operation and the transmission gate for transmitting the output of second d type flip flop.
In one embodiment of the invention, two input terminals with door respectively with the end Q of first d type flip flop and
The end Q of second d type flip flop is connected, the output end with door with respectively with the end R of first d type flip flop and described the
The end R of 2-D trigger is connected.
In one embodiment of the invention, the charge pump include with first NOT gate and be fanned out to that electric current is connected first
Second group of switch group switch and be connected with the transmission gate and the fan-in electric current；First group of switch and second group described
The voltage signal output end of the output voltage signal comprising frequency error information is drawn between switch.
In one embodiment of the invention, first group of switch includes that concatenated first PMOS switch and the 2nd PMOS are opened
It closes；Wherein, it first PMOS switch and first NOT gate and is fanned out to electric current and is connected, second PMOS switch passes through second
NOT gate is connected with first NOT gate.
In one embodiment of the invention, second group of switch includes that concatenated first NMOS switch and the 2nd NMOS are opened
It closes；Wherein, first NMOS switch is connected with the transmission gate and fan-in electric current, and second NMOS switch passes through third
NOT gate is connected with the transmission gate.
In one embodiment of the invention, the charge pump further include: the low pass being connected with the voltage signal output end
Filter circuit.
In one embodiment of the invention, the low-pass filter circuit includes: the first filter branch including first capacitor
With the second filter branch including concatenated resistance and the second capacitor.
In one embodiment of the invention, the current source includes: divider resistance, is connected with input voltage, to input electricity
Pressure is divided；Amplifier, non-inverting input terminal are connected with the divider resistance, and reverse input end is connected with a voltage regulation resistance；
PMOS current mirror and NMOS current mirror, are connected with the amplifier respectively, obtain described being fanned out to electric current and institute respectively by mirror image
State fan-in electric current.
The embodiment of the present invention also provides a kind of BUCK converter, and the BUCK converter includes: comprising as described above
The adaptive turn-on time generation circuit of the frequency locking control circuit of BUCK converter, pulse width modulated comparator, error amplifier are defeated
Voltage sample and synchronous slope generating circuit out, input terminal respectively with the adaptive turn-on time generation circuit and the pulsewidth
Modulate the connected rest-set flip-flop of comparator, the closed loop control logic being connected with the rest-set flip-flop output end, power switch
Driving circuit and power stage output circuit including PMOS power switch and NMOS power switch.
In one embodiment of the invention, the adaptive turn-on time generation circuit includes: to be connected with the current source
Turn-on time comparator, timing capacitor and time switch；Wherein, the base stage of the upper time switch is connected with a NOT gate.
In one embodiment of the invention, the non-inverting input terminal of the pulse width modulated comparator connects error amplifier, instead
Output voltage sampling and synchronous slope generating circuit are connected to input terminal.
In one embodiment of the invention, the output voltage sampling includes: filter circuit with synchronous slope generating circuit,
Cycle by Cycle filtering is carried out to the node voltage of Buck inverter power output；Coupled capacitor, with the filter circuit phase
Even, the ramp voltage signal synchronous with the inductive current in the power stage output circuit is exported；Feedback resistance, with voltage output
End is connected, and exports feedback voltage signal.
In one embodiment of the invention, isolation is connected between the ramp voltage signal and the feedback voltage signal
Resistance.
As described above, BUCK converter and its frequency locking control circuit of the invention, have the advantages that
1, the present invention is by introducing frequency locking control circuit, so that keeping tradition based on the BUCK converter of ACOT framework
PWM control loop structure simply and quickly linear/load response advantage while, it is good that solve width in practical application defeated
The switching frequency fluctuation problem for entering wide output, also greatly improves the EMI characteristic of system.
2. the voltage of the invention by controlling frequency locking including frequency error information, directly as adaptive turn-on time
The threshold value compared determines turn-on time compared with timing capacitor voltage (being charged by the electric current directly proportional with VIN to it).Therefore
Frequency-locked loop does not additionally introduce current amplifier pole yet, so that the stability of frequency-locked loop is improved, design also becomes
It is relatively easy.
Detailed description of the invention
Fig. 1 is shown as the integrated circuit theory structure schematic diagram of BUCK converter of the invention.
Fig. 2 is shown as the circuit diagram of the frequency locking control circuit of BUCK converter of the invention.
Fig. 3 is shown as the connection schematic diagram of the turn-on time comparator of BUCK converter of the invention.
The output voltage sampling that Fig. 4 is shown as BUCK converter of the invention is illustrated with the circuit of synchronous slope generating circuit
Figure.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
Referring to FIG. 1 to FIG. 4, it should be noted that diagram provided in following embodiment only illustrates in a schematic way
Basic conception of the invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
The purpose of the present embodiment is that a kind of BUCK converter and its frequency locking control circuit are provided, for solving the prior art
The BUCK converter of middle ACOT control framework has that larger frequency fluctuation or frequency-locked loop stabiloity compensation are complicated.
The principle and embodiment of BUCK converter and its frequency locking control circuit of the invention described in detail below, makes art technology
Personnel do not need creative work and are appreciated that BUCK converter and its frequency locking control circuit of the invention.
The BUCK converter that the BUCK converter and its frequency locking control circuit of the present embodiment are controlled based on traditional ACOT is whole
Body circuit is as shown in Figure 1, introduce an additional frequency locking control circuit in PWM master control loop, directly using after phaselocked loop phase demodulation
Output voltage remove control turn-on time, that is, maintain the advantages of structure is simple and quick response of COT control, also achieve
The problem of switching frequency of PWM loop locks, and avoids switching frequency fluctuation in practical applications.Below to the present embodiment
BUCK converter and its frequency locking control circuit are specifically described.
The present embodiment provides a kind of BUCK converters, as shown in Figure 1, the BUCK converter 1 includes: to control comprising frequency locking
The adaptive turn-on time generation circuit 11 (for generating the adaptive turn-on time with frequency locking information) of circuit 110, pulsewidth
Modulate comparator A2 (Cycle by Cycle relative error voltage Vea and synchronous slope Vramp), rest-set flip-flop 12 (rest-set flip-flop 12 it is defeated
The power switch work of logic Duty closed-loop control BUCK converter 1 out, when Duty is logically high, power power PMOS is led
Logical, power power NMOS is closed；When Duty logic is low, power power PMOS is closed, power power NMOS conducting.
Duty logic is the duty ratio that logically high time accounting is BUCK converter 1 within the period), closed loop control logic 13
(closed loop control logic 13 and power switch driver circuit 14 control BUCK converter 1 with power switch driver circuit 14
The working condition of closed-loop control and power switch and generate the non-overlapping power power PMOS of two-phase driving voltage GH and
The driving voltage GL of power power NMOS), including PMOS power switch (PMOS shown in Fig. 1) and NMOS power switch
Power stage output circuit.Power stage output circuit mainly includes PMOS power switch (PMOS shown in Fig. 1), NMOS power
Switch (NMOS shown in Fig. 1), filter inductance L, filter capacitor C and output loading, power stage output circuit undertake BUCK
1 power of converter and energy output.
In this present embodiment, the adaptive turn-on time generation circuit 11 is used to generate adaptive with frequency locking information
Turn-on time.
In this present embodiment, the adaptive turn-on time generation circuit 11 includes: frequency locking control circuit 110, and described
Current source connected turn-on time comparator A1 (Cycle by Cycle compares frequency locking error Vferr and timing voltage Vct), timing capacitor Ct
With time switch Q；Wherein, the base stage of the upper time switch Q is connected with a NOT gate A.
Specifically, in this present embodiment, as shown in Fig. 2, the frequency locking control circuit 110 includes: frequency and phase discrimination logic electricity
Road 111, charge pump 112 and current source 113.
The frequency and phase discrimination logic circuit 111 is missed according to the duty cycle signals of BUCK converter 1 and the frequency of reference frequency
Difference signal generates the first control logic signal and the second control logic signal with frequency error information.
Specifically, in Yu Benfa embodiment, the frequency and phase discrimination logic circuit 111 includes: the first d type flip flop 111a, is connect
Receive the duty cycle signals of BUCK converter 1；Second d type flip flop 111b, receives the frequency error signal of reference frequency；Logic electricity
It road will including the first d type flip flop 111a of majority and the second d type flip flop 111b being carried out logic and operation and door 111c
The first d type flip flop 111a speed goes out to carry out the first NOT gate 111d of inverted running and by the second d type flip flop 111b's
Export the transmission gate 111c transmitted.Wherein, in this present embodiment, two input terminals with door 111c respectively with it is described
The end Q of first d type flip flop 111a is connected with the end Q of the second d type flip flop 111b, the output end and difference with door 111c
It is connected with the end R at the end R of the first d type flip flop 111a and the second d type flip flop 111b.
The frequency and phase discrimination logic circuit 111 passes through the duty ratio Duty and reference frequency of real-time monitoring BUCK converter 1
The frequency error of Fref generates the control logic UP and DN with frequency error information.UP and DN is respectively used to control charge pump
112 on and off for being fanned out to electric current Isource and fan-in electric current Isink.
The charge pump 112 is connected with the frequency and phase discrimination logic circuit 111, is believed respectively according to first control logic
Number and the second control logic signal control be fanned out to being turned on and off for electric current and fan-in electric current, and exporting includes frequency error
The voltage signal of information is to the adaptive turn-on time generation circuit 11.
Specifically, in this present embodiment, the charge pump 112 includes and the first NOT gate 111d and is fanned out to electric current and is connected
First group of switch and second group of switch being connected with the transmission gate 111c and the fan-in electric current；First group of switch and
The voltage signal output end of the output voltage signal comprising frequency error information is drawn between second group of switch
Vferr。
Wherein, first group of switch includes concatenated first PMOS switch Q1 and the second PMOS switch Q2；Wherein, described
First PMOS switch Q1 with the first NOT gate 111d and be fanned out to electric current Isource and be connected, the second PMOS switch Q2 is logical
112 a of the second NOT gate is crossed to be connected with the first NOT gate 111d；Second group of switch includes concatenated first NMOS switch Q3
With the second NMOS switch Q4；Wherein, the first NMOS switch Q3 with the transmission gate 111c and fan-in electric current Isink phase
Even, the second NMOS switch Q4 is connected by third NOT gate with the transmission gate 111c.The PMOS switch control of UP logic control
System is fanned out to electric current Isource, and the NMOS switch of DN logic control controls fan-in electric current Isink.
In this present embodiment, the charge pump 112 further include: the low-pass filtering electricity being connected with the voltage signal output end
Road.
In this present embodiment, as shown in Fig. 2, the low-pass filter circuit includes: the first filtering including first capacitor C2
Branch and the second filter branch including concatenated resistance R1 and the second capacitor C1.The wherein concatenated combination of resistance R1 capacitor C1 is given
Frequency locking closed loop provides necessary zero compensation.Output voltage Vferr is the voltage signal for including frequency error information.
In this present embodiment, the current source 113, which generates, described is fanned out to electric current Isource and the fan-in electric current Isink.
Specifically, the current source 113 includes: divider resistance (including resistance R3 and resistance R4), with input voltage
(VOUT) it is connected, input voltage is divided；Amplifier (AMP), non-inverting input terminal is connected with the divider resistance (to be connect
Between resistance R3 and resistance R4), reverse input end is connected with a voltage regulation resistance Rf；PMOS current mirror (Q6, Q7, Q8) and
NMOS current mirror (Q9, Q10) is connected with the amplifier (AMP) respectively, obtains described being fanned out to electric current and institute respectively by mirror image
State fan-in electric current.
The current source 113 turns mainly by electric resistance partial pressure output voltage Vout by V-to-I amplifier AMP and resistance Rf
After change, the electric current gm*Vout directly proportional to Vout is obtained.Then by PMOS current mirror and NMOS current mirror, mirror image is obtained respectively
It is fanned out to electric current Isource and input current Isink.It generates the electric current directly proportional to Vout and is used for charge pump 112, can keep locking
The loop stability of frequency closed loop can make the ACOT control BUCK converter 1 proposed by the present invention with frequency locking function be suitable for width
Range output.
Based on charge pump phase lock loop, frequency-locked loop first passes through the DUTY of frequency discrimination/phase device Cycle by Cycle detection PWM loop
Then the frequency error of CYCLE and reference clock Fref obtain frequency error by the control of charge pump 112 and low-pass filtering
One information of voltage.Finally with this information of voltage directly as the comparison threshold value of adaptive turn-on time.In order to adapt to wide scope
Input and output application, be fanned out to used in charge pump 112 electric current Isource and fan-in electric current Isink need to design it is equal, and
It is directly proportional to output voltage.The turn-on time comparator A1 control circuit that the present embodiment is used is as shown in Figure 3.
Wherein, the reverse input end of the turn-on time comparator A1 connects output voltage terminal.The pulsewidth modulation is compared
The non-inverting input terminal connection error amplifier A3 of device A2 (exports feedback reference Vref and output feedback signal by real-time detection
Vfb obtains amplified error voltage Vea, as loop pulsewidth modulation foundation), reverse input end connects an output voltage and adopts
Sample and synchronous slope generating circuit 15 are (for output voltage feedback signal Vfb and and inductance needed for generating ACOT control model
The ramp signal Vramp of current synchronization).
Turn-on time comparator A1 controls output voltage Vferr and timing voltage Ct by real-time comparator frequency locking, by week
Phase obtains the switch conduction times of BUCK converter 1.It is RS in 1 master control loop of BUCK converter that it, which exports logic Vrset,
The reset signal R of trigger 12.
It is obtained with VIN after V-to-I amplifier AMP and resistance Rt conversion at just by electric resistance partial pressure input voltage VIN
The electric current gm*VIN of ratio.Then timing charging current Ict is obtained by PMOS current mirror.When switch periods start, Duty is patrolled
It collects to be high, time switch Q is closed, and timing charging current Ict gives timing capacitor Ct to charge.When timing voltage Vct rises to frequency locking
Control output voltage Vferr when, turn-on time comparator A1 export Vrset be it is logically high, resets Duty be logic low, BUCK
The turn-on time of converter 1 terminates.Therefore, the adaptive turn-on time of generation is to contain frequency error information.Generation and VIN
Directly proportional electric current can make the ACOT control BUCK converter 1 proposed by the present invention with frequency locking function for periodically charging
It is inputted suitable for wide scope.
That is, obtaining the electric current Ict directly proportional to input voltage vin by V-to-I conversion circuit and giving timing electricity
Hold Ct charging.As previously mentioned, PWM loop turn-on time Ton=RtCt (Vferr/Vin) at this time, Vferr are to include frequency
The voltage signal of control information.As can be seen that design through the invention, the BUCK converter 1 based on ACOT control framework is right
In the control of switching frequency, it actually is equivalent to a voltage controlled oscillator.Voltage Vferr controls turn-on time Ton, and then controls
Switching frequency.The frequency locking control circuit 110 of introducing does not introduce additional fortune other than the low-pass filtering pole that itself is needed
Pole is put, so that the stabiloity compensation of loop becomes simple.
In order to adapt to the input and output application of wide scope, what the charge pump 112 of frequency locking control circuit 110 controlled is fanned out to electric current
Need to be designed to electric current equal in magnitude, and proportional to 1 reality output of BUCK converter with fan-in electric current, to avoid exporting
The difference of voltage and the stability for influencing frequency-locked loop.
In this present embodiment, the non-inverting input terminal of the pulse width modulated comparator A2 connects error amplifier A3, reversed defeated
Enter the sampling of one output voltage of end connection and synchronous slope generating circuit 15.
The error amplifier A3 exports feedback reference Vref and output feedback signal Vfb by real-time detection, is put
Error voltage Vea after big, as loop pulsewidth modulation foundation.
In this present embodiment, the output voltage sampling is with synchronous slope generating circuit for generating ACOT control model institute
The output voltage feedback signal Vfb and the ramp signal Vramp synchronous with inductive current needed.
Specifically, as shown in figure 4, it includes: filter circuit, coupling that the output voltage, which is sampled with synchronous slope generating circuit 15,
Close capacitor and feedback resistance.
In this present embodiment, the filter circuit carries out by week the node voltage of 1 power output of BUCK converter
Phase filtering；The filter circuit includes resistance Rr and capacitor Cr.
Resistance Rr and capacitor Cr carries out Cycle by Cycle filtering to the node voltage LX of 1 power output of BUCK converter.Electricity
The DC voltage for holding Cr includes output voltage VO UT information.When Duty is logically high, power power PMOS conducting, power
When power NMOS is closed, the electric current of resistance Rr is approximately (VIN-VOUT)/Rr, is charged to capacitor Cr, on capacitor Cr voltage
It rises；When Duty is logic low, power power PMOS is closed, and when power power NMOS is connected, the electric current of resistance Rr is approximately
(0-VOUT)/Rr discharges to capacitor Cr, the decline of capacitor Cr voltage.
In this present embodiment, the coupled capacitor is connected with the filter circuit, output and the power stage output circuit
In the synchronous ramp voltage signal of inductive current；The coupled capacitor includes capacitor Cd and capacitor Cp.Capacitor Cp passes through coupling
Output voltage VO UT ripple is coupled to synchronous slope Vramp by capacitor Cd, and needed for ACOT is controlled and inductive current is just obtained
Synchronous ramp signal Vramp.
In this present embodiment, the feedback resistance is connected with voltage output end, exports feedback voltage signal.The feedback electricity
Resistance includes resistance R1 and R2.Resistance R1 and R2 form output voltage feedback, obtain output feedback voltage Vfb.Output voltage it is straight
Galvanic electricity pressure is determined by R1 and R2.
So the output voltage sampling in the present embodiment can be ACOT control with synchronous slope generating circuit 15
1 voltage close loop of BUCK converter improves loop stability, can also be when transient changing occurs for output voltage VO UT, quick coupling
Undershoot overshoot voltage is exported to synchronous slope Vramp, error amplifying element is skipped, directly acts on
Main comparator, it is corresponding to adjust loop pulse width logic Duty, realize quick transient response.
In this present embodiment, isolation resistance Rd is connected between the ramp voltage signal and the feedback voltage signal.
The series resistor Rd between synchronous slope Vramp and output feedback Vfb, as isolation, primarily to reducing output feedback Vfb
On ripple, realize preferably output DC voltage regulation.
The BUCK converter 1 of the present embodiment is worked by prototype test, the switching frequency of BUCK converter 1 in PWM mode
When can be very good to be locked in benchmark 2.5MHz.Meanwhile quickly (< 5us) for the transient response of load jump, output voltage
Fluctuation also very little.Test result shows that transient response is well many than the prior art.The BUCK converter 1 of design, it is defeated in width
Enter VIN=2.5V-6.0V, in the case where wide output VOUT=0.6V-1.5V, IOUT=0A-6A, frequency-locked loop is very stable, opens
It closes frequency and is also locked in reference clock 2.5MHz.
In conclusion the present invention, which passes through, introduces frequency locking control circuit, so that the BUCK converter based on ACOT framework is being protected
Hold traditional PWM control loop structure simply and quickly linear/load response advantage while, it is good to solve practical application
The switching frequency fluctuation problem of the middle wide output of wide input, also greatly improves the EMI characteristic of system；The present invention is by by frequency locking
It include the voltage of frequency error information in control, directly as the threshold value that adaptive turn-on time compares, with timing capacitor voltage
Compared with (being charged by the electric current directly proportional with VIN to it), turn-on time is determined.Therefore frequency-locked loop does not also additionally introduce electric current
Amplifier pole, so that the stability of frequency-locked loop is improved, design also becomes relatively easy.So effective gram of the present invention
It has taken various shortcoming in the prior art and has had high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of BUCK converter, which is characterized in that the BUCK converter includes: the frequency locking control electricity comprising BUCK converter
The adaptive turn-on time generation circuit on road, pulse width modulated comparator, error amplifier, output voltage sampling are produced with synchronous slope
Raw circuit, the RS triggering that input terminal is connected with the adaptive turn-on time generation circuit and the pulse width modulated comparator respectively
Device, the closed loop control logic being connected with the rest-set flip-flop output end, power switch driver circuit and including PMOS function
The power stage output circuit of rate switch and NMOS power switch；The non-inverting input terminal connection error of the pulse width modulated comparator is put
Big device, reverse input end connect output voltage sampling and synchronous slope generating circuit；Output voltage sampling with it is synchronous tiltedly
Slope generation circuit includes:
Filter circuit carries out Cycle by Cycle filtering to the node voltage of Buck inverter power output；
Coupled capacitor is connected with the filter circuit, exports synchronous with the inductive current in the power stage output circuit oblique
Slope voltage signal；
Feedback resistance is connected with voltage output end, exports feedback voltage signal.
2. BUCK converter according to claim 1, which is characterized in that the adaptive turn-on time generation circuit is also wrapped
It includes: the turn-on time comparator being connected with the frequency locking control circuit, timing capacitor and time switch；Wherein, the upper timing
The base stage of switch is connected with a NOT gate.
3. BUCK converter according to claim 1, which is characterized in that the ramp voltage signal and the feedback voltage
Isolation resistance is connected between signal.
4. BUCK converter according to claim 1, which is characterized in that the frequency locking control circuit includes:
Frequency and phase discrimination logic circuit generates tool according to the duty cycle signals of Buck converter and the frequency error signal of reference frequency
There are the first control logic signal and the second control logic signal of frequency error information；
Charge pump is connected with the frequency and phase discrimination logic circuit, respectively according to the first control logic signal and described second
The control of control logic signal is fanned out to being turned on and off for electric current and fan-in electric current, and exports the voltage comprising frequency error information and believe
Number to adaptive turn-on time generation circuit；
Current source is fanned out to electric current and the fan-in electric current described in generation.
5. BUCK converter according to claim 4, which is characterized in that the frequency and phase discrimination logic circuit includes:
First d type flip flop receives the duty cycle signals of Buck converter；
Second d type flip flop receives the frequency error signal of reference frequency；
Logic circuit, including first d type flip flop and second d type flip flop being carried out logic and operation and door, by institute
The output of the first d type flip flop is stated to carry out the first NOT gate of inverted running and transmit the output of second d type flip flop
Transmission gate.
6. BUCK converter according to claim 5, which is characterized in that two input terminals with door respectively with it is described
The end Q of first d type flip flop is connected with the end Q of second d type flip flop, the output end with door with respectively with the first D
The end R of trigger is connected with the end R of second d type flip flop.
7. BUCK converter according to claim 5 or 6, which is characterized in that the charge pump include with it is described first non-
Door and the second group of switch for being fanned out to first group of connected switch of electric current and being connected with the transmission gate and the fan-in electric current；It is described
The voltage letter of the output voltage signal comprising frequency error information is drawn between first group of switch and second group of switch
Number output end.
8. BUCK converter according to claim 7, which is characterized in that first group of switch includes concatenated first
PMOS switch and the second PMOS switch；Wherein, it first PMOS switch and first NOT gate and is fanned out to electric current and is connected, it is described
Second PMOS switch is connected by the second NOT gate with first NOT gate.
9. BUCK converter according to claim 7, which is characterized in that second group of switch includes concatenated first
NMOS switch and the second NMOS switch；Wherein, first NMOS switch is connected with the transmission gate and fan-in electric current, and described
Two NMOS switches are connected by third NOT gate with the transmission gate.
10. BUCK converter according to claim 7, which is characterized in that the charge pump further include: believe with the voltage
The connected low-pass filter circuit of number output end.
11. BUCK converter according to claim 10, which is characterized in that the low-pass filter circuit includes: including
First filter branch of one capacitor and the second filter branch including concatenated resistance and the second capacitor.
12. BUCK converter according to claim 4, which is characterized in that the current source includes:
Divider resistance is connected with input voltage, divides to input voltage；
Amplifier, non-inverting input terminal are connected with the divider resistance, and reverse input end is connected with a voltage regulation resistance；
PMOS current mirror and NMOS current mirror are connected to the output end of the amplifier by a switch, are obtained respectively by mirror image
Electric current and the fan-in electric current are fanned out to described.
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| CN201810073962.8A CN108282084B (en) | 2018-01-25 | 2018-01-25 | BUCK converter and its frequency locking control circuit |
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| CN201810073962.8A CN108282084B (en) | 2018-01-25 | 2018-01-25 | BUCK converter and its frequency locking control circuit |
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| CN110098720A (en) * | 2018-08-22 | 2019-08-06 | 上海权策微电子技术有限公司 | Reduce the circuit of total harmonic distortion and increase power factor |
| CN110250575A (en) * | 2019-06-06 | 2019-09-20 | 西安拓尔微电子有限责任公司 | It is a kind of to export the circuit and its implementation for indicating current rate by PWM |
| CN110149042B (en) * | 2019-06-14 | 2020-11-27 | 电子科技大学 | Power tube grid driving circuit with sectional driving function |
| CN110943601A (en) * | 2019-12-18 | 2020-03-31 | 西安航天民芯科技有限公司 | Constant frequency circuit for constant on-time control mode switching power supply |
| CN113241941B (en) * | 2020-12-31 | 2022-09-02 | 上海晶丰明源半导体股份有限公司 | Switching power supply control circuit, system and control method |
| CN112865530A (en) * | 2021-01-12 | 2021-05-28 | 南京理工大学 | Buck converter with quick dynamic response |
| CN112865534B (en) * | 2021-01-21 | 2022-06-07 | 西安电子科技大学 | Buck converter with self-adaptive on-time control |
| CN116667650B (en) * | 2023-04-18 | 2024-02-20 | 华南理工大学 | Single-inductor multi-level direct current converter based on self-adaptive slope calibration mode |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co.,Ltd. Address before: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: FUZHOU ROCKCHIP ELECTRONICS Co.,Ltd. |
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Application publication date: 20180713 Assignee: Shanghai hanmai Electronic Technology Co.,Ltd. Assignor: Ruixin Microelectronics Co.,Ltd. Contract record no.: X2023350000312 Denomination of invention: BUCK Converter and Its Frequency Locked Control Circuit Granted publication date: 20190531 License type: Common License Record date: 20230718 |