WO2020199804A1 - Switching power supply system employing hysteretic mode control - Google Patents

Switching power supply system employing hysteretic mode control Download PDF

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Publication number
WO2020199804A1
WO2020199804A1 PCT/CN2020/076936 CN2020076936W WO2020199804A1 WO 2020199804 A1 WO2020199804 A1 WO 2020199804A1 CN 2020076936 W CN2020076936 W CN 2020076936W WO 2020199804 A1 WO2020199804 A1 WO 2020199804A1
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Prior art keywords
circuit
hysteresis
signal
switch
control signal
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PCT/CN2020/076936
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French (fr)
Chinese (zh)
Inventor
马忠亮
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无锡职业技术学院
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Publication of WO2020199804A1 publication Critical patent/WO2020199804A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Definitions

  • the invention relates to the field of switching power supplies, in particular to a switching power supply system based on hysteresis mode control.
  • the digital logic IC When the digital logic IC is working, it needs the system front-end DC-DC switching power supply to supply it. As the semiconductor process enters the nano-era, the chip area of the digital logic IC is continuously reduced, the working voltage is continuously reduced, and the working clock frequency is continuously increased. Therefore, more and more stringent requirements are put forward for the DC-DC switching power supply of the front stage of the digital logic IC system.
  • the DC-DC switching power supply is required to have a smaller PCB area, higher switching frequency and conversion efficiency, and faster Transient response and lower output voltage ripple.
  • the switching power supply of hysteresis control mode is more and more commonly used in switching power supply products due to its simple compensation and high working frequency.
  • the proposed switching power supply system based on the hysteresis control mode has the method of forcibly injecting a sampling commutation point (SW) voltage into the system output voltage feedback FB node to form a triangular wave signal, and then making a hysteresis comparison with the reference voltage Vref, see patent number US6147478
  • SW sampling commutation point
  • Vref reference voltage feedback
  • the patent number US6147478 provides a method when the system is under heavy load due to the decrease of the pressure drop at the sampling commutation point, which leads to the inconsistent slope of the signal injected into the system under light and heavy loads, which causes the system operating frequency to vary with the load, and the system The output voltage ripple is still too large.
  • Another approach provided by the patent number US8866450B2 requires a separate transconductance amplifier in the system, and an RC network must be connected in parallel to both ends of the inductor, which increases the complexity of the system design.
  • the switching power supply system includes a series circuit composed of an upper arm MOS switch and a lower arm MOS switch. One end of the series circuit is connected to the system input end of the switching power supply system and the other end is grounded.
  • the upper arm MOS switch and The common end of the lower arm MOS switch is used as the sampling commutation point to connect to the output end of the switching power supply system through an inductor.
  • the output end of the system is also connected to the first resistor, the first capacitor, and the second capacitor.
  • the other end of the second capacitor is grounded.
  • a resistor is connected to the other end of the first capacitor and then grounded through a second resistor.
  • the common end of the first resistor and the second resistor is connected to the inverting input terminal of the error amplifier.
  • the non-inverting input terminal of the error amplifier inputs the reference signal.
  • the output terminal is connected to the hysteresis comparator circuit, the output terminal of the error amplifier is also connected to the compensation capacitor and the compensation resistor in turn, and then grounded.
  • the error amplifier generates an error signal according to the input signal and outputs it to the hysteresis comparator circuit;
  • the input terminal of the voltage sampling circuit obtains the sampling signal, and the output terminal is connected to the input terminal of the triangle wave generating circuit.
  • the voltage sampling circuit is used to generate a bias voltage according to the sampling signal and output it to the triangle wave generating circuit.
  • the sampling signal is a fixed signal or the sampling signal is a reaction sampling
  • the triangle wave generating circuit includes a series circuit composed of a first switch and a second switch. One end of the series circuit is connected to the working voltage and the other end is grounded. The first switch and the second switch are common The third resistor and the third capacitor are sequentially connected to the third resistor and the third capacitor.
  • the other end of the third capacitor is used as the input terminal of the triangle wave generating circuit to connect to the voltage sampling circuit, and the common terminal of the third resistor and the third capacitor is used as the output terminal of the triangle wave generating circuit to connect hysteresis Comparator circuit, the triangular wave generating circuit is used to generate a triangular wave signal according to the bias voltage and the control signal of the first switch and the control signal of the second switch and output it to the hysteresis comparator circuit; the output terminal of the hysteresis comparator circuit is connected to the logic control circuit At the input, the hysteresis comparator circuit is used to compare the error signal and the triangle wave signal according to the input first control signal to generate a modulated wave signal and output it to the logic control circuit.
  • the logic control circuit logically processes the modulated wave signal to generate the upper arm
  • the drive signal, the lower arm drive signal, the first control signal, the second control signal and the third control signal is opposite to the lower arm drive signal.
  • the first control signal, the second control signal and the third control signal are coupled to the upper arm drive signal.
  • the lower arm drive signal has the same frequency as the upper and lower arm drive signals
  • the upper arm drive signal is used to drive the upper arm MOS switch
  • the lower arm drive signal is used to drive the lower arm MOS switch
  • the first control signal is used as the control signal of the hysteresis comparator circuit
  • the second control signal is output to the triangle wave generating circuit as the control signal of the first switch
  • the third control signal is output to the triangle wave generating circuit as the control signal of the second switch.
  • the hysteresis comparator circuit includes a hysteresis generating circuit and a comparator, the input of the comparator is respectively connected to the output of the error amplifier and the output of the triangle wave generating circuit, and the output of the comparator is used as the hysteresis comparator circuit
  • the output terminal is connected to the logic control circuit, and the first control signal generated by the logic control circuit is output to the hysteresis generating circuit;
  • the hysteresis generating circuit is arranged at the output terminal of the error amplifier and generates a hysteresis signal to the error signal according to the first control signal, or the hysteresis generating circuit It is arranged at the output terminal of the triangle wave generating circuit and generates a hysteresis signal to the triangle wave signal according to the first control signal.
  • the further technical solution is that when the hysteresis generating circuit is arranged at the output terminal of the error amplifier, the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged at two ends of the compensation resistor. end;
  • the hysteresis generating circuit When the hysteresis generating circuit is arranged at the output terminal of the triangle wave generating circuit, the hysteresis generating circuit is arranged between the output terminal of the triangle wave generating circuit and the input terminal of the comparator.
  • the further technical solution is that when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged between the output terminal of the triangular wave generating circuit and the input terminal of the comparator,
  • the hysteresis generating circuit includes:
  • a first series circuit composed of a first current source, a first hysteresis switch, a second hysteresis switch, and a second current source
  • a first series circuit composed of a third current source, a second hysteresis switch, a first hysteresis switch, and a fourth current source
  • the positive poles of the first series circuit and the second series circuit are respectively connected to the working voltage, and the negative poles are respectively grounded.
  • One end of the hysteresis resistance is connected to the common end of the first and second hysteresis switches in the first series circuit.
  • the hysteresis resistance The other end of is connected to the common end of the first hysteresis switch and the second hysteresis switch in the second series circuit, and the common end of the first hysteresis switch and the second hysteresis switch in the first series circuit is used as the input end of the hysteresis generating circuit.
  • the output terminal of the amplifier or the triangular wave generating circuit, the common terminal of the first hysteresis switch and the second hysteresis switch in the second series circuit is connected to the comparator as the output terminal of the hysteresis generating circuit; the first hysteresis switch and the second hysteresis switch in the first series circuit
  • the first hysteresis switch in the two series circuits is controlled by the same control signal.
  • the second hysteresis switch in the first series circuit and the second hysteresis switch in the second series circuit are controlled by the same control signal.
  • the first hysteresis switch is controlled by the same control signal.
  • the signal and the control signal of the second hysteresis switch are both coupled to the first control signal and the two control signals are opposite.
  • the hysteresis generating circuit when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, the hysteresis generating circuit includes:
  • a series circuit composed of a current source, a second hysteresis switch, and a first hysteresis switch.
  • the positive pole of the series circuit is connected to the working voltage and the negative pole is grounded.
  • the common end of the second hysteresis switch and the first hysteresis switch is used to connect the compensation capacitor and the compensation resistor.
  • the control signal of the first hysteresis switch and the control signal of the second hysteresis switch are both coupled to the first control signal and the two control signals are opposite.
  • a further technical solution is that the input terminal of the voltage sampling circuit is connected to a fixed voltage, and the sampling signal obtained by the voltage sampling circuit is a fixed voltage; or the input terminal of the voltage sampling circuit is coupled to the sampling commutation point, and the voltage sampling circuit obtains
  • the sampling signal is the signal at the sampling commutation point; or, the input terminal of the voltage sampling circuit is connected to the logic control circuit, and the sampling signal obtained by the voltage sampling circuit includes the fourth control signal and the fifth control signal output by the logic control circuit.
  • the control signal and the fifth control signal are coupled to the upper and lower arm drive signals, and the fourth control signal and the fifth control signal are opposite.
  • the voltage sampling circuit when the input terminal of the voltage sampling circuit is directly coupled to the sampling commutation point, the voltage sampling circuit includes: an RC filter circuit composed of a filter resistor and a filter capacitor, and the input terminal of the RC filter circuit is used as the voltage sampling circuit The input terminal is coupled to the sampling commutation point, and the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through a buffer.
  • the voltage sampling circuit when the input terminal of the voltage sampling circuit is connected to the logic control circuit, the voltage sampling circuit includes:
  • a series circuit composed of the first sampling switch and the second sampling switch One end of the series circuit is connected to the working voltage and the other end is grounded.
  • the common end of the first sampling switch and the second sampling switch is connected to the RC filter circuit composed of a filter resistor and a filter capacitor.
  • Input terminal, the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer; the fourth control signal output by the logic control circuit is output to the voltage sampling circuit as the control signal of the first sampling switch, and the fifth control signal output by the logic control circuit The control signal is output to the voltage sampling circuit as a control signal of the second sampling switch.
  • the triangle wave generating circuit also includes a current generating circuit
  • the current generating circuit includes a first gain module, a second gain module, a divider and a voltage-current converter
  • the input terminal of the first gain module is connected to the system input terminal
  • the input terminal of the second gain module is connected to the system output terminal
  • the output terminal of the first gain module and the output terminal of the second gain module are respectively connected to the two input terminals of the divider
  • the output terminal of the divider is connected to the input of the voltage-current converter
  • the output terminal of the voltage-current converter is connected to the output terminal of the triangle wave generating circuit as the output terminal of the current generating circuit.
  • This application discloses a switching power supply system based on hysteresis mode control.
  • the hysteresis design exists in the rear stage of the error amplifier.
  • the output COMP is the sampling signal of VOUT and the amplified signal of the reference voltage, so the output
  • the working hysteresis of the signal feedback node FB is small, so that a small output signal ripple can be realized;
  • the triangular wave signal Ramp which is compared with the COMP output by the error amplifier, is generated by the triangular wave generating circuit.
  • the slope of the triangular wave signal Ramp is exchanged with the sample
  • the phase point SW voltage is basically irrelevant, so the operating frequency of the system has a very small relationship with the output current load. At the same time, the system also has a faster transient response speed, and the operating frequency changes little with the system input and system output.
  • FIG. 1 is a circuit structure diagram of a switching power supply system based on hysteresis mode control disclosed in the present application.
  • Figure 2 is a circuit diagram of a triangle wave generating circuit.
  • Figure 3 is another circuit diagram of the triangle wave generating circuit.
  • FIG. 4 is a circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
  • Fig. 5 is a circuit diagram of a hysteresis generating circuit in the circuit shown in Fig. 4.
  • Fig. 6 is an operating waveform diagram of the hysteresis generating circuit shown in Fig. 5.
  • FIG. 7 is another circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
  • Fig. 8 is a circuit diagram of a hysteresis generating circuit in the circuit shown in Fig. 7.
  • Fig. 9 is an operating waveform diagram of the hysteresis generating circuit shown in Fig. 8.
  • FIG. 10 is another circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
  • Fig. 11 is a specific circuit diagram when the voltage sampling circuit is directly coupled to the sampling commutation point.
  • FIG. 12 is a circuit configuration diagram when the voltage sampling circuit in FIG. 4 is changed to the configuration in which the logic control circuit is connected.
  • Figure 13 is a specific circuit diagram when the voltage sampling circuit is connected to the logic control circuit.
  • Fig. 14 is a working waveform diagram of the voltage sampling circuit shown in Fig. 13.
  • Figure 15 is a circuit diagram of a logic control circuit.
  • Fig. 16 is a working waveform diagram of the circuit structure shown in Fig. 4 in CCM mode.
  • Fig. 17 is a working waveform diagram of the circuit structure shown in Fig. 4 in DCM mode.
  • Fig. 18 is a working waveform diagram of the circuit structure shown in Fig. 10 in CCM mode.
  • the switching power supply system includes a series circuit composed of an upper arm MOS switch S1 and a lower arm MOS switch S2. One end of the series circuit is connected to the switching power supply system. The input terminal VIN of the system and the other terminal are grounded. The common terminal of the upper arm MOS switch S1 and the lower arm MOS switch S2 is used as the sampling commutation point SW to connect to the system output terminal VOUT of the switching power supply system through the inductor L. The output terminal VOUT of the system is also connected to the first resistor R1, the first capacitor C1 and the second capacitor C2 respectively. The other end of the second capacitor C2 is grounded.
  • the other end of the first resistor R1 and the first capacitor C1 is connected through the second resistor R2. Ground.
  • the common terminal of the first resistor R1 and the second resistor R2 is connected to the inverting input terminal of the error amplifier EA, and this node is the output signal feedback node FB.
  • the non-inverting input terminal of the error amplifier EA inputs the reference signal VREF
  • the output terminal of the error amplifier EA is connected to the hysteresis comparator circuit CMP
  • the output terminal of the error amplifier EA is connected to the compensation capacitor C C and the compensation resistor R C in turn and then grounded.
  • the error amplifier EA generates an error signal COMP according to the input VOUT feedback signal and the reference signal VREF and outputs it to the hysteresis comparator circuit CMP.
  • the input terminal of the voltage sampling circuit obtains the sampling signal Vpe, and the output terminal is connected to the input terminal of the triangle wave generating circuit.
  • the voltage sampling circuit is used to generate the bias voltage VDP according to the sampling signal Vpe and output it to the triangle wave generating circuit.
  • the triangle wave generating circuit is also connected to a logic control circuit.
  • the logic control circuit is used to output the second control signal Sense2 and the third control signal Sense3 to the triangle wave generating circuit.
  • the triangle wave generating circuit is used to generate the triangle wave according to the bias voltage VDP, the second control signal Sense2 and the third control signal.
  • the control signal Sense3 generates a triangular wave signal Ramp and outputs it to the hysteresis comparator circuit CMP.
  • the output terminal of the hysteresis comparator circuit CMP is connected to the input terminal of the logic control circuit.
  • the hysteresis comparator circuit CMP is also connected to the logic control circuit.
  • the logic control circuit is used to output the first control signal Sense1 to the hysteresis comparator circuit CMP.
  • the hysteresis comparator circuit CMP is used to perform hysteresis comparison between the error signal COMP and the triangular wave signal Ramp according to the input first control signal Sense1 to generate a modulated wave signal PWM and output it to the logic control circuit.
  • the logic control circuit includes a series of conventional logic devices.
  • the logic control circuit performs logic processing on the modulation wave signal PWM to generate the upper arm drive signal DRU, the lower arm drive signal DRL, the first control signal Sense1, the second control signal Sense2 and the third control
  • the signal Sense3, the upper arm drive signal DRU and the lower arm drive signal DRL are opposite, the first control signal Sense1, the second control signal Sense2 and the third control signal Sense3 are coupled to the upper and lower arm drive signals so as to be the same as the upper arm drive signal DRU and the lower arm drive signal DRL
  • the second control signal Sense2 and the third control signal Sense3 are two non-overlapping clock signals.
  • the coupling means that the upper arm drive signal DRU or the lower arm drive signal DRL is directly used, or the upper arm drive signal DRU or the lower arm drive signal DRL is obtained through a series of logic control, that is, the sampling of the upper arm drive signal DRU or the lower arm drive signal DRL is realized .
  • the first control signal Sense1 is output as the control signal of the hysteresis comparator circuit CMP to the hysteresis comparator circuit CMP
  • the second control signal Sense2 and the third control signal Sense3 are output as the control signals of the triangle wave generating circuit to the triangle wave generating circuit
  • the upper arm drive signal DRU It is used to drive the upper arm MOS switch S1
  • the lower arm drive signal DRL is used to drive the lower arm MOS switch S2, so as to achieve a stable voltage output at the system output terminal VOUT.
  • the triangle wave generating circuit includes a series circuit composed of a first switch S3 and a second switch S4. One end of the series circuit is connected to the working voltage VCC and the other end is grounded.
  • VCC can be a fixed voltage inside the system or the input voltage of the input terminal VIN of the system.
  • the common ends of the first switch S3 and the second switch S4 are sequentially connected to the third resistor R R and the third capacitor C R , and the other end of the third capacitor C R is used as the input end of the triangle wave generating circuit for connecting the voltage sampling circuit to obtain the bias Set the voltage VDP, the common end of the third resistor R R and the third capacitor C R is connected to the hysteresis comparator circuit CMP as the output end of the triangle wave generating circuit.
  • the second control signal Sense2 and the third control signal Sense3 as the control signal of the triangle wave generating circuit are specifically: the second control signal Sense2 is used as the control signal of the first switch S3, and the third control signal Sense3 is used as the control signal of the second switch S4.
  • FIG. 3 adds a current generating circuit to the output terminal on the basis of the circuit shown in FIG. 2.
  • the current generating circuit includes a first gain module k1, a second gain module k2, a divider DIVIDER, and a voltage-current converter V/R.
  • the input terminal of the first gain module k1 is connected to the system input terminal VIN, and the input terminal of the second gain module k2 Connect the system output terminal VOUT, the output terminal of the first gain module k1 and the output terminal of the second gain module k2 are respectively connected to the two input terminals of the divider DIVIDER, and the output terminal of the divider DIVIDER is connected to the input of the voltage-current converter V/R
  • the output terminal of the voltage-current converter V/R is connected to the output terminal of the triangle wave generating circuit as the output terminal of the current generating circuit.
  • the current generating circuit is controlled by the signals of the system input terminal VIN and the system output terminal VOUT.
  • the input signal VIN and the output signal VOUT are sampled and operated respectively through two gain modules, and then the relationship between VOUT divided by VIN is realized through the divider DIVIDER, and then by The voltage-current converter V/R converts into a current related to the voltage of the input signal VIN and the output signal VOUT to participate in the change of the rising and falling slopes of the triangular wave signal Ramp, so as to reduce the system operating frequency as the input signal VIN and the output signal VOUT change.
  • the purpose of the change in this way, the effect that its operating frequency is further independent of the input signal VIN and the output signal VOUT can be achieved.
  • the current involved in changing the triangular wave signal Ramp is inversely proportional to the input signal VIN and proportional to the output signal VOUT.
  • FIG 1 is the overall circuit architecture of the switching power supply system disclosed in this application. In actual implementation, each part of the circuit in the circuit architecture of Figure 1 has multiple implementation modes:
  • the hysteresis comparator circuit CMP mainly has two implementation methods: the first method is to directly use a commercially available hysteresis comparator, and the second method is to use a hysteresis generating circuit and a comparator.
  • the circuit structure of a commercially available hysteresis comparator is directly adopted as the circuit structure of FIG. 1, wherein the hysteresis comparator circuit CMP can select a suitable model according to actual needs, which will not be described in detail in this application. This application mainly explains the self-built situation.
  • the hysteresis comparator circuit CMP includes a hysteresis generating circuit and a comparator P
  • the input terminal of the comparator P is connected to the output terminal of the error amplifier EA and the output terminal of the triangle wave generating circuit respectively
  • the output terminal of the comparator P serves as the hysteresis comparator circuit
  • the output terminal is connected to the logic control circuit, and the first control signal Sense1 generated by the logic control circuit is output to the hysteresis generating circuit for control.
  • the hysteresis generating circuit There are mainly three specific settings for the hysteresis generating circuit:
  • the hysteresis generating circuit is set at the output of the error amplifier, and the hysteresis generating circuit is set between the output of the error amplifier EA and the input of the comparator P.
  • the hysteresis generating circuit Please refer to Figure 5 for the specific circuit diagram.
  • the hysteresis generating circuit includes a first series circuit composed of a first current source IBP1, a first hysteresis switch Sh1, a second hysteresis switch Sh2, and a second current source IBP2, and a third current source IBP3, a second hysteresis switch Sh2, and a first series circuit.
  • the positive poles of the first series circuit and the second series circuit are respectively connected to the working voltage VCC, and the negative poles are respectively grounded.
  • the working voltage VCC is defined above.
  • One end of the hysteresis resistor Rhyst is connected to the common end of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the first series circuit, and the other end of the hysteresis resistor Rhyst is connected to the first hysteresis switch Sh1 and the second hysteresis switch in the second series circuit.
  • the common terminal of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the first series circuit is used as the input terminal IN of the hysteresis generating circuit
  • the common terminal of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the second series circuit is used as the input terminal IN of the hysteresis generating circuit.
  • the first hysteresis switch Sh1 in the first series circuit and the first hysteresis switch Sh1 in the second series circuit are controlled by the same control signal.
  • the second hysteresis switch Sh2 in the first series circuit and the second hysteresis switch Sh2 in the second series circuit are controlled by the same control signal.
  • the hysteresis switch Sh2 is controlled by the same control signal.
  • the control signal of the first hysteresis switch Sh1 and the control signal of the second hysteresis switch Sh2 are both coupled to the first control signal Sense1 and the two control signals are opposite.
  • the coupling means that the two control signals are directly obtained by the first control signal Sense1 or generated by the first control signal Sense1 through logic control.
  • FIG. 5 takes the first control signal Sense1 as an example, and FIG. 5 only shows the pair Control diagram of two hysteresis switches.
  • the hysteresis generating circuit drives a current through a set of control signals related to the upper and lower arm drive signals to flow through a hysteresis resistor Rhyst to obtain a hysteresis coupling to the IN terminal signal.
  • the OUT end signal of the signal, Vhysteretic in Figure 6 represents the hysteresis signal coupled to the IN end signal.
  • the input terminal IN of the hysteresis generating circuit is connected to the output terminal of the error amplifier EA, and the output terminal OUT of the hysteresis generating circuit is connected to the input terminal of the comparator P.
  • the hysteresis generating circuit generates a hysteresis signal which is input at the IN terminal.
  • the lagging COMP signal obtained from the error signal COMP is output from the OUT terminal to the comparator P, and the comparator P compares the triangular wave signal Ramp with the lagging COMP to generate a modulation wave signal PWM.
  • the output end COMP is the amplified signal of the sampling signal of VOUT and the reference signal VREF, so the working hysteresis of the FB end is small, and the system output VOUT can achieve very Small ripples.
  • the hysteresis generating circuit is also set at the output end of the error amplifier EA, but the hysteresis generating circuit is set at both ends of the compensation resistor R C to hysteresize the COMP signal output by the error amplifier EA.
  • the circuit diagram of the hysteresis generating circuit is shown in Figure 8.
  • the hysteresis generating circuit includes a series circuit composed of a current source IBP, a second hysteresis switch Sh2, and a first hysteresis switch Sh1.
  • the positive pole of the series circuit is connected to the working voltage VCC and the negative pole is grounded.
  • the common end of the second hysteresis switch Sh2 and the first hysteresis switch Sh1 is used to connect the common end of the compensation capacitor C C and the compensation resistor R C.
  • the control signal of the first hysteresis switch Sh1 and the control signal of the second hysteresis switch Sh2 are both coupled to the first control signal Sense1 and the two control signals are opposite.
  • Figure 8 only shows two control signals A kind of hint.
  • a set of control signals related to the upper and lower arm drive signals drive a current to flow through the compensation resistor R C to achieve the effect of coupling a hysteresis signal Vhysteretic to the COMP signal .
  • the hysteresis generating circuit also generates a hysteresis signal on the error signal COMP, and the comparator P compares the triangular wave signal Ramp with the delayed COMP to generate the modulated wave signal PWM, but compared to the case 1, due to the hysteresis control
  • the compensation resistor R C is generated at both ends, the control is simpler, and the possibility of the COMP signal being interfered in the signal transmission process can be further reduced.
  • the hysteresis generating circuit is set at the output terminal of the triangle wave generating circuit, specifically between the output terminal of the triangle wave generating circuit and the input terminal of the comparator P,
  • the specific circuit diagram of the hysteresis generating circuit is the same as that of Figure 5
  • the waveform diagram is the same as that of Figure 6, except that the input terminal IN of the hysteresis generating circuit shown in Figure 5 is connected to the output terminal and output terminal OUT of the triangular wave generating circuit.
  • the hysteresis generating circuit Connect the input terminal of the comparator P, the hysteresis generating circuit generates a hysteresis signal on the triangular wave signal Ramp input at the IN terminal to obtain the lagging triangular wave signal Ramp from the OUT terminal to the comparator P, and the comparator P responds to the error signal COMP and the hysteresis
  • the triangular wave signal Ramp is compared to generate the modulated wave signal PWM.
  • the hysteresis control in this case is at the Ramp end, which can reduce the interference of the COMP signal during signal generation.
  • the sampling signal obtained by the voltage sampling circuit reflects the information characteristics of the signal at the sampling commutation point. There are two main cases:
  • the input terminal of the voltage sampling circuit is directly coupled to the sampling commutation point SW, as shown in Figures 4, 7 and 10, the sampling signal obtained by the voltage sampling circuit is the signal at the sampling commutation point SW.
  • the sampling circuit includes an RC filter circuit composed of a filter resistor RF and a filter capacitor CF.
  • the input of the RC filter circuit is directly coupled to the sampling commutation point as the input of the voltage sampling circuit.
  • SW the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer to output the bias voltage VDP.
  • the voltage sampling circuit generates the bias voltage VDP according to the signal at the sampling commutation point SW It has the same information characteristics as the signal at the sampling commutation point SW.
  • the slope of the triangular wave signal Ramp is basically independent of the size of the sampling commutation point SW, so the system operating frequency has a very small relationship with the output current load.
  • the input terminal of the voltage sampling circuit is not directly coupled to the sampling commutation point SW, but is connected to the logic control circuit.
  • the sampling signal obtained by the voltage sampling circuit includes the fourth control signal Sense4 and the fifth control signal Sense5 output by the logic control circuit.
  • the fourth control signal Sense4 and the fifth control signal Sense5 are both coupled to the upper and lower control signals.
  • the arm drive signal and the fourth control signal Sense4 are opposite to the fifth control signal Sense5.
  • the meaning of coupling is as above.
  • the sampling signal obtained by the voltage sampling circuit reflects the information characteristics of the signal at the sampling commutation point SW, and the voltage sampling
  • the bias voltage VDP generated by the circuit according to the sampling signal also has the same information characteristics as the signal at the sampling commutation point SW.
  • the voltage sampling circuit includes a series circuit composed of a first sampling switch S5 and a second sampling switch S6. One end of the series circuit is connected to the working voltage VCC and the other end is grounded.
  • the common terminal of the S5 switch and the second sampling switch S6 is connected to the input terminal of the RC filter circuit formed by the filter resistor RF and the filter capacitor CF, and the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer to output the bias voltage VDP.
  • the fourth control signal Sense4 output by the logic control circuit is output to the voltage sampling circuit as a control signal of the first sampling switch S5, and the fifth control signal Sense5 output by the logic control circuit is output to the voltage sampling circuit as a control signal of the second sampling switch S6.
  • the left part of the figure is the S5, S6 state and VA node voltage waveforms in CCM mode; the right part is the voltage waveform of the VA node in DEM mode.
  • the bias voltage VDP entering the triangle wave generating circuit is completely independent of the signal size at the sampling commutation point SW, so the system operating frequency is completely independent of the output current load.
  • the sampling signal obtained by the voltage sampling circuit is a fixed signal.
  • the input terminal of the voltage sampling circuit is directly connected to a fixed voltage, and the sampling signal obtained by the voltage sampling circuit is a fixed voltage, and the fixed voltage is internally buffered. After the device, the bias voltage VDP is output from the output terminal. This application will not show the circuit diagram of the voltage sampling circuit in this case.
  • the logic control circuit includes various conventional logic devices, so that the input modulation wave signal PWM is logically processed to generate the required driving and control signals.
  • the circuit construction of the specific logic control circuit can be based on The actual situation is self-configured.
  • the logic control circuit outputs the upper arm drive signal DRU, the lower arm drive signal DRL and five control signals Sense1 to Sense5 as an example, and a possible circuit structure of the logic control circuit is shown in Figure 15. As shown, Figure 15 is for reference only and is not used to limit the logic control circuit.
  • FIG. 4 and FIG. 10 are two typical circuit structures to show the working process of the switching power supply system disclosed in this application:
  • the switching power supply system adopts the circuit structure shown in Figure 4, the hysteresis generation circuit is set between the error amplifier and the comparator to perform hysteresis control on the COMP signal, and the voltage sampling circuit is directly coupled to SW, then the switching power supply system is in CCM mode (Continuous mode) Please refer to Figure 16 for the working waveform diagram.
  • the hysteresis generating circuit When the upper arm MOS switch S1 is turned on and the lower arm MOS switch S2 is turned off, the hysteresis generating circuit generates a hysteresis signal Vhysteretic on the error signal COMP generated by the error amplifier to obtain the hysteresis. After the error signal, shown as COMP2 in Figure 16, the triangular wave signal Ramp voltage starts to rise linearly.
  • the Ramp voltage rises to equal to COMP2 When the Ramp voltage rises to equal to COMP2, the upper arm MOS switch S1 is turned off, and the lower arm MOS switch S2 is turned on. At this time, the COMP2 signal jumps a hysteresis Vhysteretic, and the Ramp signal linearly drops; when the Ramp signal drops to COMP2 again, The lower arm S2 is turned off and the upper arm S1 is turned on again. At this time, the COMP2 signal jumps by a hysteresis, the Ramp signal rises linearly again until the Ramp signal is equal to the COMP2 signal again, the upper arm MOS switch S1 is turned off, the lower arm MOS switch S2 is turned on, and the cycle repeats .
  • the operating frequency of the system in CCM mode is:
  • FIG. 17 Please refer to Figure 17 for the operating waveform of the switching power supply system in DCM mode (intermittent mode).
  • the lower arm MOS switch S2 When the system enters DCM, the lower arm MOS switch S2 is turned off. At this time, the upper and lower arm MOS switches are both in the off state, the SW voltage stabilizes at the output voltage VOUT value after oscillation, and the Ramp signal terminates the linear speed drop during the on-time of the lower arm MOS switch S2. Since both the upper and lower arm MOS switches are turned off, the system output voltage VOUT decreases after being consumed by the load, so that the output voltage COMP of the error amplifier EA increases.
  • the switching power supply system adopts the circuit structure shown in Figure 10
  • the hysteresis generating circuit is set between the triangle wave generating circuit and the comparator to perform hysteresis control on the Ramp signal, and the voltage sampling circuit is directly coupled to SW, then the switching power supply system is in CCM
  • Figure 18 for the working waveform diagram in the continuous mode.
  • the Ramp signal jumps up by a hysteresis amount Vhysteretic, and then the Ramp signal begins to linearly decrease; when the Ramp signal drops to the COMP signal again, the lower arm MOS switch S2 is turned off , The upper arm MOS switch S1 is turned on again.
  • the Ramp signal first jumps by a hysteresis amount Vhysteretic, and the Ramp signal rises linearly again until the Ramp signal is equal to the COMP signal again.
  • the upper arm MOS switch S1 is turned off, and the lower arm MOS switch S2 is turned on, and the cycle starts again. .

Abstract

The present application relates to the field of switching power supply, and discloses a switching power supply system employing hysteretic mode control. In the switching power supply system, an error amplifier has a hysteretic design at a later stage thereof, and outputs COMP, which is an amplified signal obtained from a sampling signal of VOUT and a reference voltage, such that an output signal feedback node FB has a reduced amount of operating hysteresis, thereby achieving small output signal ripples. Moreover, a triangular wave signal Ramp is generated by a triangular wave generation circuit, and undergoes a hysteretic comparison with the COMP output by the error amplifier. A slope of the triangular wave signal Ramp is basically unrelated to the voltage at a sampling commutation point SW, such that the operating frequency of the system is mostly unrelated to output current load. The system also has fast transient response speed, and the operating frequency thereof is less affected by system inputs and outputs.

Description

一种基于迟滞模式控制的开关电源系统A switching power supply system based on hysteresis mode control 技术领域Technical field
本发明涉及开关电源领域,尤其是一种基于迟滞模式控制的开关电源系统。The invention relates to the field of switching power supplies, in particular to a switching power supply system based on hysteresis mode control.
背景技术Background technique
数字逻辑IC在工作时,需要系统前级DC-DC开关电源为其供电,随着半导体工艺制程进入纳米时代,数字逻辑IC的芯片面积不断减小、工作电压不断降低、工作时钟频率不断升高,因此对数字逻辑IC系统前级的DC-DC开关电源也提出了越来越严格的要求,需要DC-DC开关电源具有较小的PCB面积、更高的开关频率和转换效率、更快的瞬态响应以及更低的输出电压纹波。When the digital logic IC is working, it needs the system front-end DC-DC switching power supply to supply it. As the semiconductor process enters the nano-era, the chip area of the digital logic IC is continuously reduced, the working voltage is continuously reduced, and the working clock frequency is continuously increased. Therefore, more and more stringent requirements are put forward for the DC-DC switching power supply of the front stage of the digital logic IC system. The DC-DC switching power supply is required to have a smaller PCB area, higher switching frequency and conversion efficiency, and faster Transient response and lower output voltage ripple.
迟滞控制模式的开关电源由于其补偿简单、工作频率较高的特点而被越来越普遍的应用至开关电源产品中。已经提出的基于迟滞控制模式的开关电源系统有在系统输出电压反馈FB节点强行注入一个采样换相点(SW)电压形成三角波信号,再与参考电压Vref做迟滞比较的方式,参见专利号为US6147478的专利的做法,但这种做法在系统处于重载下由于采样换相点压降的降低导致系统在轻重载下注入信号的斜率不一致,从而导致系统工作频率随负载轻重而变化,且系统的输出电压纹波还是偏大。也有一种做法是通过RC网络采样电感电流纹波信息构成三角波信号,再与反馈电压FB经误差放大器EA后的COMP信号做迟滞比较,参见专利号为US8866450B2的专利的做法,但是这种做法在系统中需要有一个单独的跨导放大器,且必须有RC网络并联于电感两端,增加了系统设计的复杂性。The switching power supply of hysteresis control mode is more and more commonly used in switching power supply products due to its simple compensation and high working frequency. The proposed switching power supply system based on the hysteresis control mode has the method of forcibly injecting a sampling commutation point (SW) voltage into the system output voltage feedback FB node to form a triangular wave signal, and then making a hysteresis comparison with the reference voltage Vref, see patent number US6147478 However, when the system is under heavy load, the pressure drop at the sampling commutation point causes the system to have inconsistent slopes of the injected signal under light and heavy loads, resulting in the system operating frequency changing with the load, and the system The output voltage ripple is still too large. There is also a method of sampling the inductor current ripple information through the RC network to form a triangular wave signal, and then compare the hysteresis with the COMP signal of the feedback voltage FB after the error amplifier EA. Refer to the patent number US8866450B2, but this method is in A separate transconductance amplifier is required in the system, and an RC network must be connected in parallel to both ends of the inductor, which increases the complexity of the system design.
发明概述Summary of the invention
技术问题technical problem
专利号为US6147478提供的一种做法在系统处于重载下由于采样换相点压降的降低导致系统在轻重载下注入信号的斜率不一致,从而导致系统工作频率随负载轻重而变化,且系统的输出电压纹波还是偏大。专利号为US8866450B2提供的另一种做法在系统中需要有一个单独的跨导放大器,且必须有RC网络并联于电 感两端,增加了系统设计的复杂性。The patent number US6147478 provides a method when the system is under heavy load due to the decrease of the pressure drop at the sampling commutation point, which leads to the inconsistent slope of the signal injected into the system under light and heavy loads, which causes the system operating frequency to vary with the load, and the system The output voltage ripple is still too large. Another approach provided by the patent number US8866450B2 requires a separate transconductance amplifier in the system, and an RC network must be connected in parallel to both ends of the inductor, which increases the complexity of the system design.
问题的解决方案The solution to the problem
技术解决方案Technical solutions
一种基于迟滞模式控制的开关电源系统,该开关电源系统包括上臂MOS开关和下臂MOS开关构成的串联电路,串联电路的一端连接开关电源系统的系统输入端、另一端接地,上臂MOS开关和下臂MOS开关的公共端作为采样换相点通过电感连接开关电源系统的系统输出端,系统输出端还分别连接第一电阻、第一电容和第二电容,第二电容的另一端接地,第一电阻和第一电容的另一端相连后通过第二电阻接地,第一电阻与第二电阻的公共端连接至误差放大器的反相输入端,误差放大器的同相输入端输入基准信号,误差放大器的输出端连接迟滞比较器电路,误差放大器的输出端还依次连接补偿电容和补偿电阻后接地,误差放大器根据输入的信号产生误差信号并输出给迟滞比较器电路;A switching power supply system based on hysteresis mode control. The switching power supply system includes a series circuit composed of an upper arm MOS switch and a lower arm MOS switch. One end of the series circuit is connected to the system input end of the switching power supply system and the other end is grounded. The upper arm MOS switch and The common end of the lower arm MOS switch is used as the sampling commutation point to connect to the output end of the switching power supply system through an inductor. The output end of the system is also connected to the first resistor, the first capacitor, and the second capacitor. The other end of the second capacitor is grounded. A resistor is connected to the other end of the first capacitor and then grounded through a second resistor. The common end of the first resistor and the second resistor is connected to the inverting input terminal of the error amplifier. The non-inverting input terminal of the error amplifier inputs the reference signal. The output terminal is connected to the hysteresis comparator circuit, the output terminal of the error amplifier is also connected to the compensation capacitor and the compensation resistor in turn, and then grounded. The error amplifier generates an error signal according to the input signal and outputs it to the hysteresis comparator circuit;
电压采样电路的输入端获取采样信号、输出端连接三角波产生电路的输入端,电压采样电路用于根据采样信号生成偏置电压并输出给三角波产生电路,采样信号为固定信号或采样信号是反应采样换相点处信号的信息特征的可变信号;三角波产生电路包括第一开关和第二开关构成的串联电路,串联电路的一端连接工作电压、另一端接地,第一开关和第二开关的公共端依次连接第三电阻和第三电容,第三电容的另一端作为三角波产生电路的输入端用于连接电压采样电路,第三电阻和第三电容的公共端作为三角波产生电路的输出端连接迟滞比较器电路,三角波产生电路用于根据偏置电压以及第一开关的控制信号和第二开关的控制信号产生三角波信号并输出给迟滞比较器电路;迟滞比较器电路的输出端连接逻辑控制电路的输入端,迟滞比较器电路用于根据输入的第一控制信号对误差信号和三角波信号进行迟滞比较后产生调制波信号并输出给逻辑控制电路,逻辑控制电路对调制波信号进行逻辑处理后产生上臂驱动信号、下臂驱动信号、第一控制信号、第二控制信号和第三控制信号,上臂驱动信号和下臂驱动信号相反,第一控制信号、第二控制信号和第三控制信号耦合于上、下臂驱动信号并与上、下臂驱动信号同频率,上臂驱动信号用于驱动上臂MOS开关,下臂驱动信号用于驱动下臂MOS开关,第一控制信号作为迟滞比较器电路 的控制信号输出给迟滞比较器电路,第二控制信号作为第一开关的控制信号输出给三角波产生电路,第三控制信号作为第二开关的控制信号输出给三角波产生电路。The input terminal of the voltage sampling circuit obtains the sampling signal, and the output terminal is connected to the input terminal of the triangle wave generating circuit. The voltage sampling circuit is used to generate a bias voltage according to the sampling signal and output it to the triangle wave generating circuit. The sampling signal is a fixed signal or the sampling signal is a reaction sampling The variable signal of the information characteristic of the signal at the commutation point; the triangle wave generating circuit includes a series circuit composed of a first switch and a second switch. One end of the series circuit is connected to the working voltage and the other end is grounded. The first switch and the second switch are common The third resistor and the third capacitor are sequentially connected to the third resistor and the third capacitor. The other end of the third capacitor is used as the input terminal of the triangle wave generating circuit to connect to the voltage sampling circuit, and the common terminal of the third resistor and the third capacitor is used as the output terminal of the triangle wave generating circuit to connect hysteresis Comparator circuit, the triangular wave generating circuit is used to generate a triangular wave signal according to the bias voltage and the control signal of the first switch and the control signal of the second switch and output it to the hysteresis comparator circuit; the output terminal of the hysteresis comparator circuit is connected to the logic control circuit At the input, the hysteresis comparator circuit is used to compare the error signal and the triangle wave signal according to the input first control signal to generate a modulated wave signal and output it to the logic control circuit. The logic control circuit logically processes the modulated wave signal to generate the upper arm The drive signal, the lower arm drive signal, the first control signal, the second control signal and the third control signal. The upper arm drive signal is opposite to the lower arm drive signal. The first control signal, the second control signal and the third control signal are coupled to the upper arm drive signal. , The lower arm drive signal has the same frequency as the upper and lower arm drive signals, the upper arm drive signal is used to drive the upper arm MOS switch, the lower arm drive signal is used to drive the lower arm MOS switch, and the first control signal is used as the control signal of the hysteresis comparator circuit Output to the hysteresis comparator circuit, the second control signal is output to the triangle wave generating circuit as the control signal of the first switch, and the third control signal is output to the triangle wave generating circuit as the control signal of the second switch.
其进一步的技术方案为,迟滞比较器电路包括迟滞产生电路和比较器,比较器的输入端分别连接误差放大器的输出端和三角波产生电路的输出端,比较器的输出端作为迟滞比较器电路的输出端连接逻辑控制电路,逻辑控制电路产生的第一控制信号输出给迟滞产生电路;迟滞产生电路设置在误差放大器的输出端并根据第一控制信号产生迟滞信号于误差信号,或者,迟滞产生电路设置在三角波产生电路的输出端并根据第一控制信号产生迟滞信号于三角波信号。A further technical solution is that the hysteresis comparator circuit includes a hysteresis generating circuit and a comparator, the input of the comparator is respectively connected to the output of the error amplifier and the output of the triangle wave generating circuit, and the output of the comparator is used as the hysteresis comparator circuit The output terminal is connected to the logic control circuit, and the first control signal generated by the logic control circuit is output to the hysteresis generating circuit; the hysteresis generating circuit is arranged at the output terminal of the error amplifier and generates a hysteresis signal to the error signal according to the first control signal, or the hysteresis generating circuit It is arranged at the output terminal of the triangle wave generating circuit and generates a hysteresis signal to the triangle wave signal according to the first control signal.
其进一步的技术方案为,当迟滞产生电路设置在误差放大器的输出端时,迟滞产生电路设置在误差放大器的输出端与比较器的输入端之间,或者,迟滞产生电路设置在补偿电阻的两端;The further technical solution is that when the hysteresis generating circuit is arranged at the output terminal of the error amplifier, the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged at two ends of the compensation resistor. end;
当迟滞产生电路设置在三角波产生电路的输出端时,迟滞产生电路设置在三角波产生电路的输出端与比较器的输入端之间。When the hysteresis generating circuit is arranged at the output terminal of the triangle wave generating circuit, the hysteresis generating circuit is arranged between the output terminal of the triangle wave generating circuit and the input terminal of the comparator.
其进一步的技术方案为,当迟滞产生电路设置在误差放大器的输出端与比较器的输入端之间,或者,迟滞产生电路设置在三角波产生电路的输出端与比较器的输入端之间时,迟滞产生电路包括:The further technical solution is that when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged between the output terminal of the triangular wave generating circuit and the input terminal of the comparator, The hysteresis generating circuit includes:
第一电流源、第一迟滞开关、第二迟滞开关和第二电流源构成的第一串联电路,以及,第三电流源、第二迟滞开关、第一迟滞开关和第四电流源构成的第二串联电路,第一串联电路和第二串联电路的正极分别连接工作电压、负极分别接地,迟滞电阻的一端连接第一串联电路中的第一迟滞开关和第二迟滞开关的公共端,迟滞电阻的另一端连接第二串联电路中的第一迟滞开关和第二迟滞开关的公共端,第一串联电路中的第一迟滞开关和第二迟滞开关的公共端作为迟滞产生电路的输入端连接误差放大器或三角波产生电路的输出端,第二串联电路中的第一迟滞开关和第二迟滞开关的公共端作为迟滞产生电路的输出端连接比较器;第一串联电路中的第一迟滞开关和第二串联电路中的第一迟滞开关由同一个控制信号控制,第一串联电路中的第二迟滞开关和第二串联电路中的第二迟滞开关由同一个控制信号控制,第一迟滞开关的控制信号和第二迟滞开关 的控制信号均耦合于第一控制信号且两个控制信号相反。A first series circuit composed of a first current source, a first hysteresis switch, a second hysteresis switch, and a second current source, and a first series circuit composed of a third current source, a second hysteresis switch, a first hysteresis switch, and a fourth current source Two series circuits. The positive poles of the first series circuit and the second series circuit are respectively connected to the working voltage, and the negative poles are respectively grounded. One end of the hysteresis resistance is connected to the common end of the first and second hysteresis switches in the first series circuit. The hysteresis resistance The other end of is connected to the common end of the first hysteresis switch and the second hysteresis switch in the second series circuit, and the common end of the first hysteresis switch and the second hysteresis switch in the first series circuit is used as the input end of the hysteresis generating circuit. Connection error The output terminal of the amplifier or the triangular wave generating circuit, the common terminal of the first hysteresis switch and the second hysteresis switch in the second series circuit is connected to the comparator as the output terminal of the hysteresis generating circuit; the first hysteresis switch and the second hysteresis switch in the first series circuit The first hysteresis switch in the two series circuits is controlled by the same control signal. The second hysteresis switch in the first series circuit and the second hysteresis switch in the second series circuit are controlled by the same control signal. The first hysteresis switch is controlled by the same control signal. The signal and the control signal of the second hysteresis switch are both coupled to the first control signal and the two control signals are opposite.
其进一步的技术方案为,当迟滞产生电路设置在误差放大器的输出端与比较器的输入端之间时,迟滞产生电路包括:A further technical solution is that when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, the hysteresis generating circuit includes:
电流源、第二迟滞开关和第一迟滞开关构成的串联电路,串联电路的正极连接工作电压、负极接地,第二迟滞开关和第一迟滞开关的公共端用于连接补偿电容和补偿电阻的公共端,第一迟滞开关的控制信号和第二迟滞开关的控制信号均耦合于第一控制信号且两个控制信号相反。A series circuit composed of a current source, a second hysteresis switch, and a first hysteresis switch. The positive pole of the series circuit is connected to the working voltage and the negative pole is grounded. The common end of the second hysteresis switch and the first hysteresis switch is used to connect the compensation capacitor and the compensation resistor. At the end, the control signal of the first hysteresis switch and the control signal of the second hysteresis switch are both coupled to the first control signal and the two control signals are opposite.
其进一步的技术方案为,电压采样电路的输入端连接固定电压,电压采样电路获取到的采样信号为固定电压;或者,电压采样电路的输入端耦接采样换相点,电压采样电路获取到的采样信号为采样换相点处的信号;或者,电压采样电路的输入端连接逻辑控制电路,电压采样电路获取到的采样信号包括逻辑控制电路输出的第四控制信号和第五控制信号,第四控制信号和第五控制信号耦合于上、下臂驱动信号且第四控制信号和第五控制信号相反。A further technical solution is that the input terminal of the voltage sampling circuit is connected to a fixed voltage, and the sampling signal obtained by the voltage sampling circuit is a fixed voltage; or the input terminal of the voltage sampling circuit is coupled to the sampling commutation point, and the voltage sampling circuit obtains The sampling signal is the signal at the sampling commutation point; or, the input terminal of the voltage sampling circuit is connected to the logic control circuit, and the sampling signal obtained by the voltage sampling circuit includes the fourth control signal and the fifth control signal output by the logic control circuit. The control signal and the fifth control signal are coupled to the upper and lower arm drive signals, and the fourth control signal and the fifth control signal are opposite.
其进一步的技术方案为,当电压采样电路的输入端直接耦接采样换相点时,电压采样电路包括:滤波电阻和滤波电容构成的RC滤波电路,RC滤波电路的输入端作为电压采样电路的输入端耦接采样换相点,RC滤波电路的输出端通过缓冲器连接电压采样电路的输出端。The further technical solution is that when the input terminal of the voltage sampling circuit is directly coupled to the sampling commutation point, the voltage sampling circuit includes: an RC filter circuit composed of a filter resistor and a filter capacitor, and the input terminal of the RC filter circuit is used as the voltage sampling circuit The input terminal is coupled to the sampling commutation point, and the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through a buffer.
其进一步的技术方案为,当电压采样电路的输入端连接逻辑控制电路时,电压采样电路包括:A further technical solution is that when the input terminal of the voltage sampling circuit is connected to the logic control circuit, the voltage sampling circuit includes:
第一采样开关和第二采样开关构成的串联电路,串联电路的一端连接工作电压、另一端接地,第一采样开关和第二采样开关的公共端连接滤波电阻和滤波电容构成的RC滤波电路的输入端,RC滤波电路的输出端通过缓冲器连接电压采样电路的输出端;逻辑控制电路输出的第四控制信号作为第一采样开关的控制信号输出给电压采样电路,逻辑控制电路输出的第五控制信号作为第二采样开关的控制信号输出给电压采样电路。A series circuit composed of the first sampling switch and the second sampling switch. One end of the series circuit is connected to the working voltage and the other end is grounded. The common end of the first sampling switch and the second sampling switch is connected to the RC filter circuit composed of a filter resistor and a filter capacitor. Input terminal, the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer; the fourth control signal output by the logic control circuit is output to the voltage sampling circuit as the control signal of the first sampling switch, and the fifth control signal output by the logic control circuit The control signal is output to the voltage sampling circuit as a control signal of the second sampling switch.
其进一步的技术方案为,三角波产生电路中还包括电流产生电路,电流产生电路包括第一增益模块、第二增益模块、除法器和电压电流转换器,第一增益模块的输入端连接系统输入端,第二增益模块的输入端连接系统输出端,第一增 益模块的输出端和第二增益模块的输出端分别连接除法器的两个输入端,除法器的输出端连接电压电流转换器的输入端,电压电流转换器的输出端作为电流产生电路的输出端连接三角波产生电路的输出端。A further technical solution is that the triangle wave generating circuit also includes a current generating circuit, the current generating circuit includes a first gain module, a second gain module, a divider and a voltage-current converter, and the input terminal of the first gain module is connected to the system input terminal , The input terminal of the second gain module is connected to the system output terminal, the output terminal of the first gain module and the output terminal of the second gain module are respectively connected to the two input terminals of the divider, and the output terminal of the divider is connected to the input of the voltage-current converter The output terminal of the voltage-current converter is connected to the output terminal of the triangle wave generating circuit as the output terminal of the current generating circuit.
发明的有益效果The beneficial effects of the invention
有益效果Beneficial effect
本申请公开了一种基于迟滞模式控制的开关电源系统,在该开关电源系统中,迟滞的设计存在于误差放大器的后级,其输出COMP为VOUT的采样信号于基准电压的放大信号,故输出信号反馈节点FB端的工作迟滞量较小,从而可以实现很小的输出信号纹波;同时与误差放大器输出的COMP进行迟滞比较的三角波信号Ramp由三角波产生电路,该三角波信号Ramp的斜率与采样换相点SW电压基本无关,因此系统的工作频率与输出电流负载关系很小,同时该系统还具有较快的瞬态响应速度,工作频率随系统输入和系统输出的变化也较小。This application discloses a switching power supply system based on hysteresis mode control. In the switching power supply system, the hysteresis design exists in the rear stage of the error amplifier. The output COMP is the sampling signal of VOUT and the amplified signal of the reference voltage, so the output The working hysteresis of the signal feedback node FB is small, so that a small output signal ripple can be realized; at the same time, the triangular wave signal Ramp, which is compared with the COMP output by the error amplifier, is generated by the triangular wave generating circuit. The slope of the triangular wave signal Ramp is exchanged with the sample The phase point SW voltage is basically irrelevant, so the operating frequency of the system has a very small relationship with the output current load. At the same time, the system also has a faster transient response speed, and the operating frequency changes little with the system input and system output.
对附图的简要说明Brief description of the drawings
附图说明Description of the drawings
图1是本申请公开的基于迟滞模式控制的开关电源系统的电路结构图。FIG. 1 is a circuit structure diagram of a switching power supply system based on hysteresis mode control disclosed in the present application.
图2是三角波产生电路的一种电路图。Figure 2 is a circuit diagram of a triangle wave generating circuit.
图3是三角波产生电路的另一种电路图。Figure 3 is another circuit diagram of the triangle wave generating circuit.
图4是图1中的迟滞比较器电路由迟滞产生电路和比较器构成时的一种电路结构图。FIG. 4 is a circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
图5是图4所示的电路中的迟滞产生电路的电路图。Fig. 5 is a circuit diagram of a hysteresis generating circuit in the circuit shown in Fig. 4.
图6是图5所示的迟滞产生电路的工作波形图。Fig. 6 is an operating waveform diagram of the hysteresis generating circuit shown in Fig. 5.
图7是图1中的迟滞比较器电路由迟滞产生电路和比较器构成时的另一种电路结构图。FIG. 7 is another circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
图8是图7所示的电路中的迟滞产生电路的电路图。Fig. 8 is a circuit diagram of a hysteresis generating circuit in the circuit shown in Fig. 7.
图9是图8所示的迟滞产生电路的工作波形图。Fig. 9 is an operating waveform diagram of the hysteresis generating circuit shown in Fig. 8.
图10是图1中的迟滞比较器电路由迟滞产生电路和比较器构成时的又一种电路结构图。FIG. 10 is another circuit configuration diagram when the hysteresis comparator circuit in FIG. 1 is composed of a hysteresis generating circuit and a comparator.
图11是电压采样电路直接耦接采样换相点时的具体电路图。Fig. 11 is a specific circuit diagram when the voltage sampling circuit is directly coupled to the sampling commutation point.
图12是图4改用电压采样电路连接逻辑控制电路的结构时的电路结构图。FIG. 12 is a circuit configuration diagram when the voltage sampling circuit in FIG. 4 is changed to the configuration in which the logic control circuit is connected.
图13是电压采样电路连接逻辑控制电路时的具体电路图。Figure 13 is a specific circuit diagram when the voltage sampling circuit is connected to the logic control circuit.
图14是图13所示的电压采样电路的工作波形图。Fig. 14 is a working waveform diagram of the voltage sampling circuit shown in Fig. 13.
图15是逻辑控制电路的一种电路图。Figure 15 is a circuit diagram of a logic control circuit.
图16是图4所示的电路结构在CCM模式下的工作波形图。Fig. 16 is a working waveform diagram of the circuit structure shown in Fig. 4 in CCM mode.
图17是图4所示的电路结构在DCM模式下的工作波形图。Fig. 17 is a working waveform diagram of the circuit structure shown in Fig. 4 in DCM mode.
图18是图10所示的电路结构在CCM模式下的工作波形图。Fig. 18 is a working waveform diagram of the circuit structure shown in Fig. 10 in CCM mode.
发明实施例Invention embodiment
本发明的实施方式Embodiments of the invention
下面结合附图对本发明的具体实施方式做进一步说明。The specific embodiments of the present invention will be further described below in conjunction with the drawings.
本申请公开了一种基于迟滞模式控制的开关电源系统,请参考图1,该开关电源系统包括上臂MOS开关S1和下臂MOS开关S2构成的串联电路,该串联电路的一端连接开关电源系统的系统输入端VIN、另一端接地。上臂MOS开关S1和下臂MOS开关S2的公共端作为采样换相点SW通过电感L连接开关电源系统的系统输出端VOUT。系统输出端VOUT还分别连接第一电阻R1、第一电容C1和第二电容C2,第二电容C2的另一端接地,第一电阻R1和第一电容C1的另一端相连后通过第二电阻R2接地。第一电阻R1与第二电阻R2的公共端连接至误差放大器EA的反相输入端,该节点即为输出信号反馈节点FB。误差放大器EA的同相输入端输入基准信号VREF,误差放大器EA的输出端连接迟滞比较器电路CMP,误差放大器EA的输出端还依次连接补偿电容C C和补偿电阻R C后接地。误差放大器EA根据输入的VOUT反馈信号与基准信号VREF产生误差信号COMP并输出给迟滞比较器电路CMP。 This application discloses a switching power supply system based on hysteresis mode control. Please refer to Figure 1. The switching power supply system includes a series circuit composed of an upper arm MOS switch S1 and a lower arm MOS switch S2. One end of the series circuit is connected to the switching power supply system. The input terminal VIN of the system and the other terminal are grounded. The common terminal of the upper arm MOS switch S1 and the lower arm MOS switch S2 is used as the sampling commutation point SW to connect to the system output terminal VOUT of the switching power supply system through the inductor L. The output terminal VOUT of the system is also connected to the first resistor R1, the first capacitor C1 and the second capacitor C2 respectively. The other end of the second capacitor C2 is grounded. The other end of the first resistor R1 and the first capacitor C1 is connected through the second resistor R2. Ground. The common terminal of the first resistor R1 and the second resistor R2 is connected to the inverting input terminal of the error amplifier EA, and this node is the output signal feedback node FB. The non-inverting input terminal of the error amplifier EA inputs the reference signal VREF, the output terminal of the error amplifier EA is connected to the hysteresis comparator circuit CMP, and the output terminal of the error amplifier EA is connected to the compensation capacitor C C and the compensation resistor R C in turn and then grounded. The error amplifier EA generates an error signal COMP according to the input VOUT feedback signal and the reference signal VREF and outputs it to the hysteresis comparator circuit CMP.
电压采样电路的输入端获取采样信号Vpe、输出端连接三角波产生电路的输入端,电压采样电路用于根据采样信号Vpe生成偏置电压VDP并输出给三角波产生电路。三角波产生电路还连接逻辑控制电路,逻辑控制电路用于输出第二控制信号Sense2和第三控制信号Sense3给三角波产生电路,三角波产生电路用于根据偏置电压VDP、第二控制信号Sense2和第三控制信号Sense3产生三角波信号Ramp并输出给迟滞比较器电路CMP。The input terminal of the voltage sampling circuit obtains the sampling signal Vpe, and the output terminal is connected to the input terminal of the triangle wave generating circuit. The voltage sampling circuit is used to generate the bias voltage VDP according to the sampling signal Vpe and output it to the triangle wave generating circuit. The triangle wave generating circuit is also connected to a logic control circuit. The logic control circuit is used to output the second control signal Sense2 and the third control signal Sense3 to the triangle wave generating circuit. The triangle wave generating circuit is used to generate the triangle wave according to the bias voltage VDP, the second control signal Sense2 and the third control signal. The control signal Sense3 generates a triangular wave signal Ramp and outputs it to the hysteresis comparator circuit CMP.
迟滞比较器电路CMP的输出端连接逻辑控制电路的输入端,迟滞比较器电路CMP还连接逻辑控制电路,逻辑控制电路用于输出第一控制信号Sense1给迟滞比较器电路CMP。迟滞比较器电路CMP用于根据输入的第一控制信号Sense1对误差信号COMP和三角波信号Ramp进行迟滞比较后产生调制波信号PWM并输出给逻辑控制电路。逻辑控制电路中包括一些列常规逻辑器件,逻辑控制电路对调制波信号PWM进行逻辑处理后产生上臂驱动信号DRU、下臂驱动信号DRL、第一控制信号Sense1、第二控制信号Sense2和第三控制信号Sense3,上臂驱动信号DRU和下臂驱动信号DRL相反,第一控制信号Sense1、第二控制信号Sense2和第三控制信号Sense3耦合于上下臂驱动信号从而与上臂驱动信号DRU和下臂驱动信号DRL同频率,第二控制信号Sense2和第三控制信号Sense3是两个非交叠时钟信号。其中耦合表示直接采用上臂驱动信号DRU或下臂驱动信号DRL,或者由上臂驱动信号DRU或下臂驱动信号DRL经过一系列逻辑控制得到,即实现对上臂驱动信号DRU或下臂驱动信号DRL的采样。第一控制信号Sense1作为迟滞比较器电路CMP的控制信号输出给迟滞比较器电路CMP,第二控制信号Sense2和第三控制信号Sense3作为三角波产生电路的控制信号输出给三角波产生电路,上臂驱动信号DRU用于驱动上臂MOS开关S1,下臂驱动信号DRL用于驱动下臂MOS开关S2,从而实现在系统输出端VOUT输出稳定的电压。The output terminal of the hysteresis comparator circuit CMP is connected to the input terminal of the logic control circuit. The hysteresis comparator circuit CMP is also connected to the logic control circuit. The logic control circuit is used to output the first control signal Sense1 to the hysteresis comparator circuit CMP. The hysteresis comparator circuit CMP is used to perform hysteresis comparison between the error signal COMP and the triangular wave signal Ramp according to the input first control signal Sense1 to generate a modulated wave signal PWM and output it to the logic control circuit. The logic control circuit includes a series of conventional logic devices. The logic control circuit performs logic processing on the modulation wave signal PWM to generate the upper arm drive signal DRU, the lower arm drive signal DRL, the first control signal Sense1, the second control signal Sense2 and the third control The signal Sense3, the upper arm drive signal DRU and the lower arm drive signal DRL are opposite, the first control signal Sense1, the second control signal Sense2 and the third control signal Sense3 are coupled to the upper and lower arm drive signals so as to be the same as the upper arm drive signal DRU and the lower arm drive signal DRL At the same frequency, the second control signal Sense2 and the third control signal Sense3 are two non-overlapping clock signals. The coupling means that the upper arm drive signal DRU or the lower arm drive signal DRL is directly used, or the upper arm drive signal DRU or the lower arm drive signal DRL is obtained through a series of logic control, that is, the sampling of the upper arm drive signal DRU or the lower arm drive signal DRL is realized . The first control signal Sense1 is output as the control signal of the hysteresis comparator circuit CMP to the hysteresis comparator circuit CMP, the second control signal Sense2 and the third control signal Sense3 are output as the control signals of the triangle wave generating circuit to the triangle wave generating circuit, and the upper arm drive signal DRU It is used to drive the upper arm MOS switch S1, and the lower arm drive signal DRL is used to drive the lower arm MOS switch S2, so as to achieve a stable voltage output at the system output terminal VOUT.
其中,三角波产生电路的一种电路图请参考图2,三角波产生电路包括第一开关S3和第二开关S4构成的串联电路,该串联电路的一端连接工作电压VCC、另一端接地,这里的工作电压VCC可以是系统内部的固定电压,也可以是系统输入端VIN的输入电压。第一开关S3和第二开关S4的公共端依次连接第三电阻R R和第三电容C R,第三电容C R的另一端作为三角波产生电路的输入端用于连接电压采样电路从而获取偏置电压VDP,第三电阻R R和第三电容C R的公共端作为三角波产生电路的输出端连接迟滞比较器电路CMP。第二控制信号Sense2和第三控制信号Sense3作为三角波产生电路的控制信号具体为:第二控制信号Sense2作为第一开关S3的控制信号,第三控制信号Sense3作为第二开关S4的控制信号。 Please refer to Figure 2 for a circuit diagram of the triangle wave generating circuit. The triangle wave generating circuit includes a series circuit composed of a first switch S3 and a second switch S4. One end of the series circuit is connected to the working voltage VCC and the other end is grounded. VCC can be a fixed voltage inside the system or the input voltage of the input terminal VIN of the system. The common ends of the first switch S3 and the second switch S4 are sequentially connected to the third resistor R R and the third capacitor C R , and the other end of the third capacitor C R is used as the input end of the triangle wave generating circuit for connecting the voltage sampling circuit to obtain the bias Set the voltage VDP, the common end of the third resistor R R and the third capacitor C R is connected to the hysteresis comparator circuit CMP as the output end of the triangle wave generating circuit. The second control signal Sense2 and the third control signal Sense3 as the control signal of the triangle wave generating circuit are specifically: the second control signal Sense2 is used as the control signal of the first switch S3, and the third control signal Sense3 is used as the control signal of the second switch S4.
本申请中的三角波产生电路的另一种电路图请参考图3,图3在图2所示的电路的基础上在输出端增加了电流产生电路。电流产生电路包括第一增益模块k1、 第二增益模块k2、除法器DIVIDER和电压电流转换器V/R,第一增益模块k1的输入端连接系统输入端VIN,第二增益模块k2的输入端连接系统输出端VOUT,第一增益模块k1的输出端和第二增益模块k2的输出端分别连接除法器DIVIDER的两个输入端,除法器DIVIDER的输出端连接电压电流转换器V/R的输入端,电压电流转换器V/R的输出端作为电流产生电路的输出端连接三角波产生电路的输出端。电流产生电路受系统输入端VIN和系统输出端VOUT的信号控制,通过两个增益模块分别对输入信号VIN和输出信号VOUT进行采样运算,然后通过除法器DIVIDER实现VOUT除以VIN的关系,再由电压电流转换器V/R转换成一与输入信号VIN和输出信号VOUT电压相关的电流参与三角波信号Ramp上升、下降斜率的改变,以达到减小该系统工作频率随输入信号VIN和输出信号VOUT变化而变动的目的,通过这种方式,可以实现其工作频率进一步和输入信号VIN与输出信号VOUT无关的效果。参与改变三角波信号Ramp的电流和输入信号VIN成反比,和输出信号VOUT成正比,公式为IB=k*VOUT/VIN,其中,k表示一个常数。Please refer to FIG. 3 for another circuit diagram of the triangle wave generating circuit in this application. FIG. 3 adds a current generating circuit to the output terminal on the basis of the circuit shown in FIG. 2. The current generating circuit includes a first gain module k1, a second gain module k2, a divider DIVIDER, and a voltage-current converter V/R. The input terminal of the first gain module k1 is connected to the system input terminal VIN, and the input terminal of the second gain module k2 Connect the system output terminal VOUT, the output terminal of the first gain module k1 and the output terminal of the second gain module k2 are respectively connected to the two input terminals of the divider DIVIDER, and the output terminal of the divider DIVIDER is connected to the input of the voltage-current converter V/R The output terminal of the voltage-current converter V/R is connected to the output terminal of the triangle wave generating circuit as the output terminal of the current generating circuit. The current generating circuit is controlled by the signals of the system input terminal VIN and the system output terminal VOUT. The input signal VIN and the output signal VOUT are sampled and operated respectively through two gain modules, and then the relationship between VOUT divided by VIN is realized through the divider DIVIDER, and then by The voltage-current converter V/R converts into a current related to the voltage of the input signal VIN and the output signal VOUT to participate in the change of the rising and falling slopes of the triangular wave signal Ramp, so as to reduce the system operating frequency as the input signal VIN and the output signal VOUT change. The purpose of the change, in this way, the effect that its operating frequency is further independent of the input signal VIN and the output signal VOUT can be achieved. The current involved in changing the triangular wave signal Ramp is inversely proportional to the input signal VIN and proportional to the output signal VOUT. The formula is IB=k*VOUT/VIN, where k represents a constant.
图1是本申请公开的开关电源系统的整体电路架构,在实际实现时,图1的电路架构中的各部分电路都有多种实现方式:Figure 1 is the overall circuit architecture of the switching power supply system disclosed in this application. In actual implementation, each part of the circuit in the circuit architecture of Figure 1 has multiple implementation modes:
一、迟滞比较器电路CMP的多种实现方式。1. Multiple implementations of hysteresis comparator circuit CMP.
迟滞比较器电路CMP主要有两种实现方式:第一种方式为直接采用市售的迟滞比较器,第二种方式为采用迟滞产生电路和比较器构成。直接采用市售迟滞比较器的电路结构即直接为图1的电路结构,其中迟滞比较器电路CMP可以根据实际需要选用合适的型号,本申请不再详细介绍。本申请主要对自行搭建的情况进行说明。当迟滞比较器电路CMP包括迟滞产生电路和比较器P时,比较器P的输入端分别连接误差放大器EA的输出端和三角波产生电路的输出端,比较器P的输出端作为迟滞比较器电路的输出端连接逻辑控制电路,逻辑控制电路产生的第一控制信号Sense1输出给迟滞产生电路进行控制,迟滞产生电路的具体设置方式主要有三种情况:The hysteresis comparator circuit CMP mainly has two implementation methods: the first method is to directly use a commercially available hysteresis comparator, and the second method is to use a hysteresis generating circuit and a comparator. The circuit structure of a commercially available hysteresis comparator is directly adopted as the circuit structure of FIG. 1, wherein the hysteresis comparator circuit CMP can select a suitable model according to actual needs, which will not be described in detail in this application. This application mainly explains the self-built situation. When the hysteresis comparator circuit CMP includes a hysteresis generating circuit and a comparator P, the input terminal of the comparator P is connected to the output terminal of the error amplifier EA and the output terminal of the triangle wave generating circuit respectively, and the output terminal of the comparator P serves as the hysteresis comparator circuit The output terminal is connected to the logic control circuit, and the first control signal Sense1 generated by the logic control circuit is output to the hysteresis generating circuit for control. There are mainly three specific settings for the hysteresis generating circuit:
1、请参考图4,迟滞产生电路设置在误差放大器的输出端,且迟滞产生电路设置在误差放大器EA的输出端与比较器P的输入端之间,则在这种情况中,迟滞产生电路的具体电路图请参考图5。迟滞产生电路包括第一电流源IBP1、第一迟滞 开关Sh1、第二迟滞开关Sh2和第二电流源IBP2构成的第一串联电路,以及,第三电流源IBP3、第二迟滞开关Sh2、第一迟滞开关Sh1和第四电流源IBP4构成的第二串联电路。第一串联电路和第二串联电路的正极分别连接工作电压VCC、负极分别接地,工作电压VCC的定义见上。迟滞电阻Rhyst的一端连接第一串联电路中的第一迟滞开关Sh1和第二迟滞开关Sh2的公共端,迟滞电阻Rhyst的另一端连接第二串联电路中的第一迟滞开关Sh1和第二迟滞开关Sh2的公共端。第一串联电路中的第一迟滞开关Sh1和第二迟滞开关Sh2的公共端作为迟滞产生电路的输入端IN,第二串联电路中的第一迟滞开关Sh1和第二迟滞开关Sh2的公共端作为迟滞产生电路的输出端OUT。第一串联电路中的第一迟滞开关Sh1和第二串联电路中的第一迟滞开关Sh1由同一个控制信号控制,第一串联电路中的第二迟滞开关Sh2和第二串联电路中的第二迟滞开关Sh2由同一个控制信号控制,如图5所示,第一迟滞开关Sh1的控制信号和第二迟滞开关Sh2的控制信号均耦合于第一控制信号Sense1且两个控制信号相反。其中耦合表示这两个控制信号直接由第一控制信号Sense1得到或者由第一控制信号Sense1经过逻辑控制产生,图5以直接由第一控制信号Sense1得到为例,且图5仅示出了对其中两个迟滞开关的控制示意图。1. Please refer to Figure 4. The hysteresis generating circuit is set at the output of the error amplifier, and the hysteresis generating circuit is set between the output of the error amplifier EA and the input of the comparator P. In this case, the hysteresis generating circuit Please refer to Figure 5 for the specific circuit diagram. The hysteresis generating circuit includes a first series circuit composed of a first current source IBP1, a first hysteresis switch Sh1, a second hysteresis switch Sh2, and a second current source IBP2, and a third current source IBP3, a second hysteresis switch Sh2, and a first series circuit. The second series circuit formed by the hysteresis switch Sh1 and the fourth current source IBP4. The positive poles of the first series circuit and the second series circuit are respectively connected to the working voltage VCC, and the negative poles are respectively grounded. The working voltage VCC is defined above. One end of the hysteresis resistor Rhyst is connected to the common end of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the first series circuit, and the other end of the hysteresis resistor Rhyst is connected to the first hysteresis switch Sh1 and the second hysteresis switch in the second series circuit. The public end of Sh2. The common terminal of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the first series circuit is used as the input terminal IN of the hysteresis generating circuit, and the common terminal of the first hysteresis switch Sh1 and the second hysteresis switch Sh2 in the second series circuit is used as the input terminal IN of the hysteresis generating circuit. The output terminal OUT of the hysteresis generating circuit. The first hysteresis switch Sh1 in the first series circuit and the first hysteresis switch Sh1 in the second series circuit are controlled by the same control signal. The second hysteresis switch Sh2 in the first series circuit and the second hysteresis switch Sh2 in the second series circuit are controlled by the same control signal. The hysteresis switch Sh2 is controlled by the same control signal. As shown in FIG. 5, the control signal of the first hysteresis switch Sh1 and the control signal of the second hysteresis switch Sh2 are both coupled to the first control signal Sense1 and the two control signals are opposite. The coupling means that the two control signals are directly obtained by the first control signal Sense1 or generated by the first control signal Sense1 through logic control. FIG. 5 takes the first control signal Sense1 as an example, and FIG. 5 only shows the pair Control diagram of two hysteresis switches.
图5所示的迟滞产生电路的信号波形图请参考图6,迟滞产生电路通过一组和上下臂驱动信号相关的控制信号驱动一股电流流过一迟滞电阻Rhyst得到对IN端信号耦合一迟滞信号的OUT端信号,图6中的Vhysteretic即表示耦合在IN端信号上的迟滞信号。在这种情况中,迟滞产生电路的输入端IN即连接误差放大器EA的输出端,迟滞产生电路的输出端OUT即连接比较器P的输入端,因此迟滞产生电路产生迟滞信号于IN端输入的误差信号COMP上得到迟滞后的COMP信号从OUT端输出给比较器P,则比较器P对三角波信号Ramp和迟滞后的COMP进行比较产生调制波信号PWM。For the signal waveform diagram of the hysteresis generating circuit shown in Figure 5, please refer to Figure 6. The hysteresis generating circuit drives a current through a set of control signals related to the upper and lower arm drive signals to flow through a hysteresis resistor Rhyst to obtain a hysteresis coupling to the IN terminal signal. The OUT end signal of the signal, Vhysteretic in Figure 6 represents the hysteresis signal coupled to the IN end signal. In this case, the input terminal IN of the hysteresis generating circuit is connected to the output terminal of the error amplifier EA, and the output terminal OUT of the hysteresis generating circuit is connected to the input terminal of the comparator P. Therefore, the hysteresis generating circuit generates a hysteresis signal which is input at the IN terminal. The lagging COMP signal obtained from the error signal COMP is output from the OUT terminal to the comparator P, and the comparator P compares the triangular wave signal Ramp with the lagging COMP to generate a modulation wave signal PWM.
在情况1中,由于迟滞的设计存在与误差放大器EA的输出端,其输出端COMP为VOUT的采样信号于基准信号VREF的放大信号,故FB端的工作迟滞量较小,系统输出VOUT可以实现很小的波纹。In case 1, due to the hysteresis design and the output end of the error amplifier EA, the output end COMP is the amplified signal of the sampling signal of VOUT and the reference signal VREF, so the working hysteresis of the FB end is small, and the system output VOUT can achieve very Small ripples.
2、请参考图7,如情况1一样,迟滞产生电路也设置在误差放大器EA的输出端 ,但迟滞产生电路设置在补偿电阻R C的两端对误差放大器EA输出的COMP信号进行迟滞。则迟滞产生电路的电路图如图8所示,迟滞产生电路包括:电流源IBP、第二迟滞开关Sh2和第一迟滞开关Sh1构成的串联电路,该串联电路的正极连接工作电压VCC、负极接地,第二迟滞开关Sh2和第一迟滞开关Sh1的公共端用于连接补偿电容C C和补偿电阻R C的公共端。第一迟滞开关Sh1的控制信号和第二迟滞开关Sh2的控制信号均耦合于第一控制信号Sense1且两个控制信号相反,耦合的含义可以参照情况1,图8仅示出了两个控制信号的一种示意。 2. Please refer to Figure 7. As in case 1, the hysteresis generating circuit is also set at the output end of the error amplifier EA, but the hysteresis generating circuit is set at both ends of the compensation resistor R C to hysteresize the COMP signal output by the error amplifier EA. The circuit diagram of the hysteresis generating circuit is shown in Figure 8. The hysteresis generating circuit includes a series circuit composed of a current source IBP, a second hysteresis switch Sh2, and a first hysteresis switch Sh1. The positive pole of the series circuit is connected to the working voltage VCC and the negative pole is grounded. The common end of the second hysteresis switch Sh2 and the first hysteresis switch Sh1 is used to connect the common end of the compensation capacitor C C and the compensation resistor R C. The control signal of the first hysteresis switch Sh1 and the control signal of the second hysteresis switch Sh2 are both coupled to the first control signal Sense1 and the two control signals are opposite. For the meaning of the coupling, refer to Case 1. Figure 8 only shows two control signals A kind of hint.
图8所示的迟滞产生电路的信号波形图请参考图9,通过一组和上下臂驱动信号相关的控制信号驱动一股电流流过补偿电阻R C实现对COMP信号耦合一迟滞信号Vhysteretic的效果。在这种情况中,迟滞产生电路同样产生迟滞信号于误差信号COMP上,比较器P对三角波信号Ramp和迟滞后的COMP进行比较产生调制波信号PWM,但相比于情况1,由于迟滞控制在补偿电阻R C两端产生,控制更为简单,并可以进一步减少COMP信号在信号传输过程中被干扰的可能性。 For the signal waveform diagram of the hysteresis generating circuit shown in Figure 8, please refer to Figure 9. A set of control signals related to the upper and lower arm drive signals drive a current to flow through the compensation resistor R C to achieve the effect of coupling a hysteresis signal Vhysteretic to the COMP signal . In this case, the hysteresis generating circuit also generates a hysteresis signal on the error signal COMP, and the comparator P compares the triangular wave signal Ramp with the delayed COMP to generate the modulated wave signal PWM, but compared to the case 1, due to the hysteresis control The compensation resistor R C is generated at both ends, the control is simpler, and the possibility of the COMP signal being interfered in the signal transmission process can be further reduced.
3、请参考图10,与情况1和2不同,在情况3中,迟滞产生电路设置在三角波产生电路的输出端,具体设置在三角波产生电路的输出端与比较器P的输入端之间,则这种情况中迟滞产生电路的具体电路图与图5相同,波形图与图6相同,不同的是,图5所示的迟滞产生电路的输入端IN连接三角波产生电路的输出端、输出端OUT连接比较器P的输入端,则迟滞产生电路产生迟滞信号于IN端输入的三角波信号Ramp上得到迟滞后的三角波信号Ramp从OUT端输出给比较器P,比较器P对误差信号COMP和迟滞后的三角波信号Ramp进行比较产生调制波信号PWM,相比于情况1和2,这种情况的迟滞控制在Ramp端,可以减少COMP信号在信号产生过程中被干扰。3. Please refer to Figure 10. Different from cases 1 and 2, in case 3, the hysteresis generating circuit is set at the output terminal of the triangle wave generating circuit, specifically between the output terminal of the triangle wave generating circuit and the input terminal of the comparator P, In this case, the specific circuit diagram of the hysteresis generating circuit is the same as that of Figure 5, and the waveform diagram is the same as that of Figure 6, except that the input terminal IN of the hysteresis generating circuit shown in Figure 5 is connected to the output terminal and output terminal OUT of the triangular wave generating circuit. Connect the input terminal of the comparator P, the hysteresis generating circuit generates a hysteresis signal on the triangular wave signal Ramp input at the IN terminal to obtain the lagging triangular wave signal Ramp from the OUT terminal to the comparator P, and the comparator P responds to the error signal COMP and the hysteresis The triangular wave signal Ramp is compared to generate the modulated wave signal PWM. Compared with cases 1 and 2, the hysteresis control in this case is at the Ramp end, which can reduce the interference of the COMP signal during signal generation.
二、电压采样电路的多种实现方式,主要有如下几种:2. There are several ways to realize the voltage sampling circuit, mainly as follows:
1、电压采样电路获取的采样信号反应了采样换相点处信号的信息特征,主要有两种情况:1. The sampling signal obtained by the voltage sampling circuit reflects the information characteristics of the signal at the sampling commutation point. There are two main cases:
1.1、电压采样电路的输入端直接耦接采样换相点SW,如图4、7和10所示,则电压采样电路获取到的采样信号即为采样换相点SW处的信号,在这种情况中,电压采样电路的电路图请参考图11,电压采样电路包括滤波电阻RF和滤波电容C F构成的RC滤波电路,RC滤波电路的输入端作为电压采样电路的输入端直接耦接采样换相点SW,RC滤波电路的输出端通过缓冲器Buffer连接电压采样电路的输出端从而输出偏置电压VDP,在这种情况中,电压采样电路根据采样换相点SW处的信号生成的偏置电压VDP具有与采样换相点SW处的信号一致的信息特征。在这种情况下,三角波信号Ramp的斜率基本与采样换相点SW的大小无关,所以系统工作频率与输出电流负载关系很小。1.1. The input terminal of the voltage sampling circuit is directly coupled to the sampling commutation point SW, as shown in Figures 4, 7 and 10, the sampling signal obtained by the voltage sampling circuit is the signal at the sampling commutation point SW. In this case, please refer to Figure 11 for the circuit diagram of the voltage sampling circuit. The voltage sampling circuit includes an RC filter circuit composed of a filter resistor RF and a filter capacitor CF. The input of the RC filter circuit is directly coupled to the sampling commutation point as the input of the voltage sampling circuit. SW, the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer to output the bias voltage VDP. In this case, the voltage sampling circuit generates the bias voltage VDP according to the signal at the sampling commutation point SW It has the same information characteristics as the signal at the sampling commutation point SW. In this case, the slope of the triangular wave signal Ramp is basically independent of the size of the sampling commutation point SW, so the system operating frequency has a very small relationship with the output current load.
1.2、电压采样电路的输入端不直接耦接采样换相点SW,而是连接逻辑控制电路,请参考图12,图12是在图4的基础上改变电压采样电路得到的电路结构。则在这种情况中,电压采样电路获取到的采样信号包括逻辑控制电路输出的第四控制信号Sense4和第五控制信号Sense5,第四控制信号Sense4和第五控制信号Sense5均耦合于上、下臂驱动信号且第四控制信号Sense4和第五控制信号Sense5相反,耦合的含义见上。由于第四控制信号Sense4和第五控制信号Sense5分别采样了上臂驱动信号DRU和下臂驱动信号DRL,因此电压采样电路获取到的采样信号反应了采样换相点SW处信号的信息特征,电压采样电路根据该采样信号生成的偏置电压VDP也具有与采样换相点SW处的信号一致的信息特征。1.2. The input terminal of the voltage sampling circuit is not directly coupled to the sampling commutation point SW, but is connected to the logic control circuit. Please refer to Figure 12, which is a circuit structure obtained by changing the voltage sampling circuit on the basis of Figure 4. In this case, the sampling signal obtained by the voltage sampling circuit includes the fourth control signal Sense4 and the fifth control signal Sense5 output by the logic control circuit. The fourth control signal Sense4 and the fifth control signal Sense5 are both coupled to the upper and lower control signals. The arm drive signal and the fourth control signal Sense4 are opposite to the fifth control signal Sense5. The meaning of coupling is as above. Since the fourth control signal Sense4 and the fifth control signal Sense5 sample the upper arm drive signal DRU and the lower arm drive signal DRL respectively, the sampling signal obtained by the voltage sampling circuit reflects the information characteristics of the signal at the sampling commutation point SW, and the voltage sampling The bias voltage VDP generated by the circuit according to the sampling signal also has the same information characteristics as the signal at the sampling commutation point SW.
这种情况中的电压采样电路请参考图13,电压采样电路包括第一采样开关S5和第二采样开关S6构成的串联电路,该串联电路的一端连接工作电压VCC、另一端接地,第一采样S5开关和第二采样开关S6的公共端连接滤波电阻RF和滤波电容CF构成的RC滤波电路的输入端,RC滤波电路的输出端通过缓冲器Buffer连接电压采样电路的输出端从而输出偏置电压VDP。逻辑控制电路输出的第四控制信号Sense4作为第一采样开关S5的控制信号输出给电压采样电路,逻辑控制电路输出的第五控制信号Sense5作为第二采样开关S6的控制信号输出给电压采样电路。图13所示的电压采样电路在CCM模式和DEM模式下的时序波形图请参考图14,图中左边部分为CCM模式下的S5、S6状态和VA节点电压波形;右边部分为DEM模式下的S5、S6状态和VA节点电压波形,当S5和S6均关断时,VA节点电压等于BUFFER的输入电压VB。在这种情况中,进入三角波产生电路的偏置电压VDP与采样换相点SW的信号大小完全无关,所以系统工作频率与输出电流负载大小完全无关。Please refer to Figure 13 for the voltage sampling circuit in this case. The voltage sampling circuit includes a series circuit composed of a first sampling switch S5 and a second sampling switch S6. One end of the series circuit is connected to the working voltage VCC and the other end is grounded. The common terminal of the S5 switch and the second sampling switch S6 is connected to the input terminal of the RC filter circuit formed by the filter resistor RF and the filter capacitor CF, and the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through the buffer to output the bias voltage VDP. The fourth control signal Sense4 output by the logic control circuit is output to the voltage sampling circuit as a control signal of the first sampling switch S5, and the fifth control signal Sense5 output by the logic control circuit is output to the voltage sampling circuit as a control signal of the second sampling switch S6. For the timing waveform diagrams of the voltage sampling circuit shown in Figure 13 in CCM mode and DEM mode, please refer to Figure 14. The left part of the figure is the S5, S6 state and VA node voltage waveforms in CCM mode; the right part is the voltage waveform of the VA node in DEM mode. S5, S6 state and VA node voltage waveform, when S5 and S6 are both off, the VA node voltage is equal to the input voltage VB of BUFFER. In this case, the bias voltage VDP entering the triangle wave generating circuit is completely independent of the signal size at the sampling commutation point SW, so the system operating frequency is completely independent of the output current load.
2、电压采样电路获取的采样信号是固定信号,则在这种情况中,电压采样电路的输入端直接连接固定电压,则电压采样电路获取到的采样信号为固定电压,固定电压经过内部的缓冲器后从输出端输出偏置电压VDP,本申请不再示出这种情况时的电压采样电路的电路图。2. The sampling signal obtained by the voltage sampling circuit is a fixed signal. In this case, the input terminal of the voltage sampling circuit is directly connected to a fixed voltage, and the sampling signal obtained by the voltage sampling circuit is a fixed voltage, and the fixed voltage is internally buffered. After the device, the bias voltage VDP is output from the output terminal. This application will not show the circuit diagram of the voltage sampling circuit in this case.
本申请通过上述内容介绍了迟滞比较器电路、电压采样电路和三角波产生电路的多种电路实现方式,在实际实现时,这多部分电路可以进行不同的互相组合,从而构成多种不同的电路结构的开关电源系统的电路,本申请不对每一种可能的实现方式进行详细图示说明。在上述各个实施例中,逻辑控制电路内部包括各种常规逻辑器件,从而对输入的调制波信号PWM进行逻辑处理产生所需的各路驱动和控制信号,具体的逻辑控制电路的电路搭建可以根据实际情况自行配置,本申请以逻辑控制电路输出上臂驱动信号DRU、下臂驱动信号DRL和五路控制信号Sense1~Sense5为例,给出了逻辑控制电路的一种可能的电路结构如图15所示,图15仅供参考,并不用于对逻辑控制电路进行限定。This application introduces various circuit implementations of hysteresis comparator circuit, voltage sampling circuit and triangle wave generating circuit through the above content. In actual implementation, these multiple circuits can be combined with each other in different ways to form a variety of different circuit structures. For the circuit of the switching power supply system, this application does not illustrate every possible implementation in detail. In each of the above-mentioned embodiments, the logic control circuit includes various conventional logic devices, so that the input modulation wave signal PWM is logically processed to generate the required driving and control signals. The circuit construction of the specific logic control circuit can be based on The actual situation is self-configured. In this application, the logic control circuit outputs the upper arm drive signal DRU, the lower arm drive signal DRL and five control signals Sense1 to Sense5 as an example, and a possible circuit structure of the logic control circuit is shown in Figure 15. As shown, Figure 15 is for reference only and is not used to limit the logic control circuit.
基于本申请公开的上述电路结构,本申请以图4和图10作为两个典型的电路结构来展示本申请公开的开关电源系统的工作过程:Based on the above-mentioned circuit structure disclosed in this application, this application uses FIG. 4 and FIG. 10 as two typical circuit structures to show the working process of the switching power supply system disclosed in this application:
1、在开关电源系统采用图4所示的电路结构时,迟滞产生电路设置在误差放大器和比较器之间对COMP信号进行迟滞控制、电压采样电路直接耦接SW,则开关电源系统在CCM模式(连续模式)下的工作波形图请参考图16,在上臂MOS开关S1打开、下臂MOS开关S2关断的时候,迟滞产生电路在误差放大器产生的误差信号COMP上产生一迟滞信号Vhysteretic得到迟滞后的误差信号,图16中表示为COMP2,三角波信号Ramp电压开始线性上升。当Ramp电压上升到等于COMP2时,上臂MOS开关S1关断、下臂MOS开关S2导通,此时COMP2信号下跳一个迟滞量Vhysteretic,Ramp信号线性下降;当Ramp信号下降到再次等于COMP2时,下臂S2关断上臂S1重新导通,此时COMP2信号上跳一个迟滞量,Ramp信号再次线性上升直到Ramp信号再次等于COMP2信号,上臂MOS开关S1关断、下臂MOS开关S2导通,周而复始。系统在CCM模式下的工作频率为:1. When the switching power supply system adopts the circuit structure shown in Figure 4, the hysteresis generation circuit is set between the error amplifier and the comparator to perform hysteresis control on the COMP signal, and the voltage sampling circuit is directly coupled to SW, then the switching power supply system is in CCM mode (Continuous mode) Please refer to Figure 16 for the working waveform diagram. When the upper arm MOS switch S1 is turned on and the lower arm MOS switch S2 is turned off, the hysteresis generating circuit generates a hysteresis signal Vhysteretic on the error signal COMP generated by the error amplifier to obtain the hysteresis. After the error signal, shown as COMP2 in Figure 16, the triangular wave signal Ramp voltage starts to rise linearly. When the Ramp voltage rises to equal to COMP2, the upper arm MOS switch S1 is turned off, and the lower arm MOS switch S2 is turned on. At this time, the COMP2 signal jumps a hysteresis Vhysteretic, and the Ramp signal linearly drops; when the Ramp signal drops to COMP2 again, The lower arm S2 is turned off and the upper arm S1 is turned on again. At this time, the COMP2 signal jumps by a hysteresis, the Ramp signal rises linearly again until the Ramp signal is equal to the COMP2 signal again, the upper arm MOS switch S1 is turned off, the lower arm MOS switch S2 is turned on, and the cycle repeats . The operating frequency of the system in CCM mode is:
开关电源系统在DCM模式(断续模式)下的工作波形图请参考图17,当系统进入DCM后,下臂MOS开关S2关断。此时上下臂MOS开关均处于关断状态,SW电压振荡后稳定在输出电压VOUT值,Ramp信号终止以下臂MOS开关S2导通期间的线性速度下降。由于上下臂MOS开关均关断,系统输出电压VOUT经负载消耗后降低,使得误差放大器EA的输出电压COMP升高。Please refer to Figure 17 for the operating waveform of the switching power supply system in DCM mode (intermittent mode). When the system enters DCM, the lower arm MOS switch S2 is turned off. At this time, the upper and lower arm MOS switches are both in the off state, the SW voltage stabilizes at the output voltage VOUT value after oscillation, and the Ramp signal terminates the linear speed drop during the on-time of the lower arm MOS switch S2. Since both the upper and lower arm MOS switches are turned off, the system output voltage VOUT decreases after being consumed by the load, so that the output voltage COMP of the error amplifier EA increases.
2、在开关电源系统采用图10所示的电路结构时,迟滞产生电路设置在三角波产生电路和比较器之间对Ramp信号进行迟滞控制、电压采样电路直接耦接SW,则开关电源系统在CCM模式(连续模式)下的工作波形图请参考图18,在上臂MOS开关S1打开、下臂MOS开关S2关断的时候,Ramp信号开始线性上升,当Ramp信号上升到等于COMP信号时,上臂MOS开关S1关断、下臂MOS开关S2导通,此时Ramp信号先上跳一个迟滞量Vhysteretic,Ramp信号然后开始线性下降;当Ramp信号下降到再次等于COMP信号时,下臂MOS开关S2关断、上臂MOS开关S1重新导通,此时Ramp信号先下跳一个迟滞量Vhysteretic,Ramp信号再次线性上升直到Ramp信号再次等于COMP信号,上臂MOS开关S1关断、下臂MOS开关S2导通,周而复始。2. When the switching power supply system adopts the circuit structure shown in Figure 10, the hysteresis generating circuit is set between the triangle wave generating circuit and the comparator to perform hysteresis control on the Ramp signal, and the voltage sampling circuit is directly coupled to SW, then the switching power supply system is in CCM Please refer to Figure 18 for the working waveform diagram in the continuous mode. When the upper arm MOS switch S1 is turned on and the lower arm MOS switch S2 is turned off, the Ramp signal starts to rise linearly. When the Ramp signal rises to equal to the COMP signal, the upper arm MOS The switch S1 is turned off and the lower arm MOS switch S2 is turned on. At this time, the Ramp signal jumps up by a hysteresis amount Vhysteretic, and then the Ramp signal begins to linearly decrease; when the Ramp signal drops to the COMP signal again, the lower arm MOS switch S2 is turned off , The upper arm MOS switch S1 is turned on again. At this time, the Ramp signal first jumps by a hysteresis amount Vhysteretic, and the Ramp signal rises linearly again until the Ramp signal is equal to the COMP signal again. The upper arm MOS switch S1 is turned off, and the lower arm MOS switch S2 is turned on, and the cycle starts again. .
以上所述的仅是本申请的优选实施方式,本发明不限于以上实施例。可以理解,本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想到的其他改进和变化,均应认为包含在本发明的保护范围之内。The above are only the preferred implementation manners of the present application, and the present invention is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought of by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims (9)

  1. 一种基于迟滞模式控制的开关电源系统,其特征在于,所述开关电源系统包括上臂MOS开关和下臂MOS开关构成的串联电路,所述串联电路的一端连接所述开关电源系统的系统输入端、另一端接地,所述上臂MOS开关和下臂MOS开关的公共端作为采样换相点通过电感连接所述开关电源系统的系统输出端,所述系统输出端还分别连接第一电阻、第一电容和第二电容,所述第二电容的另一端接地,所述第一电阻和所述第一电容的另一端相连后通过第二电阻接地,所述第一电阻与所述第二电阻的公共端连接至误差放大器的反相输入端,所述误差放大器的同相输入端输入基准信号,所述误差放大器的输出端连接迟滞比较器电路,所述误差放大器的输出端还依次连接补偿电容和补偿电阻后接地,所述误差放大器根据输入的信号产生误差信号并输出给所述迟滞比较器电路;A switching power supply system based on hysteresis mode control, characterized in that the switching power supply system includes a series circuit composed of an upper arm MOS switch and a lower arm MOS switch, and one end of the series circuit is connected to the system input end of the switching power supply system , The other end is grounded, the common end of the upper arm MOS switch and the lower arm MOS switch is used as a sampling commutation point to connect the system output end of the switching power supply system through an inductor, and the system output end is also connected to a first resistor and a first resistor, respectively. A capacitor and a second capacitor, the other end of the second capacitor is grounded, the first resistor is connected to the other end of the first capacitor and then grounded through a second resistor, the first resistor is connected to the second resistor The common terminal is connected to the inverting input terminal of the error amplifier, the non-inverting input terminal of the error amplifier inputs the reference signal, the output terminal of the error amplifier is connected to the hysteresis comparator circuit, and the output terminal of the error amplifier is also connected to the compensation capacitor and After the compensation resistor is grounded, the error amplifier generates an error signal according to the input signal and outputs it to the hysteresis comparator circuit;
    电压采样电路的输入端获取采样信号、输出端连接三角波产生电路的输入端,所述电压采样电路用于根据所述采样信号生成偏置电压并输出给所述三角波产生电路,所述采样信号为固定信号或所述采样信号是反应所述采样换相点处信号的信息特征的可变信号;所述三角波产生电路包括第一开关和第二开关构成的串联电路,所述串联电路的一端连接工作电压、另一端接地,所述第一开关和第二开关的公共端依次连接第三电阻和第三电容,所述第三电容的另一端作为所述三角波产生电路的输入端用于连接所述电压采样电路,所述第三电阻和第三电容的公共端作为所述三角波产生电路的输出端连接所述迟滞比较器电路,所述三角波产生电路用于根据所述偏置电压以及所述第一开关的控制信号和所述第二开关的控制信号产生三角波信号并输出给所述迟滞比较器电路;所述迟滞比较器电路的输出端连接逻辑控制电路的输入端,所述迟滞比较器电路用于根据输入的第一控制信号对所述误差信 号和三角波信号进行迟滞比较后产生调制波信号并输出给所述逻辑控制电路,所述逻辑控制电路对所述调制波信号进行逻辑处理后产生上臂驱动信号、下臂驱动信号、所述第一控制信号、第二控制信号和第三控制信号,所述上臂驱动信号和所述下臂驱动信号相反,所述第一控制信号、第二控制信号和第三控制信号耦合于上、下臂驱动信号并与上、下臂驱动信号同频率,所述上臂驱动信号用于驱动所述上臂MOS开关,所述下臂驱动信号用于驱动所述下臂MOS开关,所述第一控制信号作为所述迟滞比较器电路的控制信号输出给所述迟滞比较器电路,所述第二控制信号作为所述第一开关的控制信号输出给所述三角波产生电路,所述第三控制信号作为所述第二开关的控制信号输出给所述三角波产生电路。The input terminal of the voltage sampling circuit obtains a sampling signal, and the output terminal is connected to the input terminal of the triangle wave generating circuit. The voltage sampling circuit is used to generate a bias voltage according to the sampling signal and output it to the triangle wave generating circuit. The sampling signal is The fixed signal or the sampling signal is a variable signal reflecting the information characteristics of the signal at the sampling commutation point; the triangle wave generating circuit includes a series circuit composed of a first switch and a second switch, one end of the series circuit is connected The working voltage and the other end are grounded. The common ends of the first switch and the second switch are sequentially connected to a third resistor and a third capacitor. The other end of the third capacitor is used as the input end of the triangle wave generating circuit to connect to the In the voltage sampling circuit, the common terminal of the third resistor and the third capacitor is used as the output terminal of the triangular wave generating circuit to be connected to the hysteresis comparator circuit, and the triangular wave generating circuit is used to connect the hysteresis comparator circuit according to the bias voltage and the The control signal of the first switch and the control signal of the second switch generate a triangular wave signal and output it to the hysteresis comparator circuit; the output terminal of the hysteresis comparator circuit is connected to the input terminal of the logic control circuit, the hysteresis comparator The circuit is used to perform a hysteresis comparison between the error signal and the triangular wave signal according to the input first control signal to generate a modulated wave signal and output it to the logic control circuit. The logic control circuit performs logic processing on the modulated wave signal The upper arm drive signal, the lower arm drive signal, the first control signal, the second control signal, and the third control signal are generated. The upper arm drive signal is opposite to the lower arm drive signal, and the first control signal, the second The control signal and the third control signal are coupled to the upper and lower arm drive signals and have the same frequency as the upper and lower arm drive signals. The upper arm drive signal is used to drive the upper arm MOS switch, and the lower arm drive signal is used to drive the upper arm. In the lower arm MOS switch, the first control signal is output to the hysteresis comparator circuit as a control signal of the hysteresis comparator circuit, and the second control signal is output to the hysteresis comparator circuit as a control signal of the first switch A triangle wave generating circuit, and the third control signal is output to the triangle wave generating circuit as a control signal of the second switch.
  2. 根据权利要求1所述的开关电源系统,其特征在于,所述迟滞比较器电路包括迟滞产生电路和比较器,所述比较器的输入端分别连接所述误差放大器的输出端和所述三角波产生电路的输出端,所述比较器的输出端作为所述迟滞比较器电路的输出端连接所述逻辑控制电路,所述逻辑控制电路产生的所述第一控制信号输出给所述迟滞产生电路;所述迟滞产生电路设置在所述误差放大器的输出端并根据所述第一控制信号产生迟滞信号于所述误差信号,或者,所述迟滞产生电路设置在所述三角波产生电路的输出端并根据所述第一控制信号产生迟滞信号于所述三角波信号。The switching power supply system according to claim 1, wherein the hysteresis comparator circuit comprises a hysteresis generating circuit and a comparator, and the input of the comparator is respectively connected to the output of the error amplifier and the triangular wave generator. An output terminal of the circuit, the output terminal of the comparator is connected to the logic control circuit as the output terminal of the hysteresis comparator circuit, and the first control signal generated by the logic control circuit is output to the hysteresis generating circuit; The hysteresis generating circuit is arranged at the output terminal of the error amplifier and generates a hysteresis signal to the error signal according to the first control signal, or the hysteresis generating circuit is arranged at the output terminal of the triangle wave generating circuit and according to The first control signal generates a hysteresis signal to the triangle wave signal.
  3. 根据权利要求2所述的开关电源系统,其特征在于,The switching power supply system according to claim 2, wherein:
    当所述迟滞产生电路设置在所述误差放大器的输出端时,所述迟滞产生电路设置在所述误差放大器的输出端与所述比较器的输入端之间,或者,所述迟滞产生电路设置在所述补偿电阻的两端;当所述迟滞产生电路设置在所述三角波产生电路的输出端时,所述迟滞产生电路设置在所述三角波产生电路的输出端与所述比较器的输入端之间。When the hysteresis generating circuit is arranged at the output terminal of the error amplifier, the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged At both ends of the compensation resistor; when the hysteresis generating circuit is arranged at the output terminal of the triangle wave generating circuit, the hysteresis generating circuit is arranged at the output terminal of the triangle wave generating circuit and the input terminal of the comparator between.
  4. 根据权利要求3所述的开关电源系统,其特征在于,当所述迟滞产生电路设置在所述误差放大器的输出端与所述比较器的输入端之间,或者,所述迟滞产生电路设置在所述三角波产生电路的输出端与所述比较器的输入端之间时,所述迟滞产生电路包括:The switching power supply system according to claim 3, wherein when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, or the hysteresis generating circuit is arranged at When between the output terminal of the triangle wave generating circuit and the input terminal of the comparator, the hysteresis generating circuit includes:
    第一电流源、第一迟滞开关、第二迟滞开关和第二电流源构成的第一串联电路,以及,第三电流源、第二迟滞开关、第一迟滞开关和第四电流源构成的第二串联电路,所述第一串联电路和所述第二串联电路的正极分别连接工作电压、负极分别接地,迟滞电阻的一端连接所述第一串联电路中的第一迟滞开关和第二迟滞开关的公共端,所述迟滞电阻的另一端连接第二串联电路中的第一迟滞开关和第二迟滞开关的公共端,所述第一串联电路中的第一迟滞开关和第二迟滞开关的公共端作为所述迟滞产生电路的输入端连接所述误差放大器或所述三角波产生电路的输出端,所述第二串联电路中的第一迟滞开关和第二迟滞开关的公共端作为所述迟滞产生电路的输出端连接所述比较器;所述第一串联电路中的第一迟滞开关和所述第二串联电路中的第一迟滞开关由同一个控制信号控制,所述第一串联电路中的第二迟滞开关和所述第二串联电路中的第二迟滞开关由同一个控制信号控制,第一迟滞开关的控制信号和第二迟滞开关的控制信号均耦合于所述第一控制信号且两个控制信号相反。A first series circuit composed of a first current source, a first hysteresis switch, a second hysteresis switch, and a second current source, and a first series circuit composed of a third current source, a second hysteresis switch, a first hysteresis switch, and a fourth current source Two series circuits, the positive poles of the first series circuit and the second series circuit are respectively connected to the working voltage, and the negative poles are respectively grounded, and one end of the hysteresis resistor is connected to the first hysteresis switch and the second hysteresis switch in the first series circuit The other end of the hysteresis resistor is connected to the common end of the first hysteresis switch and the second hysteresis switch in the second series circuit, the common end of the first hysteresis switch and the second hysteresis switch in the first series circuit Terminal as the input terminal of the hysteresis generating circuit is connected to the error amplifier or the output terminal of the triangular wave generating circuit, the common terminal of the first hysteresis switch and the second hysteresis switch in the second series circuit is used as the hysteresis generating circuit The output terminal of the circuit is connected to the comparator; the first hysteresis switch in the first series circuit and the first hysteresis switch in the second series circuit are controlled by the same control signal, and the first hysteresis switch in the first series circuit The second hysteresis switch and the second hysteresis switch in the second series circuit are controlled by the same control signal. The control signal of the first hysteresis switch and the control signal of the second hysteresis switch are both coupled to the first control signal and both The control signals are opposite.
  5. 根据权利要求3所述的开关电源系统,其特征在于,当所述迟滞产生电路设置在所述误差放大器的输出端与所述比较器的输入端之间时,所述迟滞产生电路包括:4. The switching power supply system of claim 3, wherein when the hysteresis generating circuit is arranged between the output terminal of the error amplifier and the input terminal of the comparator, the hysteresis generating circuit comprises:
    电流源、第二迟滞开关和第一迟滞开关构成的串联电路,所述串联电路的正极连接工作电压、负极接地,所述第二迟滞开关和第一迟滞开关的公共端用于连接所述补偿电容和所述补偿电阻的公共端,所述第一迟滞开关的控制信号和所述第二迟滞开关的控制信号均耦合于所述第一控制信号且两个控制信号相反。A series circuit composed of a current source, a second hysteresis switch and a first hysteresis switch, the positive pole of the series circuit is connected to the working voltage and the negative pole is grounded, and the common terminal of the second hysteresis switch and the first hysteresis switch is used to connect the compensation The common terminal of the capacitor and the compensation resistor, the control signal of the first hysteresis switch and the control signal of the second hysteresis switch are all coupled to the first control signal, and the two control signals are opposite.
  6. 根据权利要求1所述的开关电源系统,其特征在于,The switching power supply system according to claim 1, wherein:
    所述电压采样电路的输入端连接固定电压,所述电压采样电路获取到的所述采样信号为所述固定电压;The input terminal of the voltage sampling circuit is connected to a fixed voltage, and the sampling signal obtained by the voltage sampling circuit is the fixed voltage;
    或者,所述电压采样电路的输入端耦接所述采样换相点,所述电压采样电路获取到的所述采样信号为所述采样换相点处的信号;Alternatively, the input terminal of the voltage sampling circuit is coupled to the sampling commutation point, and the sampling signal acquired by the voltage sampling circuit is the signal at the sampling commutation point;
    或者,所述电压采样电路的输入端连接所述逻辑控制电路,所述电压采样电路获取到的所述采样信号包括所述逻辑控制电路输出的第四控制信号和第五控制信号,所述第四控制信号和所述第五控制信号耦合于上、下臂驱动信号且所述第四控制信号和所述第五控制信号相反。Alternatively, the input terminal of the voltage sampling circuit is connected to the logic control circuit, and the sampling signal acquired by the voltage sampling circuit includes a fourth control signal and a fifth control signal output by the logic control circuit, and the first The fourth control signal and the fifth control signal are coupled to the upper and lower arm drive signals, and the fourth control signal is opposite to the fifth control signal.
  7. 根据权利要求6所述的开关电源系统,其特征在于,当所述电压采样电路的输入端直接耦接所述采样换相点时,所述电压采样电路包括:滤波电阻和滤波电容构成的RC滤波电路,所述RC滤波电路的输入端作为所述电压采样电路的输入端耦接所述采样换相点,所述RC滤波电路的输出端通过缓冲器连接所述电压采样电路的输出端。The switching power supply system according to claim 6, wherein when the input terminal of the voltage sampling circuit is directly coupled to the sampling commutation point, the voltage sampling circuit comprises: an RC composed of a filter resistor and a filter capacitor A filter circuit, the input terminal of the RC filter circuit as the input terminal of the voltage sampling circuit is coupled to the sampling commutation point, and the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through a buffer.
  8. 根据权利要求6所述的开关电源系统,其特征在于,当所述电压采样电路的输入端连接所述逻辑控制电路时,所述电压采样电路包括:The switching power supply system according to claim 6, wherein when the input terminal of the voltage sampling circuit is connected to the logic control circuit, the voltage sampling circuit comprises:
    第一采样开关和第二采样开关构成的串联电路,所述串联电路的一端连接工作电压、另一端接地,所述第一采样开关和第二采样开关的公共端连接滤波电阻和滤波电容构成的RC滤波电路的输入端,所述RC滤波电路的输出端通过缓冲器连接所述电压采样电路的输出端;所述逻辑控制电路输出的第四控制信号作为所述第一采样开关的控制信号输出给所述电压采样电路,所述逻辑控制电路输出的第五控制信号作为所述第二采样开关的控制信号输出给所述电压采样电路。A series circuit composed of a first sampling switch and a second sampling switch. One end of the series circuit is connected to the working voltage and the other end is grounded. The common end of the first sampling switch and the second sampling switch is connected to a filter resistor and a filter capacitor. The input terminal of the RC filter circuit, the output terminal of the RC filter circuit is connected to the output terminal of the voltage sampling circuit through a buffer; the fourth control signal output by the logic control circuit is output as the control signal of the first sampling switch For the voltage sampling circuit, the fifth control signal output by the logic control circuit is output to the voltage sampling circuit as a control signal of the second sampling switch.
  9. 根据权利要求1至8任一所述的开关电源系统,其特征在于,所述 三角波产生电路中还包括电流产生电路,所述电流产生电路包括第一增益模块、第二增益模块、除法器和电压电流转换器,所述第一增益模块的输入端连接所述系统输入端,所述第二增益模块的输入端连接所述系统输出端,所述第一增益模块的输出端和所述第二增益模块的输出端分别连接所述除法器的两个输入端,所述除法器的输出端连接所述电压电流转换器的输入端,所述电压电流转换器的输出端作为所述电流产生电路的输出端连接所述三角波产生电路的输出端。The switching power supply system according to any one of claims 1 to 8, wherein the triangle wave generating circuit further includes a current generating circuit, and the current generating circuit includes a first gain module, a second gain module, a divider and In the voltage-current converter, the input terminal of the first gain module is connected to the system input terminal, the input terminal of the second gain module is connected to the system output terminal, and the output terminal of the first gain module is connected to the first gain module. The output terminals of the two gain modules are respectively connected to the two input terminals of the divider, the output terminal of the divider is connected to the input terminal of the voltage-current converter, and the output terminal of the voltage-current converter is used as the current generator The output terminal of the circuit is connected to the output terminal of the triangle wave generating circuit.
PCT/CN2020/076936 2019-04-02 2020-02-27 Switching power supply system employing hysteretic mode control WO2020199804A1 (en)

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