CN105763054A - Frequency locking method and device for hysteresis-mode buck converter - Google Patents
Frequency locking method and device for hysteresis-mode buck converter Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
The invention discloses a frequency locking method for a hysteresis-mode buck converter. The method comprises the following steps: carrying out conversion on reference frequency and system sampling frequency to obtain voltage parameters corresponding to the reference frequency and system sampling frequency respectively; carrying out calculation according to the voltage parameters corresponding to the reference frequency and the voltage parameters corresponding to the system sampling frequency to obtain differential current signals; and controlling a slope of a voltage Vramp formed based on a feedback voltage Vfb through the differential current signals. The invention also discloses a device for realizing the method above.
Description
Technical Field
The invention relates to the technical field of analog switching power supplies, in particular to a frequency locking method and device for a hysteresis mode buck converter.
Background
Buck converters are used in portable devices such as: mobile phones, digital cameras, tablet computers, and the like are widely used. Such converters use load regulation and recovery time as an important performance indicator. The hysteresis mode control technology abandons the original loop control technology and the limit that the bandwidth must be limited to about 10% of the switching frequency, so that the system bandwidth can be greatly improved, namely: effectively improving the transient response of the system at the same operating frequency. However, the hysteresis mode itself has some disadvantages: most importantly, the operating frequency of the system varies with the duty ratio and the load size, so that new interference problems are introduced. Therefore, to make better use of the hysteresis mode, the problem of frequency variation must be solved.
Disclosure of Invention
To solve the existing technical problems, embodiments of the present invention provide a frequency locking method and apparatus for a hysteretic mode buck converter.
The embodiment of the invention provides a frequency locking method for a hysteresis mode buck converter, which comprises the following steps:
respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal.
Wherein, the converting the reference frequency and the system sampling frequency respectively to obtain the corresponding voltage parameters comprises:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
Wherein the calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency comprises:
and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.
Wherein, the voltage Vramp formed according to the feedback voltage Vfb is:
the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.
An embodiment of the present invention further provides a frequency locking device for a hysteretic mode buck converter, where the frequency locking device includes: the device comprises a frequency conversion module, a differential current forming module and a slope control module; wherein,
the frequency conversion module is used for respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;
the differential current forming module is used for calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;
and the slope control module is used for controlling the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.
The frequency conversion module converts the reference frequency and the system sampling frequency respectively to obtain corresponding voltage parameters, and the method comprises the following steps:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
Wherein the frequency conversion module comprises: two frequency detection modules with the same structure are used for converting the reference frequency and the system sampling frequency; each frequency detection module includes: the device comprises a frequency division unit, a pulse width fixing unit and a low-pass filtering unit; wherein,
the frequency dividing unit is used for executing frequency dividing operation on the reference frequency or the system sampling frequency and sending a frequency signal after frequency dividing to the pulse width fixing unit;
the pulse width fixing unit is used for generating a pulse signal with a fixed pulse width from the frequency signal after frequency division and sending the pulse signal to the low-pass filtering unit;
the low-pass filtering unit is used for generating a direct-current voltage signal according to the pulse signal with the fixed pulse width.
Wherein the differential current forming module comprises: the OTA operational amplifier, the module Z and the source follower amplifying circuit; wherein,
the two input stages of the OTA operational amplifier are a direct-current voltage signal corresponding to the reference frequency and a direct-current voltage signal corresponding to the system sampling frequency; the module Z is a compensation network of a frequency locking loop and is connected with the output end of the OTA operational amplifier; the output end of the OTA operational amplifier is also connected with the source follower amplifying circuit, and the source follower amplifying circuit is used for finally generating the differential current signal.
Wherein the slope control module comprises: MOS tubes M1, M2, M3 and M4 and a capacitor C, wherein the M1 and the M2 are P-type enhanced MOS tubes, and the M3 and the M4 are N-type enhanced MOS tubes; wherein,
the grid electrode of the M1 is connected with a PWM signal, and the source electrode is used as the input of the differential current; the grid electrode of the M2 is connected with a PWM _ N signal, and the drain electrode is used for outputting the differential current; the drain electrode of the M3 is the input of the differential current, and the grid electrode is connected with a PWM _ N signal; the grid electrode of the M4 is connected with a PWM signal, and the source electrode is used for outputting the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected and are connected with the capacitor C, and the other end of the capacitor C is connected with a feedback voltage Vfb.
An embodiment of the present invention further provides a system on a chip, where the system includes: the frequency locking device for a hysteretic mode buck converter as described above.
According to the frequency locking method and device for the hysteresis mode buck converter, provided by the embodiment of the invention, the reference frequency and the system sampling frequency are respectively converted to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal. In the embodiment of the invention, when the sampling frequency of the system is less than the reference frequency, the value of the formed differential current is increased, so that the slope of a voltage Vramp signal is increased, the voltage Vramp can trigger a reference window voltage Vhys more quickly, and the working frequency of the system is increased; otherwise, the working frequency of the system is reduced, and the function of frequency locking is realized through negative feedback.
Compared with the prior art, the embodiment of the invention has the following advantages:
firstly, the currently generally adopted technology is to utilize a phase-locked loop principle to carry out frequency locking, and the phase is locked on the basis of frequency locking, so that the complexity of system design is undoubtedly increased, and the scheme adopts a pure frequency locking technology to simplify circuit design; secondly, in the prior art, a difference signal generated by a phase-locked loop is used for adjusting a hysteresis window voltage Vhys, and the scheme uses the hysteresis window voltage Vhys to adjust a Vramp signal, so that the circuit design is also simplified.
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In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1 is a schematic flow chart illustrating an implementation of a frequency locking method for a hysteretic mode buck converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a frequency locking device for a hysteretic mode buck converter according to an embodiment of the present invention;
fig. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention;
fig. 4 is a schematic structural diagram of a frequency detection module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a differential current forming module according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a slope control module according to an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, the reference frequency and the system sampling frequency are respectively converted to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled through the differential current signal, so that the function of controlling the system frequency is finally achieved.
The invention is described in further detail below with reference to the figures and the embodiments.
Fig. 1 is a schematic flow chart illustrating an implementation of a frequency locking method for a hysteretic mode buck converter according to an embodiment of the present invention, as shown in fig. 1, the method includes:
step 101: respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;
step 102: calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;
step 103: the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal.
In this way, the voltage Vramp may be compared with the hysteresis window voltage Vhys to form a PWM signal, so as to adjust and control the operating frequency of the system.
In the embodiment of the invention, when the sampling frequency of the system is less than the reference frequency, the value of the formed differential current is increased, so that the slope of a voltage Vramp signal is increased, the voltage Vramp can trigger a reference window voltage Vhys more quickly, and the working frequency of the system is increased; otherwise, the working frequency of the system is reduced, and the function of frequency locking is realized through negative feedback.
In this embodiment of the present invention, the converting the reference frequency and the system sampling frequency in step 101 to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively includes:
respectively carrying out frequency division processing on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width; the frequency division processing operation performed on the reference frequency and the system sampling frequency is the same, for example: the same frequency divider may be used for frequency division.
In this embodiment of the present invention, the calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency in step 102 includes:
and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.
In the embodiment of the present invention, the voltage Vramp formed according to the feedback voltage Vfb is:
the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.
An embodiment of the present invention further provides a frequency locking device for a hysteretic mode buck converter, as shown in fig. 2, the frequency locking device includes: a frequency conversion module 20, a differential current forming module 21 and a slope control module 22; wherein,
the frequency conversion module 20 is configured to convert the reference frequency and the system sampling frequency respectively to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively;
the differential current forming module 21 is configured to calculate according to a voltage parameter corresponding to the reference frequency and a voltage parameter corresponding to the system sampling frequency to form a differential current signal;
the slope control module 22 is configured to control a slope of a voltage Vramp formed according to the feedback voltage Vfb through the differential current signal.
In the embodiment of the present invention, the frequency conversion module 20 converts the reference frequency and the system sampling frequency respectively to obtain corresponding voltage parameters, including:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
In one embodiment, as shown in fig. 3 and 4, the frequency conversion module 20 includes: two frequency detection modules of the same structure, one for conversion of a reference frequency and one for conversion of a system sampling frequency, each frequency detection module comprising: a frequency dividing unit 40, a pulse width fixing unit 41, and a Low Pass Filtering (LPF) unit 42; wherein,
the frequency dividing unit 40 is configured to perform frequency dividing operation on the reference frequency or the system sampling frequency, and send a frequency signal after frequency dividing to the pulse width fixing unit 41;
the pulse width fixing unit 41 is configured to generate a pulse signal with a fixed pulse width from the frequency-divided frequency signal, and send the pulse signal to the low-pass filtering unit 42;
the low-pass filtering unit 42 is configured to generate a dc voltage signal according to the pulse signal with the fixed pulse width.
In the embodiment of the present invention, the calculating by the differential current forming module 21 according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency includes:
and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.
In one embodiment, as shown in fig. 5, the differential current forming module 21 includes: the OTA operational amplifier, the module Z and the source follower amplifying circuit; wherein,
the two input stages of the OTA operational amplifier are a direct-current voltage signal corresponding to the reference frequency and a direct-current voltage signal corresponding to the system sampling frequency; the module Z is a compensation network of a frequency locking loop and is connected with the output end of the OTA operational amplifier; the output end of the OTA operational amplifier is connected with the source-follower amplifying circuit, and finally the differential current signal is generated through the source-follower amplifying circuit.
In the embodiment of the present invention, the voltage Vramp formed by the slope control module 22 according to the feedback voltage Vfb is:
the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.
In one embodiment, as shown in fig. 6, the slope control module includes: MOS tubes M1, M2, M3 and M4 and a capacitor C, wherein the M1 and M2 are P-type enhancement type MOS tubes, the M3 and M4 are N-type enhancement type MOS tubes, the M1 and M4 are switches controlled by a PWM signal, and the M3 and M2 are switches controlled by a PWM _ N signal. Wherein, the input end of the M1, namely the grid is connected with the PWM signal, and the source is the input of the differential current; the grid electrode of the M2 is connected with a PWM _ N signal, and the drain electrode is used for outputting the differential current; the drain electrode of the M3 is the input of the differential current, and the grid electrode is connected with a PWM _ N signal; the grid electrode of the M4 is connected with a PWM signal, and the source electrode is used for outputting the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected and are connected with the capacitor C, and the other end of the capacitor C is connected with a feedback voltage Vfb.
An embodiment of the present invention further provides a system on a chip, where the system includes: the frequency locking device for a hysteretic mode buck converter as described above.
Fig. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention, and as shown in fig. 3, the frequency locking device mainly comprises three parts:
the first part is composed of two frequency detection modules with the same structure, corresponding to the frequency conversion module 20 in fig. 2, and is used for converting the reference frequency and the system sampling frequency into voltage parameters respectively and then supplying the voltage parameters to the Gm unit;
the second part is a transconductance (GM) module, corresponding to the differential current forming module 21 in fig. 2, for generating current parameters for regulating the Ramp voltage;
the third part is a Ramp module, corresponding to the slope control module 22 in fig. 2, which mainly functions to generate a Ramp voltage parameter varying with the system operating frequency on the basis of the dc parameter of the feedback voltage Vfb, and it can increase the precision of the comparator and also adjust the system operating frequency through the frequency-locked loop;
in addition, the fast response PWM comparator and drive control module required for the hysteretic mode buck converter are also included in fig. 3.
As shown in fig. 3, the hysteresis mode system uses a PWM comparator as a core to control the output voltage within the window voltage range, thereby controlling the output voltage and the output voltage ripple. Because the output feedback voltage has very small ripple, a Ramp module is needed to amplify the ripple, so that the anti-interference capability of the system can be improved, and the jitter of the working frequency of the system can be reduced. On the other hand, due to different circuit parameters such as different input voltages, output voltages or inductances, the system operating frequency will also be different, and therefore the frequency-locked loop is also incorporated into the system control loop through the Ramp module. The specific control mode is that the frequency detection module respectively processes the reference frequency and the system sampling frequency, the generated voltage forms differential current through the GM module, the Ramp module influences the slope of the voltage Vramp, and the larger the slope of the voltage Vramp is, the faster the system working frequency is; the smaller the slope of the voltage Vramp, the slower the system operating frequency, so that the system operating frequency is adjusted by a negative feedback loop under different circuit parameter conditions to be stabilized near the reference frequency.
As shown in fig. 4, each of the frequency detection modules includes: a frequency dividing unit 40, a pulse width fixing unit 41, and a Low Pass Filtering (LPF) unit 42. Since the structure of each frequency detection unit is the same, the frequency detection unit corresponding to the reference frequency is described here as an example.
The reference frequency signal firstly enters a frequency division unit, and the frequency division unit mainly aims at adjusting the frequency of an input signal, so that a pulse width fixing unit at the later stage can meet the requirement of sampling in a larger frequency range, and only the reference frequency detection and the system working frequency adopt the same frequency divider; the frequency-divided frequency signal is used for generating a pulse signal with a fixed pulse width, so that different DutyCycles can be generated and input to the low-pass filtering unit at different frequencies, and corresponding direct-current output voltage Vf is generated, and the Vf signal directly reflects the frequency.
Therefore, the frequency detection process of the embodiment of the invention enables the circuit design to be simpler, does not need to use a phase-locked loop module, and enables the loop analysis to be simpler.
Fig. 5 is a schematic diagram of the structure of the transconductance module shown in fig. 3, i.e., the differential current forming module 21. The differential current forming module inputs voltage signals which reflect the high and low frequencies and are generated by the two frequency detection modules to the transconductance module, and performs operational amplification on the error of the two signals to generate differential current output signals. As shown in fig. 5, in one embodiment, a transconductance operational amplifier circuit, i.e., the OTA operational amplifier shown in fig. 5, may be directly used as an input stage of the transconductance module, the module Z is a compensation network of a frequency-locked loop, and a source-follower amplifier circuit composed of M1, M2, M3 and R is connected to the subsequent stage, the source-follower amplifier circuit is prior art and will not be described in detail herein, and finally, a required output error current signal is generated through the source-follower amplifier circuit. Here, by adjusting the size of the resistor R and the mirror ratio of M2 to M3, the gain of the OTA operational amplifier can also be set, and these parameters affect the gain of the entire frequency-locked loop.
And then, the Ramp module is controlled by the differential current signal so as to control the slope of a voltage Vramp signal, the finally output Vramp signal is generated on the basis of the direct-current working point of Vfb direct-current voltage, and then the Vramp signal is compared with a reference voltage window to form a PWM signal, so that the working frequency of the system is adjusted and controlled. As shown in fig. 6, the Vramp voltage is a triangular wave signal generated by charging and discharging with the static operating point of the Vfb voltage as the middle value, the charging and discharging currents are output error currents Δ I of the transconductance module, M1 and M2, and M3 and M4 are switches controlled by the PWM signal and the PWM _ N signal, respectively, to control charging and discharging of the capacitor C in fig. 6, when the buck converter system charges the inductor L in fig. 3, M1 and M3 are turned on, M2 and M4 are turned off, and the Ramp module charges the capacitor C in fig. 6; when the system discharges the inductor L, M1 and M3 are turned off, M2 and M4 are turned on, the Ramp module discharges the capacitor C shown in FIG. 6, and the generated voltage Vramp signal is affected by the difference between the system operating frequency and the reference operating frequency, so that the system operating frequency is adjusted.
When the system working frequency is smaller than the reference frequency, the current error signal output by the transconductance module is increased, so that the gradient of the Vramp signal is increased, the Vramp can trigger the hysteresis window voltage Vhys more quickly, and the system working frequency is increased; otherwise, the working frequency of the system is reduced, and the function of frequency locking is realized through negative feedback.
Compared with the prior art, the embodiment of the invention has two differences: firstly, the currently generally adopted technology is to utilize a phase-locked loop principle to carry out frequency locking, and the phase is locked on the basis of frequency locking, so that the complexity of system design is undoubtedly increased, and the scheme adopts a pure frequency locking technology to simplify circuit design; secondly, in the prior art, a difference signal generated by a phase-locked loop is used for adjusting a hysteresis window voltage Vhys, and the scheme uses the hysteresis window voltage Vhys to adjust a Vramp signal, so that the circuit design is also simplified.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A method of frequency locking for a hysteretic mode buck converter, the method comprising:
respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal.
2. The method of claim 1, wherein the converting the reference frequency and the system sampling frequency to obtain the corresponding voltage parameters comprises:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
3. The method of claim 2, wherein the calculating from the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency comprises:
and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.
4. A method according to any of claims 1-3, characterized in that said voltage Vramp, formed from said feedback voltage Vfb, is:
the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.
5. A frequency locking apparatus for a hysteretic mode buck converter, the apparatus comprising: the device comprises a frequency conversion module, a differential current forming module and a slope control module; wherein,
the frequency conversion module is used for respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;
the differential current forming module is used for calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;
and the slope control module is used for controlling the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.
6. The apparatus of claim 5, wherein the frequency conversion module converts the reference frequency and the system sampling frequency to obtain corresponding voltage parameters, respectively, and comprises:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
7. The apparatus of claim 6, wherein the frequency conversion module comprises: two frequency detection modules with the same structure are used for converting the reference frequency and the system sampling frequency; each frequency detection module includes: the device comprises a frequency division unit, a pulse width fixing unit and a low-pass filtering unit; wherein,
the frequency dividing unit is used for executing frequency dividing operation on the reference frequency or the system sampling frequency and sending a frequency signal after frequency dividing to the pulse width fixing unit;
the pulse width fixing unit is used for generating a pulse signal with a fixed pulse width from the frequency signal after frequency division and sending the pulse signal to the low-pass filtering unit;
the low-pass filtering unit is used for generating a direct-current voltage signal according to the pulse signal with the fixed pulse width.
8. The apparatus of claim 6, wherein the differential current forming module comprises: the OTA operational amplifier, the module Z and the source follower amplifying circuit; wherein,
the two input stages of the OTA operational amplifier are a direct-current voltage signal corresponding to the reference frequency and a direct-current voltage signal corresponding to the system sampling frequency; the module Z is a compensation network of a frequency locking loop and is connected with the output end of the OTA operational amplifier; the output end of the OTA operational amplifier is also connected with the source follower amplifying circuit, and the source follower amplifying circuit is used for finally generating the differential current signal.
9. The apparatus of claim 5, wherein the slope control module comprises: MOS tubes M1, M2, M3 and M4 and a capacitor C, wherein the M1 and the M2 are P-type enhanced MOS tubes, and the M3 and the M4 are N-type enhanced MOS tubes; wherein,
the grid electrode of the M1 is connected with a PWM signal, and the source electrode is used as the input of the differential current; the grid electrode of the M2 is connected with a PWM _ N signal, and the drain electrode is used for outputting the differential current; the drain electrode of the M3 is the input of the differential current, and the grid electrode is connected with a PWM _ N signal; the grid electrode of the M4 is connected with a PWM signal, and the source electrode is used for outputting the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected and are connected with the capacitor C, and the other end of the capacitor C is connected with a feedback voltage Vfb.
10. A system on a chip, the system comprising: a frequency locking arrangement for a hysteretic mode buck converter as claimed in any of claims 5 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410775718.8A CN105763054A (en) | 2014-12-15 | 2014-12-15 | Frequency locking method and device for hysteresis-mode buck converter |
| PCT/CN2015/080466 WO2016095447A1 (en) | 2014-12-15 | 2015-06-01 | Frequency locking method and device for buck converter in hysteresis mode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410775718.8A CN105763054A (en) | 2014-12-15 | 2014-12-15 | Frequency locking method and device for hysteresis-mode buck converter |
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| CN105763054A true CN105763054A (en) | 2016-07-13 |
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| CN201410775718.8A Pending CN105763054A (en) | 2014-12-15 | 2014-12-15 | Frequency locking method and device for hysteresis-mode buck converter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109861527A (en) * | 2019-04-02 | 2019-06-07 | 无锡职业技术学院 | A kind of switch power supply system based on lag mode control |
| CN118316308A (en) * | 2024-06-07 | 2024-07-09 | 杭州元芯半导体科技有限公司 | Converter of step-down circuit, step-down conversion system and step-down conversion method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649935B (en) * | 2020-12-17 | 2024-08-30 | 圣邦微电子（北京）股份有限公司 | Switching converter and control circuit thereof |
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| US4207539A (en) * | 1976-12-29 | 1980-06-10 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
| CN101350556A (en) * | 2007-07-05 | 2009-01-21 | 英特赛尔美国股份有限公司 | Steady state frequency control of variable frequency switching regulators |
| CN103701322A (en) * | 2012-09-27 | 2014-04-02 | 三星电子株式会社 | Power supply circuit and hysteresis buck converter |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
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| US8054056B2 (en) * | 2006-09-16 | 2011-11-08 | Texas Instruments Incorporated | Frequency regulated hysteretic average current mode converter |
| US8008902B2 (en) * | 2008-06-25 | 2011-08-30 | Cirrus Logic, Inc. | Hysteretic buck converter having dynamic thresholds |
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2014
- 2014-12-15 CN CN201410775718.8A patent/CN105763054A/en active Pending
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- 2015-06-01 WO PCT/CN2015/080466 patent/WO2016095447A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4207539A (en) * | 1976-12-29 | 1980-06-10 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
| CN101350556A (en) * | 2007-07-05 | 2009-01-21 | 英特赛尔美国股份有限公司 | Steady state frequency control of variable frequency switching regulators |
| CN103701322A (en) * | 2012-09-27 | 2014-04-02 | 三星电子株式会社 | Power supply circuit and hysteresis buck converter |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109861527A (en) * | 2019-04-02 | 2019-06-07 | 无锡职业技术学院 | A kind of switch power supply system based on lag mode control |
| CN109861527B (en) * | 2019-04-02 | 2020-04-10 | 无锡职业技术学院 | Switching power supply system based on hysteresis mode control |
| CN118316308A (en) * | 2024-06-07 | 2024-07-09 | 杭州元芯半导体科技有限公司 | Converter of step-down circuit, step-down conversion system and step-down conversion method |
| CN118316308B (en) * | 2024-06-07 | 2024-09-06 | 杭州元芯半导体科技有限公司 | Converter of step-down circuit, step-down conversion system and step-down conversion method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016095447A1 (en) | 2016-06-23 |
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