CN105763054A - Frequency locking method and device for hysteresis-mode buck converter - Google Patents

Frequency locking method and device for hysteresis-mode buck converter Download PDF

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CN105763054A
CN105763054A CN201410775718.8A CN201410775718A CN105763054A CN 105763054 A CN105763054 A CN 105763054A CN 201410775718 A CN201410775718 A CN 201410775718A CN 105763054 A CN105763054 A CN 105763054A
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frequency
voltage
signal
differential current
system sampling
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方磊
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Sanechips Technology Co Ltd
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Shenzhen ZTE Microelectronics Technology Co Ltd
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Priority to PCT/CN2015/080466 priority patent/WO2016095447A1/en
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of DC power input into DC power output
    • H02M3/02Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明公开了一种用于迟滞模式降压转换器的锁频方法,该方法包括:分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制。本发明还同时公开了一种实现所述方法的装置。

The invention discloses a frequency locking method for a hysteretic mode step-down converter. The method comprises: respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters respectively corresponding to the reference frequency and the system sampling frequency; The voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency are calculated to form a differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal. The invention also discloses a device for realizing the method at the same time.

Description

一种用于迟滞模式降压转换器的锁频方法和装置A frequency locking method and device for a hysteretic mode buck converter

技术领域technical field

本发明涉及模拟开关电源技术领域,尤其涉及一种用于迟滞模式降压转换器的锁频方法和装置。The invention relates to the technical field of analog switching power supplies, in particular to a frequency locking method and device for a hysteretic mode step-down converter.

背景技术Background technique

降压型转换器在便携式设备,如:手机、数码照相机、平板电脑等中已广泛应用。这种转换器将负载调整和恢复时间作为一项重要的性能指标。迟滞模式控制技术抛开了原有的环路控制技术,抛开了带宽必须被限定在开关频率的10%左右的限制,因此可以较大的提高系统带宽,即:在相同的工作频率下有效地改善系统的瞬态响应。但是,迟滞模式本身也有一些缺点:最重要的就是系统的工作频率会随着占空比、负载大小的不同而变化,这样就会引入一些干扰方面的新问题。所以,要想更好的利用迟滞模式,必须解决频率变化的问题。Buck converters have been widely used in portable devices such as mobile phones, digital cameras, tablet computers, etc. This type of converter has load regulation and recovery time as an important performance indicator. The hysteretic mode control technology abandons the original loop control technology and the limitation that the bandwidth must be limited to about 10% of the switching frequency, so the system bandwidth can be greatly improved, that is, it is effective at the same operating frequency To improve the transient response of the system. However, the hysteretic mode itself has some disadvantages: the most important is that the operating frequency of the system will vary with the duty cycle and load size, which will introduce some new problems in terms of interference. Therefore, in order to make better use of hysteresis mode, the problem of frequency variation must be solved.

发明内容Contents of the invention

为解决现有存在的技术问题,本发明实施例提供一种用于迟滞模式降压转换器的锁频方法和装置。In order to solve the existing technical problems, an embodiment of the present invention provides a frequency locking method and device for a hysteretic mode step-down converter.

本发明实施例提供了一种用于迟滞模式降压转换器的锁频方法,该方法包括:An embodiment of the present invention provides a frequency locking method for a hysteretic mode step-down converter, the method comprising:

分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制。Converting the reference frequency and the system sampling frequency respectively to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; performing calculations based on the voltage parameters corresponding to the reference frequency and the voltage parameters corresponding to the system sampling frequency to form A differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal.

其中,所述分别对基准频率和系统采样频率进行转换,得到对应的电压参数,包括:Wherein, the reference frequency and the system sampling frequency are respectively converted to obtain corresponding voltage parameters, including:

分别对所述基准频率和系统采样频率进行相同的分频处理操作,并分别依据分频后的频率信号生成固定脉冲宽度的脉冲信号,再分别依据所述固定脉冲宽度的脉冲信号生成直流电压信号。Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

其中,所述依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,包括:Wherein, the calculation is performed based on the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

对与所述基准频率对应的直流电压信号以及与所述系统采样频率对应的直流电压信号之间的误差进行运算放大,得到差分电流信号。An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

其中,所述依据反馈电压Vfb形成的电压Vramp,为:Wherein, the voltage Vramp formed according to the feedback voltage Vfb is:

所述电压Vramp是以所述反馈电压Vfb的静态工作点为中间值而进行充放电产生的一个三角波信号,所述进行充放电的电流为所述差分电流。The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

本发明实施例还提供了一种用于迟滞模式降压转换器的锁频装置,该装置包括:频率转换模块、差分电流形成模块和斜率控制模块;其中,An embodiment of the present invention also provides a frequency locking device for a hysteretic mode step-down converter, the device includes: a frequency conversion module, a differential current forming module, and a slope control module; wherein,

所述频率转换模块,用于分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;The frequency conversion module is used to respectively convert the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;

所述差分电流形成模块,用于依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;The differential current forming module is configured to perform calculations based on voltage parameters corresponding to the reference frequency and voltage parameters corresponding to the system sampling frequency to form differential current signals;

所述斜率控制模块,用于通过所述差分电流信号对依据反馈电压Vfb形成的Vramp的斜率进行控制。The slope control module is configured to control the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.

其中,所述频率转换模块分别对基准频率和系统采样频率进行转换,得到对应的电压参数,包括:Wherein, the frequency conversion module converts the reference frequency and the system sampling frequency respectively to obtain corresponding voltage parameters, including:

分别对所述基准频率和系统采样频率进行相同的分频处理操作,并分别依据分频后的频率信号生成固定脉冲宽度的脉冲信号,再分别依据所述固定脉冲宽度的脉冲信号生成直流电压信号。Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

其中,所述频率转换模块包括:两个结构相同的频率检测模块,一个用于基准频率的转换,一个用于系统采样频率的转换;每个频率检测模块包括:分频单元、脉冲宽度固定单元和低通滤波单元;其中,Wherein, the frequency conversion module includes: two frequency detection modules with the same structure, one for the conversion of the reference frequency, and one for the conversion of the system sampling frequency; each frequency detection module includes: a frequency division unit, a pulse width fixed unit and low-pass filter unit; where,

所述分频单元,用于对基准频率或系统采样频率执行分频操作,并将分频后的频率信号发送到脉冲宽度固定单元;The frequency division unit is used to perform a frequency division operation on the reference frequency or the system sampling frequency, and send the frequency signal after frequency division to the pulse width fixing unit;

所述脉冲宽度固定单元,用于将分频后的频率信号生成固定脉冲宽度的脉冲信号,并发送到所述低通滤波单元;The pulse width fixed unit is used to generate a pulse signal with a fixed pulse width from the divided frequency signal and send it to the low-pass filter unit;

所述低通滤波单元,用于依据所述固定脉冲宽度的脉冲信号生成直流电压信号。The low-pass filtering unit is configured to generate a DC voltage signal according to the pulse signal with a fixed pulse width.

其中,所述差分电流形成模块,包括:OTA运算放大器、模块Z以及源随放大电路;其中,Wherein, the differential current forming module includes: an OTA operational amplifier, a module Z, and a source-following amplifier circuit; wherein,

所述OTA运算放大器的两个输入级为与所述基准频率对应的直流电压信号,以及与所述系统采样频率对应的直流电压信号;所述模块Z为锁频环路的补偿网络,与OTA运算放大器的输出端相连;所述OTA运算放大器的输出端还与所述源随放大电路相连,所述源随放大电路用于最终产生所述差分电流信号。The two input stages of the OTA operational amplifier are DC voltage signals corresponding to the reference frequency and DC voltage signals corresponding to the system sampling frequency; the module Z is a compensation network of a frequency-locked loop, and the OTA The output terminal of the operational amplifier is connected; the output terminal of the OTA operational amplifier is also connected with the source follower amplifier circuit, and the source follower amplifier circuit is used to finally generate the differential current signal.

其中,所述斜率控制模块,包括:MOS管M1、M2、M3和M4,以及电容C,所述M1和M2为P型增强型MOS管,M3和M4为N型增强型MOS管;其中,Wherein, the slope control module includes: MOS transistors M1, M2, M3 and M4, and a capacitor C, the M1 and M2 are P-type enhanced MOS transistors, and M3 and M4 are N-type enhanced MOS transistors; wherein,

所述M1的栅极接PWM信号,源极为所述差分电流的输入;所述M2的栅极接PWM_N信号,漏极为所述差分电流的输出;所述M3的漏极为所述差分电流的输入,栅极接PWM_N信号;所述M4的栅极接PWM信号,源极为所述差分电流的输出;所述M1的漏极、M2的源极、M3的源极以及M4的漏极间互联,且均与所述电容C相连,电容C的另一端接反馈电压Vfb。The gate of the M1 is connected to the PWM signal, and the source is the input of the differential current; the gate of the M2 is connected to the PWM_N signal, and the drain is the output of the differential current; the drain of the M3 is the input of the differential current , the gate is connected to the PWM_N signal; the gate of the M4 is connected to the PWM signal, and the source is the output of the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected, And both are connected to the capacitor C, and the other end of the capacitor C is connected to the feedback voltage Vfb.

本发明实施例还提供了一种片上系统,该系统包括:上文所述的用于迟滞模式降压转换器的锁频装置。An embodiment of the present invention also provides a system on chip, the system comprising: the frequency locking device for a hysteretic mode step-down converter as described above.

本发明实施例提供的用于迟滞模式降压转换器的锁频方法和装置,分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制。本发明实施例中,当系统采样频率小于基准频率时,形成的差分电流的值就会增加,从而使电压Vramp信号的斜率增大,从而使电压Vramp能够更快的触发基准窗口电压Vhys,增大系统工作频率;反之,则会减小系统工作频率,通过负反馈,以实现频率锁定的功能。The frequency locking method and device for the hysteretic mode step-down converter provided by the embodiments of the present invention respectively convert the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively; according to the The voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency are calculated to form a differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal. In the embodiment of the present invention, when the system sampling frequency is lower than the reference frequency, the value of the formed differential current will increase, thereby increasing the slope of the voltage Vramp signal, so that the voltage Vramp can trigger the reference window voltage Vhys faster, increasing Large system operating frequency; on the contrary, it will reduce the system operating frequency, through negative feedback, to achieve the function of frequency locking.

与现有技术相比,本发明实施例有如下优势:Compared with the prior art, the embodiments of the present invention have the following advantages:

首先,现在普遍采用的技术是利用锁相环原理来进行锁频的,在锁频基础上同时在锁相,这无疑增加了系统设计的复杂程度,而本方案是采用纯粹的锁频技术,简化了电路设计;其次,现有技术是用锁相环产生的差分信号调节迟滞窗口电压Vhys,而本方案是用该迟滞窗口电压Vhys去调节Vramp信号,同样也简化了电路设计。First of all, the technology commonly used now is to use the principle of phase-locked loop to lock the frequency. On the basis of frequency locking, the phase is locked at the same time, which undoubtedly increases the complexity of the system design. However, this solution uses pure frequency-locking technology. The circuit design is simplified; secondly, in the prior art, the differential signal generated by the phase-locked loop is used to adjust the hysteresis window voltage Vhys, while this solution uses the hysteresis window voltage Vhys to adjust the Vramp signal, which also simplifies the circuit design.

附图说明Description of drawings

在附图(其不一定是按比例绘制的)中,相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。In the drawings (which are not necessarily drawn to scale), like reference numerals may describe like parts in different views. Similar reference numbers with different letter suffixes may indicate different instances of similar components. The drawings generally illustrate the various embodiments discussed herein, by way of example and not limitation.

图1为本发明实施例所述用于迟滞模式降压转换器的锁频方法实现流程示意图;FIG. 1 is a schematic diagram of the implementation flow of the frequency locking method for the hysteretic mode step-down converter described in the embodiment of the present invention;

图2为本发明实施例所述用于迟滞模式降压转换器的锁频装置结构示意图;FIG. 2 is a schematic structural diagram of a frequency locking device for a hysteretic mode step-down converter according to an embodiment of the present invention;

图3为本发明一具体应用场景中所述锁频装置应用的整体架构图;FIG. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention;

图4为本发明实施例所述的频率检测模块的结构示意图;4 is a schematic structural diagram of a frequency detection module according to an embodiment of the present invention;

图5为本发明实施例所述的差分电流形成模块的结构示意图;5 is a schematic structural diagram of a differential current forming module according to an embodiment of the present invention;

图6为本发明实施例所述的斜率控制模块的结构示意图。FIG. 6 is a schematic structural diagram of a slope control module according to an embodiment of the present invention.

具体实施方式detailed description

本发明的实施例中,分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制,以最终达到控制系统频率的功能。In the embodiment of the present invention, the reference frequency and the system sampling frequency are respectively converted to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively; according to the voltage parameters corresponding to the reference frequency and corresponding to the system sampling frequency The voltage parameters are calculated to form a differential current signal; through the differential current signal, the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled to finally achieve the function of controlling the system frequency.

下面结合附图及具体实施例对本发明作进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

图1为本发明实施例所述用于迟滞模式降压转换器的锁频方法实现流程示意图,如图1所示,该方法包括:Fig. 1 is a schematic diagram of the implementation flow of the frequency locking method for the hysteretic mode step-down converter according to the embodiment of the present invention. As shown in Fig. 1, the method includes:

步骤101:分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;Step 101: respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;

步骤102:依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;Step 102: Calculate according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;

步骤103:通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制。Step 103: Control the slope of the voltage Vramp formed according to the feedback voltage Vfb through the differential current signal.

这样,可将所述电压Vramp与迟滞窗口电压Vhys进行比较,形成PWM信号,从而对系统工作频率进行调整控制。In this way, the voltage Vramp can be compared with the hysteresis window voltage Vhys to form a PWM signal, thereby adjusting and controlling the operating frequency of the system.

本发明实施例中,当系统采样频率小于基准频率时,形成的差分电流的值就会增加,从而使电压Vramp信号的斜率增大,从而使电压Vramp能够更快的触发基准窗口电压Vhys,增大系统工作频率;反之,则会减小系统工作频率,通过负反馈,以实现频率锁定的功能。In the embodiment of the present invention, when the system sampling frequency is lower than the reference frequency, the value of the formed differential current will increase, thereby increasing the slope of the voltage Vramp signal, so that the voltage Vramp can trigger the reference window voltage Vhys faster, increasing Large system operating frequency; on the contrary, it will reduce the system operating frequency, through negative feedback, to achieve the function of frequency locking.

在本发明实施例中,步骤101中所述分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数,包括:In the embodiment of the present invention, the reference frequency and the system sampling frequency are respectively converted in step 101 to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively, including:

分别对所述基准频率和系统采样频率进行分频处理,并分别依据分频后的频率信号生成固定脉冲宽度的脉冲信号,再分别依据所述固定脉冲宽度的脉冲信号生成直流电压信号;其中,所述对基准频率和系统采样频率进行的分频处理操作相同,例如:可采用相同的分频器进行分频。Perform frequency division processing on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths; wherein, The frequency division processing operations for the reference frequency and the system sampling frequency are the same, for example, the same frequency divider may be used for frequency division.

在本发明实施例中,步骤102中所述依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,包括:In the embodiment of the present invention, the calculation in step 102 is performed based on the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

对与所述基准频率对应的直流电压信号以及与所述系统采样频率对应的直流电压信号之间的误差进行运算放大,得到差分电流信号。An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

本发明实施例中,所述依据反馈电压Vfb形成的电压Vramp,为:In the embodiment of the present invention, the voltage Vramp formed according to the feedback voltage Vfb is:

所述电压Vramp是以所述反馈电压Vfb的静态工作点为中间值而进行充放电产生的一个三角波信号,所述进行充放电的电流为所述差分电流。The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

本发明实施例还提供了一种用于迟滞模式降压转换器的锁频装置,如图2所示,该装置包括:频率转换模块20、差分电流形成模块21和斜率控制模块22;其中,The embodiment of the present invention also provides a frequency locking device for a hysteretic mode step-down converter, as shown in FIG. 2 , the device includes: a frequency conversion module 20, a differential current forming module 21 and a slope control module 22; wherein,

所述频率转换模块20,用于分别对基准频率和系统采样频率进行转换,得到与基准频率和系统采样频率各自对应的电压参数;The frequency conversion module 20 is configured to convert the reference frequency and the system sampling frequency respectively to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively;

所述差分电流形成模块21,用于依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,形成差分电流信号;The differential current forming module 21 is configured to perform calculations based on voltage parameters corresponding to the reference frequency and voltage parameters corresponding to the system sampling frequency to form differential current signals;

所述斜率控制模块22,用于通过所述差分电流信号对依据反馈电压Vfb形成的电压Vramp的斜率进行控制。The slope control module 22 is configured to control the slope of the voltage Vramp formed according to the feedback voltage Vfb through the differential current signal.

在本发明实施例中,所述频率转换模块20分别对基准频率和系统采样频率进行转换,得到对应的电压参数,包括:In the embodiment of the present invention, the frequency conversion module 20 respectively converts the reference frequency and the system sampling frequency to obtain corresponding voltage parameters, including:

分别对所述基准频率和系统采样频率进行相同的分频处理操作,并分别依据分频后的频率信号生成固定脉冲宽度的脉冲信号,再分别依据所述固定脉冲宽度的脉冲信号生成直流电压信号。Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

在一个实施例中,如图3、4所示,所述频率转换模块20包括:两个结构相同的频率检测模块,一个用于基准频率的转换,一个用于系统采样频率的转换,每个频率检测模块包括:分频单元40、脉冲宽度固定单元41和低通滤波(LPF)单元42;其中,In one embodiment, as shown in Figures 3 and 4, the frequency conversion module 20 includes: two frequency detection modules with the same structure, one for the conversion of the reference frequency and one for the conversion of the system sampling frequency, each The frequency detection module includes: a frequency dividing unit 40, a pulse width fixing unit 41 and a low-pass filter (LPF) unit 42; wherein,

所述分频单元40,用于对基准频率或系统采样频率执行分频操作,并将分频后的频率信号发送到脉冲宽度固定单元41;The frequency division unit 40 is configured to perform a frequency division operation on the reference frequency or the system sampling frequency, and send the divided frequency signal to the pulse width fixing unit 41;

所述脉冲宽度固定单元41,用于将分频后的频率信号生成固定脉冲宽度的脉冲信号,并发送到所述低通滤波单元42;The pulse width fixing unit 41 is configured to generate a pulse signal with a fixed pulse width from the divided frequency signal and send it to the low-pass filter unit 42;

所述低通滤波单元42,用于依据所述固定脉冲宽度的脉冲信号生成直流电压信号。The low-pass filtering unit 42 is configured to generate a DC voltage signal according to the pulse signal with a fixed pulse width.

在本发明实施例中,所述差分电流形成模块21依据与所述基准频率对应的电压参数以及与所述系统采样频率对应的电压参数进行计算,包括:In the embodiment of the present invention, the differential current forming module 21 calculates according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

对与所述基准频率对应的直流电压信号以及与所述系统采样频率对应的直流电压信号之间的误差进行运算放大,得到差分电流信号。An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

在一个实施例中,如图5所示,所述差分电流形成模块21,包括:OTA运算放大器、模块Z以及源随放大电路;其中,In one embodiment, as shown in FIG. 5, the differential current forming module 21 includes: an OTA operational amplifier, a module Z, and a source-following amplifier circuit; wherein,

所述OTA运算放大器的两个输入级为与所述基准频率对应的直流电压信号,以及与所述系统采样频率对应的直流电压信号;所述模块Z为锁频环路的补偿网络,与OTA运算放大器的输出端相连;所述OTA运算放大器的输出端与所述源随放大电路相连,最终经所述源随放大电路产生所述差分电流信号。The two input stages of the OTA operational amplifier are DC voltage signals corresponding to the reference frequency and DC voltage signals corresponding to the system sampling frequency; the module Z is a compensation network of a frequency-locked loop, and the OTA The output terminal of the operational amplifier is connected; the output terminal of the OTA operational amplifier is connected with the source follower amplifying circuit, and finally the differential current signal is generated through the source follower amplifying circuit.

在本发明实施例中,所述斜率控制模块22依据反馈电压Vfb形成的电压Vramp,为:In the embodiment of the present invention, the voltage Vramp formed by the slope control module 22 according to the feedback voltage Vfb is:

所述电压Vramp是以所述反馈电压Vfb的静态工作点为中间值而进行充放电产生的一个三角波信号,所述进行充放电的电流为所述差分电流。The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

在一个实施例中,如图6所示,所述斜率控制模块,包括:MOS管M1、M2、M3和M4,以及电容C,所述M1和M2为P型增强型MOS管,M3和M4为N型增强型MOS管,M1和M4是受PWM信号控制的开关,M3和M2是受PWM_N信号控制的开关。其中,所述M1的输入端,即栅极接PWM信号,源极为所述差分电流的输入;所述M2的栅极接PWM_N信号,漏极为所述差分电流的输出;所述M3的漏极为所述差分电流的输入,栅极接PWM_N信号;所述M4的栅极接PWM信号,源极为所述差分电流的输出;所述M1的漏极、M2的源极、M3的源极以及M4的漏极间互联,且均与所述电容C相连,电容C的另一端接反馈电压Vfb。In one embodiment, as shown in FIG. 6, the slope control module includes: MOS transistors M1, M2, M3 and M4, and a capacitor C, the M1 and M2 are P-type enhanced MOS transistors, and M3 and M4 It is an N-type enhanced MOS tube, M1 and M4 are switches controlled by the PWM signal, and M3 and M2 are switches controlled by the PWM_N signal. Wherein, the input end of the M1, that is, the gate is connected to the PWM signal, and the source is the input of the differential current; the gate of the M2 is connected to the PWM_N signal, and the drain is the output of the differential current; the drain of the M3 is For the input of the differential current, the gate is connected to the PWM_N signal; the gate of the M4 is connected to the PWM signal, and the source is the output of the differential current; the drain of the M1, the source of the M2, the source of the M3 and the M4 The drains of the drains are connected to each other, and are connected to the capacitor C, and the other end of the capacitor C is connected to the feedback voltage Vfb.

本发明实施例还提供了一种片上系统,该系统包括:上文所述的用于迟滞模式降压转换器的锁频装置。An embodiment of the present invention also provides a system on chip, the system comprising: the frequency locking device for a hysteretic mode step-down converter as described above.

图3为本发明一具体应用场景中所述锁频装置应用的整体架构图,如图3所示,所述锁频装置主要由三部分组成:Fig. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention. As shown in Fig. 3, the frequency locking device is mainly composed of three parts:

第一部分由两个结构相同的频率检测模块组成,对应于图2中所述频率转换模块20,用来分别将基准频率和系统采样频率转换成电压参数后提供给所述Gm单元;The first part consists of two frequency detection modules with the same structure, corresponding to the frequency conversion module 20 described in Figure 2, which is used to convert the reference frequency and the system sampling frequency into voltage parameters and provide them to the Gm unit;

第二部分是一个跨导(GM)模块,对应于图2中所述差分电流形成模块21,用于产生调节Ramp电压的电流参数;The second part is a transconductance (GM) module, corresponding to the differential current forming module 21 described in FIG. 2, for generating current parameters for adjusting the Ramp voltage;

第三部分是一个Ramp模块,对应于图2中所述斜率控制模块22,主要作用是在反馈电压Vfb的直流参量基础上,产生一个随系统工作频率变化的Ramp电压参数,它可以增加比较器的精度,也可以通过锁频环路调整系统工作频率;The third part is a Ramp module, which corresponds to the slope control module 22 in Fig. 2, and its main function is to generate a Ramp voltage parameter that changes with the system operating frequency on the basis of the DC parameter of the feedback voltage Vfb, which can increase the comparator The accuracy of the system can also be adjusted through the frequency-locked loop;

另外,图3中还包括迟滞模式降压转换器所需要的快速响应的PWM比较器以及驱动控制模块。In addition, Figure 3 also includes a fast-response PWM comparator and a drive control module required by the hysteretic mode buck converter.

如图3所示,迟滞模式系统以一个PWM比较器为核心,将输出电压控制在窗口电压范围内,从而控制了输出电压和输出电压纹波大小。由于输出反馈电压纹波非常小,所以需要Ramp模块来放大纹波,从而可以改善系统的抗干扰能力,减少系统工作频率的抖动。另一方面,由于不同的输入电压、输出电压或电感等电路参数的不同,系统工作频率也会不同,因此锁频环路也是通过Ramp模块并入系统控制环路的。具体的控制方式为,频率检测模块会将基准频率和系统采样频率分别进行处理,产生的电压通过GM模块形成差分电流,通过Ramp模块去影响电压Vramp的斜率,电压Vramp的斜率越大,系统工作频率也就越快;电压Vramp的斜率越小,系统工作频率也就越慢,从而在不同的电路参数条件下通过负反馈环路去调节系统工作频率,使其稳定在基准频率附近。As shown in Figure 3, the hysteretic mode system uses a PWM comparator as the core to control the output voltage within the window voltage range, thereby controlling the output voltage and output voltage ripple. Since the output feedback voltage ripple is very small, the Ramp module is needed to amplify the ripple, which can improve the anti-interference ability of the system and reduce the jitter of the system operating frequency. On the other hand, due to different circuit parameters such as different input voltages, output voltages, or inductances, the operating frequency of the system will also be different, so the frequency-locked loop is also incorporated into the system control loop through the Ramp module. The specific control method is that the frequency detection module will process the reference frequency and the system sampling frequency separately, and the generated voltage will form a differential current through the GM module, and the slope of the voltage Vramp will be affected by the Ramp module. The greater the slope of the voltage Vramp, the system will work The faster the frequency; the smaller the slope of the voltage Vramp, the slower the system operating frequency, so that the system operating frequency can be adjusted through the negative feedback loop under different circuit parameter conditions to stabilize it near the reference frequency.

如图4所示,所述每个频率检测模块包括:分频单元40、脉冲宽度固定单元41和低通滤波(LPF)单元42。由于每个频率检测单元的结构相同,这里以对应于基准频率的频率检测单元为例进行说明。As shown in FIG. 4 , each frequency detection module includes: a frequency dividing unit 40 , a pulse width fixing unit 41 and a low-pass filter (LPF) unit 42 . Since each frequency detection unit has the same structure, the frequency detection unit corresponding to the reference frequency is taken as an example for illustration.

基准频率信号首先进入分频单元,分频单元的主要的目的是调整输入信号频率的大小,使后级的脉冲宽度固定单元能够满足更大频率范围的采样,只要基准频率检测和系统工作频率采用相同的分频器即可;分频后的频率信号用于产生固定脉冲宽度的脉冲信号,这样,在不同频率时,就会产生不同的DutyCycle输入给低通滤波单元,从而产生对应的直流输出电压Vf,Vf信号直接反应了频率大小。The reference frequency signal first enters the frequency division unit. The main purpose of the frequency division unit is to adjust the frequency of the input signal, so that the pulse width fixed unit of the subsequent stage can meet the sampling of a wider frequency range. As long as the reference frequency detection and system operating frequency adopt The same frequency divider is enough; the frequency signal after frequency division is used to generate a pulse signal with a fixed pulse width, so that at different frequencies, different DutyCycle inputs will be generated to the low-pass filter unit, thereby generating a corresponding DC output The voltage Vf, the Vf signal directly reflects the frequency.

可见,本发明实施例的频率检测过程使电路设计更加简单,不用使用锁相环路模块,同时使环路分析更加简单。It can be seen that the frequency detection process of the embodiment of the present invention simplifies the circuit design without using a phase-locked loop module, and at the same time simplifies the loop analysis.

图5为图3中所示跨导模块,即所述差分电流形成模块21的结构示意图。所述差分电流形成模块将两个频率检测模块产生的反映频率高低的电压信号输入给跨导模块,对两个信号的误差进行运算放大,产生差分电流输出信号。如图5所示,在一个实施例中,可以直接用跨导运算放大电路,即图5中所示OTA运算放大器作为跨导模块的输入级,模块Z为锁频环路的补偿网络,后级接由M1、M2与M3以及R组成的源随放大电路,所述源随放大电路为现有技术,此处不再详述,最后经源随放大电路产生所需要的输出误差电流信号。这里,可以通过调节电阻R的大小和M2与M3镜像比例,也可以设置OTA运算放大器的增益,这些参数都会影响整个锁频环路的增益。FIG. 5 is a schematic structural diagram of the transconductance module shown in FIG. 3 , that is, the differential current forming module 21 . The differential current forming module inputs the voltage signals reflecting the high and low frequencies generated by the two frequency detection modules to the transconductance module, performs operational amplification on the error of the two signals, and generates a differential current output signal. As shown in Figure 5, in one embodiment, the transconductance operational amplifier circuit can be directly used, that is, the OTA operational amplifier shown in Figure 5 is used as the input stage of the transconductance module, and module Z is the compensation network of the frequency-locked loop. A source-following amplifying circuit composed of M1, M2, M3 and R is connected in stages. The source-following amplifying circuit is a prior art and will not be described in detail here. Finally, the required output error current signal is generated by the source-following amplifying circuit. Here, the gain of the OTA operational amplifier can also be set by adjusting the size of the resistor R and the mirror ratio of M2 and M3, and these parameters will affect the gain of the entire frequency-locked loop.

之后,用上述差分电流信号去控制所述Ramp模块,从而控制电压Vramp信号的斜率,最终输出的Vramp信号是在Vfb直流电压的直流工作点的基础上产生的,然后与基准电压窗口比较,形成PWM信号,从而对系统工作频率进行调整控制。如图6所示,Vramp电压是以Vfb电压的静态工作点为中间值而进行充放电产生的一个三角波信号,充放电的电流均为所述跨导模块的输出误差电流ΔI,M1和M2、M3和M4分别是受PWM信号和PWM_N信号控制的开关,去控制图6中所述电容C的充放电,当降压转换器系统给图3中所述电感L充电时,M1和M3打开,M2和M4关断,Ramp模块给图6中所述电容C充电;当系统给电感L放电时,M1和M3关断,M2和M4打开,Ramp模块给图6中所述电容C放电,这样产生的电压Vramp信号受系统工作频率与基准工作频率差的影响而不同,从而调整系统工作频率。After that, use the above differential current signal to control the Ramp module, thereby controlling the slope of the voltage Vramp signal, and the final output Vramp signal is generated on the basis of the DC operating point of the Vfb DC voltage, and then compared with the reference voltage window to form PWM signal to adjust and control the operating frequency of the system. As shown in Figure 6, the Vramp voltage is a triangular wave signal generated by charging and discharging with the static operating point of the Vfb voltage as the intermediate value, and the charging and discharging currents are the output error currents ΔI, M1 and M2, of the transconductance module. M3 and M4 are switches controlled by the PWM signal and the PWM_N signal respectively to control the charging and discharging of the capacitor C in Figure 6. When the step-down converter system charges the inductor L in Figure 3, M1 and M3 are turned on. M2 and M4 are turned off, and the Ramp module charges the capacitor C in Figure 6; when the system discharges the inductor L, M1 and M3 are turned off, M2 and M4 are turned on, and the Ramp module discharges the capacitor C in Figure 6, so The generated voltage Vramp signal is different due to the difference between the system operating frequency and the reference operating frequency, thereby adjusting the system operating frequency.

当系统工作频率小于基准频率时,跨导模块输出的电流误差信号就会增加,从而使Vramp信号斜率增大,从而使Vramp能够更快的触发迟滞窗口电压Vhys,增大系统工作频率;反之,则会减小系统工作频率,通过负反馈,以实现频率锁定的功能。When the system operating frequency is lower than the reference frequency, the current error signal output by the transconductance module will increase, thereby increasing the slope of the Vramp signal, so that Vramp can trigger the hysteresis window voltage Vhys faster and increase the system operating frequency; on the contrary, It will reduce the operating frequency of the system, and realize the function of frequency locking through negative feedback.

本发明实施例与现有的技术相比,有两个不同之处:首先,现在普遍采用的技术是利用锁相环原理来进行锁频的,在锁频基础上同时在锁相,这无疑增加了系统设计的复杂程度,而本方案是采用纯粹的锁频技术,简化了电路设计;其次,现有技术是用锁相环产生的差分信号调节迟滞窗口电压Vhys,而本方案是用该迟滞窗口电压Vhys去调节Vramp信号,同样也简化了电路设计。Compared with the existing technology, the embodiment of the present invention has two differences: firstly, the technology commonly used now uses the principle of phase-locked loop to lock the frequency, and locks the phase at the same time on the basis of frequency locking, which is undoubtedly Increased the complexity of the system design, and this program uses pure frequency locking technology, which simplifies the circuit design; secondly, the existing technology uses the differential signal generated by the phase-locked loop to adjust the hysteresis window voltage Vhys, and this program uses this The hysteresis window voltage Vhys is used to adjust the Vramp signal, which also simplifies the circuit design.

本领域内的技术人员应明白,本发明的实施例可提供为方法、系统、或计算机程序产品。因此,本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且,本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) having computer-usable program code embodied therein.

本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器,使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中,使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品,该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上,使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理,从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

以上所述,仅为本发明的较佳实施例而已,并非用于限定本发明的保护范围。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (10)

1. A method of frequency locking for a hysteretic mode buck converter, the method comprising:
respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal.
2. The method of claim 1, wherein the converting the reference frequency and the system sampling frequency to obtain the corresponding voltage parameters comprises:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
3. The method of claim 2, wherein the calculating from the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency comprises:
and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.
4. A method according to any of claims 1-3, characterized in that said voltage Vramp, formed from said feedback voltage Vfb, is:
the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.
5. A frequency locking apparatus for a hysteretic mode buck converter, the apparatus comprising: the device comprises a frequency conversion module, a differential current forming module and a slope control module; wherein,
the frequency conversion module is used for respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;
the differential current forming module is used for calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;
and the slope control module is used for controlling the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.
6. The apparatus of claim 5, wherein the frequency conversion module converts the reference frequency and the system sampling frequency to obtain corresponding voltage parameters, respectively, and comprises:
and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.
7. The apparatus of claim 6, wherein the frequency conversion module comprises: two frequency detection modules with the same structure are used for converting the reference frequency and the system sampling frequency; each frequency detection module includes: the device comprises a frequency division unit, a pulse width fixing unit and a low-pass filtering unit; wherein,
the frequency dividing unit is used for executing frequency dividing operation on the reference frequency or the system sampling frequency and sending a frequency signal after frequency dividing to the pulse width fixing unit;
the pulse width fixing unit is used for generating a pulse signal with a fixed pulse width from the frequency signal after frequency division and sending the pulse signal to the low-pass filtering unit;
the low-pass filtering unit is used for generating a direct-current voltage signal according to the pulse signal with the fixed pulse width.
8. The apparatus of claim 6, wherein the differential current forming module comprises: the OTA operational amplifier, the module Z and the source follower amplifying circuit; wherein,
the two input stages of the OTA operational amplifier are a direct-current voltage signal corresponding to the reference frequency and a direct-current voltage signal corresponding to the system sampling frequency; the module Z is a compensation network of a frequency locking loop and is connected with the output end of the OTA operational amplifier; the output end of the OTA operational amplifier is also connected with the source follower amplifying circuit, and the source follower amplifying circuit is used for finally generating the differential current signal.
9. The apparatus of claim 5, wherein the slope control module comprises: MOS tubes M1, M2, M3 and M4 and a capacitor C, wherein the M1 and the M2 are P-type enhanced MOS tubes, and the M3 and the M4 are N-type enhanced MOS tubes; wherein,
the grid electrode of the M1 is connected with a PWM signal, and the source electrode is used as the input of the differential current; the grid electrode of the M2 is connected with a PWM _ N signal, and the drain electrode is used for outputting the differential current; the drain electrode of the M3 is the input of the differential current, and the grid electrode is connected with a PWM _ N signal; the grid electrode of the M4 is connected with a PWM signal, and the source electrode is used for outputting the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected and are connected with the capacitor C, and the other end of the capacitor C is connected with a feedback voltage Vfb.
10. A system on a chip, the system comprising: a frequency locking arrangement for a hysteretic mode buck converter as claimed in any of claims 5 to 9.
CN201410775718.8A 2014-12-15 2014-12-15 Frequency locking method and device for hysteresis-mode buck converter Pending CN105763054A (en)

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PCT/CN2015/080466 WO2016095447A1 (en) 2014-12-15 2015-06-01 Frequency locking method and device for buck converter in hysteresis mode

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