CN105763054A - Frequency locking method and device for hysteresis-mode buck converter - Google Patents
Frequency locking method and device for hysteresis-mode buck converter Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
The invention discloses a frequency locking method for a hysteresis-mode buck converter. The method comprises the following steps: carrying out conversion on reference frequency and system sampling frequency to obtain voltage parameters corresponding to the reference frequency and system sampling frequency respectively; carrying out calculation according to the voltage parameters corresponding to the reference frequency and the voltage parameters corresponding to the system sampling frequency to obtain differential current signals; and controlling a slope of a voltage Vramp formed based on a feedback voltage Vfb through the differential current signals. The invention also discloses a device for realizing the method above.
Description
Technical field
The present invention relates to analog switched power supply technical field, particularly relate to a kind of locking method for lag mode step-down controller and device.
Background technology
Buck converter at portable set, as: mobile phone, digital camera, panel computer etc. have been widely used.This transducer using adjustment of load and recovery time as important performance indications.Lag mode controls technology and has cast aside original loop control technology, cast aside the restriction that bandwidth must be limited at about the 10% of switching frequency, therefore raising system bandwidth that can be bigger, it may be assumed that effectively improve system's transient response under identical operating frequency.But, lag mode itself also has some shortcomings: most important is exactly that the operating frequency of system can change along with dutycycle, the difference of load, thus can introduce the new problem of some interference aspects.So, want better to utilize lag mode, it is necessary to the problem solving frequency change.
Summary of the invention
For solving the technical problem of existing existence, the embodiment of the present invention provides a kind of locking method for lag mode step-down controller and device.
Embodiments providing a kind of locking method for lag mode step-down controller, the method includes:
Respectively reference frequency and system sampling frequency are changed, obtain self-corresponding voltage parameter each with reference frequency and system sampling frequency；It is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；By described differential current signal, the slope of the voltage Vramp according to feedback voltage Vfb formation is controlled.
Wherein, described respectively reference frequency and system sampling frequency are changed, obtain the voltage parameter of correspondence, including:
Respectively described reference frequency and system sampling frequency are carried out identical scaling down processing operation, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively.
Wherein, voltage parameter and the voltage parameter corresponding with described system sampling frequency that described foundation is corresponding with described reference frequency are calculated, including:
Error between the d. c. voltage signal corresponding with described reference frequency and the d. c. voltage signal corresponding with described system sampling frequency is carried out operation amplifier, obtains differential current signal.
Wherein, the described voltage Vramp formed according to feedback voltage Vfb, for:
Described voltage Vramp is the triangular signal carrying out discharge and recharge generation with the quiescent point of described feedback voltage Vfb for intermediate value, described in carry out the electric current of discharge and recharge be described difference current.
The embodiment of the present invention additionally provides a kind of frequency locking device for lag mode step-down controller, and this device includes: frequency translation module, difference current form module and slop control module；Wherein,
Described frequency translation module, for respectively reference frequency and system sampling frequency being changed, obtains self-corresponding voltage parameter each with reference frequency and system sampling frequency；
Described difference current forms module, for being calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；
Described slop control module, for being controlled the slope of the Vramp according to feedback voltage Vfb formation by described differential current signal.
Wherein, reference frequency and system sampling frequency are changed by described frequency translation module respectively, obtain the voltage parameter of correspondence, including:
Respectively described reference frequency and system sampling frequency are carried out identical scaling down processing operation, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively.
Wherein, described frequency translation module includes: the frequency detection module that two structures are identical, a conversion for reference frequency, a conversion for system sampling frequency；Each frequency detection module includes: frequency unit, pulse width fixed cell and low-pass filter unit；Wherein,
Described frequency unit, for reference frequency or system sampling frequency perform divide operation, and is sent to pulse width fixed cell by the frequency signal after frequency dividing；
Described pulse width fixed cell, for the frequency signal after frequency dividing generates the pulse signal of fixed pulse width, and is sent to described low-pass filter unit；
Described low-pass filter unit, generates d. c. voltage signal for the pulse signal according to described fixed pulse width.
Wherein, described difference current forms module, including: OTA operational amplifier, module Z and source are with amplifying circuit；Wherein,
Two input stages of described OTA operational amplifier are the d. c. voltage signal corresponding with described reference frequency, and the d. c. voltage signal corresponding with described system sampling frequency；Described module Z is the compensation network of frequency-locked loop, is connected with the outfan of OTA operational amplifier；The outfan of described OTA operational amplifier is also connected with amplifying circuit with described source, and described source produces described differential current signal with amplifying circuit for final.
Wherein, described slop control module, including: metal-oxide-semiconductor M1, M2, M3 and M4, and electric capacity C, described M1 and M2 is P type enhancement mode metal-oxide-semiconductor, and M3 and M4 is N-type enhancement mode metal-oxide-semiconductor；Wherein,
The grid of described M1 connects pwm signal, and source electrode is the input of described difference current；The grid of described M2 connects PWM_N signal, and drain the output into described difference current；The input that drain electrode is described difference current of described M3, grid connects PWM_N signal；The grid of described M4 connects pwm signal, and source electrode is the output of described difference current；Interconnect between the drain electrode of described M1, the source electrode of M2, the source electrode of M3 and the drain electrode of M4, and be all connected with described electric capacity C, another termination feedback voltage Vfb of electric capacity C.
The embodiment of the present invention additionally provides a kind of SOC(system on a chip), and this system includes: described above for the frequency locking device of lag mode step-down controller.
The locking method for lag mode step-down controller of embodiment of the present invention offer and device, change reference frequency and system sampling frequency respectively, obtain self-corresponding voltage parameter each with reference frequency and system sampling frequency；It is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；By described differential current signal, the slope of the voltage Vramp according to feedback voltage Vfb formation is controlled.In the embodiment of the present invention, when system sampling frequency is less than reference frequency, the value of the difference current of formation will increase, so that the slope of voltage Vramp signal increases, so that voltage Vramp can trigger benchmark window voltage Vhys faster, increase system operating frequency；Otherwise, then system operating frequency can be reduced, by negative feedback, to realize the function of frequency lock.
Compared with prior art, the embodiment of the present invention has following advantage:
First, now commonly used technology utilizes principle of phase lock loop to carry out frequency locking, and simultaneously phase-locked on frequency locking basis, this adds the complexity of system design undoubtedly, and this programme is to adopt pure frequency locking technology, simplifies circuit design；Secondly, prior art is that the differential signal produced with phaselocked loop regulates retarding window voltage Vhys, and this programme is to remove to regulate Vramp signal with this retarding window voltage Vhys, also simplify circuit design equally.
Accompanying drawing explanation
In accompanying drawing (it is not necessarily drawn to scale), similar accompanying drawing labelling can at parts similar described in different views.The similar reference numerals with different letter suffix can represent the different examples of similar component.Accompanying drawing generally shows each embodiment discussed herein by way of example and not limitation.
Fig. 1 realizes schematic flow sheet for the locking method of lag mode step-down controller described in the embodiment of the present invention；
Fig. 2 is the frequency locking device structural representation described in the embodiment of the present invention for lag mode step-down controller；
Fig. 3 is the integrated stand composition of the application of frequency locking device described in the concrete application scenarios of the present invention one；
Fig. 4 is the structural representation of the frequency detection module described in the embodiment of the present invention；
Fig. 5 is the structural representation that the difference current described in the embodiment of the present invention forms module；
Fig. 6 is the structural representation of the slop control module described in the embodiment of the present invention.
Detailed description of the invention
In embodiments of the invention, respectively reference frequency and system sampling frequency are changed, obtain self-corresponding voltage parameter each with reference frequency and system sampling frequency；It is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；By described differential current signal, the slope of the voltage Vramp according to feedback voltage Vfb formation is controlled, to be finally reached the function controlling system frequency.
Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
Fig. 1 realizes schematic flow sheet for the locking method of lag mode step-down controller described in the embodiment of the present invention, as it is shown in figure 1, the method includes:
Step 101: respectively reference frequency and system sampling frequency are changed, obtains self-corresponding voltage parameter each with reference frequency and system sampling frequency；
Step 102: be calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；
Step 103: the slope of the voltage Vramp according to feedback voltage Vfb formation is controlled by described differential current signal.
So, described voltage Vramp and retarding window voltage Vhys can be compared, form pwm signal, thus being adjusted system operating frequency controlling.
In the embodiment of the present invention, when system sampling frequency is less than reference frequency, the value of the difference current of formation will increase, so that the slope of voltage Vramp signal increases, so that voltage Vramp can trigger benchmark window voltage Vhys faster, increase system operating frequency；Otherwise, then system operating frequency can be reduced, by negative feedback, to realize the function of frequency lock.
In embodiments of the present invention, respectively reference frequency and system sampling frequency are changed described in step 101, obtain self-corresponding voltage parameter each with reference frequency and system sampling frequency, including:
Respectively described reference frequency and system sampling frequency are carried out scaling down processing, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively；It is wherein, described that reference frequency is identical with the scaling down processing operation that system sampling frequency carries out, for instance: identical frequency divider can be adopted to divide.
In embodiments of the present invention, it is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency described in step 102, including:
Error between the d. c. voltage signal corresponding with described reference frequency and the d. c. voltage signal corresponding with described system sampling frequency is carried out operation amplifier, obtains differential current signal.
In the embodiment of the present invention, the described voltage Vramp formed according to feedback voltage Vfb, for:
Described voltage Vramp is the triangular signal carrying out discharge and recharge generation with the quiescent point of described feedback voltage Vfb for intermediate value, described in carry out the electric current of discharge and recharge be described difference current.
The embodiment of the present invention additionally provides a kind of frequency locking device for lag mode step-down controller, as in figure 2 it is shown, this device includes: frequency translation module 20, difference current form module 21 and slop control module 22；Wherein,
Described frequency translation module 20, for respectively reference frequency and system sampling frequency being changed, obtains self-corresponding voltage parameter each with reference frequency and system sampling frequency；
Described difference current forms module 21, for being calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；
Described slop control module 22, for being controlled the slope of the voltage Vramp according to feedback voltage Vfb formation by described differential current signal.
In embodiments of the present invention, reference frequency and system sampling frequency are changed by described frequency translation module 20 respectively, obtain the voltage parameter of correspondence, including:
Respectively described reference frequency and system sampling frequency are carried out identical scaling down processing operation, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively.
In one embodiment, as shown in Figure 3,4, described frequency translation module 20 includes: the frequency detection module that two structures are identical, one conversion for reference frequency, one conversion for system sampling frequency, each frequency detection module includes: frequency unit 40, pulse width fixed cell 41 and low-pass filtering (LPF) unit 42；Wherein,
Described frequency unit 40, for reference frequency or system sampling frequency perform divide operation, and is sent to pulse width fixed cell 41 by the frequency signal after frequency dividing；
Described pulse width fixed cell 41, for the frequency signal after frequency dividing generates the pulse signal of fixed pulse width, and is sent to described low-pass filter unit 42；
Described low-pass filter unit 42, generates d. c. voltage signal for the pulse signal according to described fixed pulse width.
In embodiments of the present invention, described difference current forms module 21 and is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, including:
Error between the d. c. voltage signal corresponding with described reference frequency and the d. c. voltage signal corresponding with described system sampling frequency is carried out operation amplifier, obtains differential current signal.
In one embodiment, as it is shown in figure 5, described difference current forms module 21, including: OTA operational amplifier, module Z and source are with amplifying circuit；Wherein,
Two input stages of described OTA operational amplifier are the d. c. voltage signal corresponding with described reference frequency, and the d. c. voltage signal corresponding with described system sampling frequency；Described module Z is the compensation network of frequency-locked loop, is connected with the outfan of OTA operational amplifier；The outfan of described OTA operational amplifier is connected with amplifying circuit with described source, finally produces described differential current signal through described source with amplifying circuit.
In embodiments of the present invention, the voltage Vramp that described slop control module 22 is formed according to feedback voltage Vfb, for:
Described voltage Vramp is the triangular signal carrying out discharge and recharge generation with the quiescent point of described feedback voltage Vfb for intermediate value, described in carry out the electric current of discharge and recharge be described difference current.
In one embodiment, as shown in Figure 6, described slop control module, including: metal-oxide-semiconductor M1, M2, M3 and M4, and electric capacity C, described M1 and M2 are P type enhancement mode metal-oxide-semiconductor, M3 and M4 is N-type enhancement mode metal-oxide-semiconductor, M1 and M4 is the switch controlled by pwm signal, and M3 and M2 is the switch controlled by PWM_N signal.Wherein, the input of described M1, namely grid connects pwm signal, and source electrode is the input of described difference current；The grid of described M2 connects PWM_N signal, and drain the output into described difference current；The input that drain electrode is described difference current of described M3, grid connects PWM_N signal；The grid of described M4 connects pwm signal, and source electrode is the output of described difference current；Interconnect between the drain electrode of described M1, the source electrode of M2, the source electrode of M3 and the drain electrode of M4, and be all connected with described electric capacity C, another termination feedback voltage Vfb of electric capacity C.
The embodiment of the present invention additionally provides a kind of SOC(system on a chip), and this system includes: described above for the frequency locking device of lag mode step-down controller.
Fig. 3 is the integrated stand composition of the application of frequency locking device described in the concrete application scenarios of the present invention one, as it is shown on figure 3, described frequency locking device is mainly made up of three parts:
Part I is made up of the frequency detection module that two structures are identical, corresponding to frequency translation module 20 described in Fig. 2, is supplied to described Gm unit after being used for converting reference frequency and system sampling frequency to voltage parameter respectively；
Part II is mutual conductance (GM) module, forms module 21 corresponding to difference current described in Fig. 2, for producing to regulate the current parameters of Ramp voltage；
Part III is a Ramp module, corresponding to slop control module described in Fig. 2 22, Main Function is on the direct current parameter basis of feedback voltage Vfb, produce a Ramp voltage parameter with system operating frequency change, it can increase the precision of comparator, it is also possible to adjusts system operating frequency by frequency-locked loop；
It addition, Fig. 3 also includes the PWM comparator quickly responded required for lag mode step-down controller and drive control module.
As it is shown on figure 3, lag mode system is with a PWM comparator for core, by output voltage control within the scope of window voltage, thus controlling output voltage and output voltage ripple size.Owing to output feedack voltage ripple is very little, so needing Ramp module to amplify ripple, such that it is able to improve the capacity of resisting disturbance of system, reduce the shake of system operating frequency.On the other hand, due to the difference of the circuit parameters such as different input voltages, output voltage or inductance, system operating frequency also can be different, and therefore frequency-locked loop is also incorporated to system control loop by Ramp module.Concrete control mode is, reference frequency and system sampling frequency can be respectively processed by frequency detection module, and the voltage of generation forms difference current by GM module, removes to affect the slope of voltage Vramp by Ramp module, the slope of voltage Vramp is more big, and system operating frequency is also more fast；The slope of voltage Vramp is more little, and system operating frequency is also more slow, thus going to regulate system operating frequency by feedback loop when different circuit parameters so that it is stable near reference frequency.
As shown in Figure 4, described each frequency detection module includes: frequency unit 40, pulse width fixed cell 41 and low-pass filtering (LPF) unit 42.Owing to the structure of each frequency detecting unit is identical, illustrate for the frequency detecting unit corresponding to reference frequency here.
Reference frequency signal initially enters frequency unit, the main purpose of frequency unit is the size adjusting frequency input signal, the pulse width fixed cell making rear class disclosure satisfy that the sampling of bigger frequency range, as long as reference frequency detection adopts identical frequency divider with system operating frequency；Frequency signal after frequency dividing is for producing the pulse signal of fixed pulse width, so, when different frequency, different DutyCycle will be produced and input to low-pass filter unit, thus producing corresponding VD Vf, Vf signal direct reaction frequency size.
Visible, the frequency detecting process of the embodiment of the present invention makes circuit design simpler, need not use lock-oriented circuit module, makes loop analysis simpler simultaneously.
Fig. 5 is transconductance modulator shown in Fig. 3, and namely described difference current forms the structural representation of module 21.Described difference current forms the voltage signal of the reflection frequency height that two frequency detection module are produced by module and inputs to transconductance modulator, and the error of two signals is carried out operation amplifier, produces difference current output signal.As shown in Figure 5, in one embodiment, can directly use operational transconductance amplifying circuit, namely OTA operational amplifier shown in Fig. 5 is as the input stage of transconductance modulator, module Z is the compensation network of frequency-locked loop, and rear class connects the source being made up of M1, M2 and M3 and R with amplifying circuit, and described source is prior art with amplifying circuit, no longer describe in detail herein, after, produce required output error current signal through source with amplifying circuit.Here it is possible to by the size and M2 and the M3 mirroring ratios that regulate resistance R, it is also possible to arranging the gain of OTA operational amplifier, these parameters all can affect the gain of whole frequency-locked loop.
Afterwards, go to control described Ramp module by above-mentioned differential current signal, thus controlling the slope of voltage Vramp signal, the Vramp signal of final output is to produce on the basis of the DC point of Vfb DC voltage, then compare with reference voltage window, form pwm signal, thus being adjusted system operating frequency controlling.As shown in Figure 6, Vramp voltage is the triangular signal carrying out discharge and recharge generation with the quiescent point of Vfb voltage for intermediate value, the electric current of discharge and recharge is the output error electric current Δ I of described transconductance modulator, M1 and M2, M3 and M4 are the switch controlled by pwm signal and PWM_N signal respectively, going to control the discharge and recharge of electric capacity C described in Fig. 6, when buck converter systems charges to inductance L described in Fig. 3, M1 and M3 opens, M2 and M4 turns off, and Ramp module is charged to electric capacity C described in Fig. 6；When system is discharged to inductance L, M1 and M3 turns off, and M2 and M4 opens, and Ramp module is discharged to electric capacity C described in Fig. 6, and the voltage Vramp signal so produced is subject to system operating frequency and the impact of benchmark job difference on the frequency and different, thus adjusting system operating frequency.
When system operating frequency is less than reference frequency, the current error signal of transconductance modulator output will increase, so that Vramp signal slope increases, so that Vramp can trigger retarding window voltage Vhys faster, increases system operating frequency；Otherwise, then system operating frequency can be reduced, by negative feedback, to realize the function of frequency lock.
The embodiment of the present invention is compared with prior art, there are two differences: first, now commonly used technology utilizes principle of phase lock loop to carry out frequency locking, simultaneously phase-locked on frequency locking basis, this adds the complexity of system design undoubtedly, and this programme is to adopt pure frequency locking technology, simplify circuit design；Secondly, prior art is that the differential signal produced with phaselocked loop regulates retarding window voltage Vhys, and this programme is to remove to regulate Vramp signal with this retarding window voltage Vhys, also simplify circuit design equally.
Those skilled in the art are it should be appreciated that embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of hardware embodiment, software implementation or the embodiment in conjunction with software and hardware aspect.And, the present invention can adopt the form at one or more upper computer programs implemented of computer-usable storage medium (including but not limited to disk memory and optical memory etc.) wherein including computer usable program code.
The present invention is that flow chart and/or block diagram with reference to method according to embodiments of the present invention, equipment (system) and computer program describe.It should be understood that can by the combination of the flow process in each flow process in computer program instructions flowchart and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can be provided to produce a machine to the processor of general purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device so that the instruction performed by the processor of computer or other programmable data processing device is produced for realizing the device of function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions may be alternatively stored in and can guide in the computer-readable memory that computer or other programmable data processing device work in a specific way, the instruction making to be stored in this computer-readable memory produces to include the manufacture of command device, and this command device realizes the function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, make on computer or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computer or other programmable devices provides for realizing the step of function specified in one flow process of flow chart or multiple flow process and/or one square frame of block diagram or multiple square frame.
The above, be only presently preferred embodiments of the present invention, is not intended to limit protection scope of the present invention.
Claims (10)
1. the locking method for lag mode step-down controller, it is characterised in that the method includes:
Respectively reference frequency and system sampling frequency are changed, obtain self-corresponding voltage parameter each with reference frequency and system sampling frequency；It is calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；By described differential current signal, the slope of the voltage Vramp according to feedback voltage Vfb formation is controlled.
2. method according to claim 1, it is characterised in that described respectively reference frequency and system sampling frequency are changed, obtains the voltage parameter of correspondence, including:
Respectively described reference frequency and system sampling frequency are carried out identical scaling down processing operation, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively.
3. method according to claim 2, it is characterised in that voltage parameter and the voltage parameter corresponding with described system sampling frequency that described foundation is corresponding with described reference frequency are calculated, including:
Error between the d. c. voltage signal corresponding with described reference frequency and the d. c. voltage signal corresponding with described system sampling frequency is carried out operation amplifier, obtains differential current signal.
4. the method according to any one of claim 1-3, it is characterised in that the described voltage Vramp formed according to feedback voltage Vfb, for:
Described voltage Vramp is the triangular signal carrying out discharge and recharge generation with the quiescent point of described feedback voltage Vfb for intermediate value, described in carry out the electric current of discharge and recharge be described difference current.
5. the frequency locking device for lag mode step-down controller, it is characterised in that this device includes: frequency translation module, difference current form module and slop control module；Wherein,
Described frequency translation module, for respectively reference frequency and system sampling frequency being changed, obtains self-corresponding voltage parameter each with reference frequency and system sampling frequency；
Described difference current forms module, for being calculated according to the voltage parameter corresponding with described reference frequency and the voltage parameter corresponding with described system sampling frequency, forms differential current signal；
Described slop control module, for being controlled the slope of the Vramp according to feedback voltage Vfb formation by described differential current signal.
6. device according to claim 5, it is characterised in that reference frequency and system sampling frequency are changed by described frequency translation module respectively, obtains the voltage parameter of correspondence, including:
Respectively described reference frequency and system sampling frequency are carried out identical scaling down processing operation, and respectively according to the pulse signal of the frequency signal generation fixed pulse width after frequency dividing, then generate d. c. voltage signal according to the pulse signal of described fixed pulse width respectively.
7. device according to claim 6, it is characterised in that described frequency translation module includes: the frequency detection module that two structures are identical, a conversion for reference frequency, a conversion for system sampling frequency；Each frequency detection module includes: frequency unit, pulse width fixed cell and low-pass filter unit；Wherein,
Described frequency unit, for reference frequency or system sampling frequency perform divide operation, and is sent to pulse width fixed cell by the frequency signal after frequency dividing；
Described pulse width fixed cell, for the frequency signal after frequency dividing generates the pulse signal of fixed pulse width, and is sent to described low-pass filter unit；
Described low-pass filter unit, generates d. c. voltage signal for the pulse signal according to described fixed pulse width.
8. device according to claim 6, it is characterised in that described difference current forms module, including: OTA operational amplifier, module Z and source are with amplifying circuit；Wherein,
Two input stages of described OTA operational amplifier are the d. c. voltage signal corresponding with described reference frequency, and the d. c. voltage signal corresponding with described system sampling frequency；Described module Z is the compensation network of frequency-locked loop, is connected with the outfan of OTA operational amplifier；The outfan of described OTA operational amplifier is also connected with amplifying circuit with described source, and described source produces described differential current signal with amplifying circuit for final.
9. device according to claim 5, it is characterised in that described slop control module, including: metal-oxide-semiconductor M1, M2, M3 and M4, and electric capacity C, described M1 and M2 is P type enhancement mode metal-oxide-semiconductor, and M3 and M4 is N-type enhancement mode metal-oxide-semiconductor；Wherein,
The grid of described M1 connects pwm signal, and source electrode is the input of described difference current；The grid of described M2 connects PWM_N signal, and drain the output into described difference current；The input that drain electrode is described difference current of described M3, grid connects PWM_N signal；The grid of described M4 connects pwm signal, and source electrode is the output of described difference current；Interconnect between the drain electrode of described M1, the source electrode of M2, the source electrode of M3 and the drain electrode of M4, and be all connected with described electric capacity C, another termination feedback voltage Vfb of electric capacity C.
10. a SOC(system on a chip), it is characterised in that this system includes: the frequency locking device for lag mode step-down controller according to any one of claim 5-9.
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| CN201410775718.8A CN105763054A (en) | 2014-12-15 | 2014-12-15 | Frequency locking method and device for hysteresis-mode buck converter |
| PCT/CN2015/080466 WO2016095447A1 (en) | 2014-12-15 | 2015-06-01 | Frequency locking method and device for buck converter in hysteresis mode |
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| CN109861527A (en) * | 2019-04-02 | 2019-06-07 | 无锡职业技术学院 | A kind of switch power supply system based on lag mode control |
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| CN114649935A (en) * | 2020-12-17 | 2022-06-21 | 圣邦微电子（北京）股份有限公司 | Switch converter and control circuit thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4207539A (en) * | 1976-12-29 | 1980-06-10 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
| CN101350556A (en) * | 2007-07-05 | 2009-01-21 | 英特赛尔美国股份有限公司 | Steady state frequency control of variable frequency switching regulators |
| CN103701322A (en) * | 2012-09-27 | 2014-04-02 | 三星电子株式会社 | Power supply circuit and hysteresis buck converter |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8054056B2 (en) * | 2006-09-16 | 2011-11-08 | Texas Instruments Incorporated | Frequency regulated hysteretic average current mode converter |
| US8008902B2 (en) * | 2008-06-25 | 2011-08-30 | Cirrus Logic, Inc. | Hysteretic buck converter having dynamic thresholds |
-
2014
- 2014-12-15 CN CN201410775718.8A patent/CN105763054A/en active Pending
-
2015
- 2015-06-01 WO PCT/CN2015/080466 patent/WO2016095447A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4207539A (en) * | 1976-12-29 | 1980-06-10 | Matsushita Electric Industrial Co., Ltd. | Frequency synthesizer |
| CN101350556A (en) * | 2007-07-05 | 2009-01-21 | 英特赛尔美国股份有限公司 | Steady state frequency control of variable frequency switching regulators |
| CN103701322A (en) * | 2012-09-27 | 2014-04-02 | 三星电子株式会社 | Power supply circuit and hysteresis buck converter |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109861527A (en) * | 2019-04-02 | 2019-06-07 | 无锡职业技术学院 | A kind of switch power supply system based on lag mode control |
| CN109861527B (en) * | 2019-04-02 | 2020-04-10 | 无锡职业技术学院 | Switching power supply system based on hysteresis mode control |
Also Published As
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| WO2016095447A1 (en) | 2016-06-23 |
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