CN105763054A - Frequency locking method and device for hysteresis-mode buck converter - Google Patents

Abstract

The invention discloses a frequency locking method for a hysteretic mode step-down converter. The method comprises: respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters respectively corresponding to the reference frequency and the system sampling frequency; The voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency are calculated to form a differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal. The invention also discloses a device for realizing the method at the same time.

Description

A frequency locking method and device for a hysteretic mode buck converter

technical field

The invention relates to the technical field of analog switching power supplies, in particular to a frequency locking method and device for a hysteretic mode step-down converter.

Background technique

Buck converters have been widely used in portable devices such as mobile phones, digital cameras, tablet computers, etc. This type of converter has load regulation and recovery time as an important performance indicator. The hysteretic mode control technology abandons the original loop control technology and the limitation that the bandwidth must be limited to about 10% of the switching frequency, so the system bandwidth can be greatly improved, that is, it is effective at the same operating frequency To improve the transient response of the system. However, the hysteretic mode itself has some disadvantages: the most important is that the operating frequency of the system will vary with the duty cycle and load size, which will introduce some new problems in terms of interference. Therefore, in order to make better use of hysteresis mode, the problem of frequency variation must be solved.

Contents of the invention

In order to solve the existing technical problems, an embodiment of the present invention provides a frequency locking method and device for a hysteretic mode step-down converter.

An embodiment of the present invention provides a frequency locking method for a hysteretic mode step-down converter, the method comprising:

Converting the reference frequency and the system sampling frequency respectively to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; performing calculations based on the voltage parameters corresponding to the reference frequency and the voltage parameters corresponding to the system sampling frequency to form A differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal.

Wherein, the reference frequency and the system sampling frequency are respectively converted to obtain corresponding voltage parameters, including:

Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

Wherein, the calculation is performed based on the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

Wherein, the voltage Vramp formed according to the feedback voltage Vfb is:

The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

An embodiment of the present invention also provides a frequency locking device for a hysteretic mode step-down converter, the device includes: a frequency conversion module, a differential current forming module, and a slope control module; wherein,

The frequency conversion module is used to respectively convert the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;

The differential current forming module is configured to perform calculations based on voltage parameters corresponding to the reference frequency and voltage parameters corresponding to the system sampling frequency to form differential current signals;

The slope control module is configured to control the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.

Wherein, the frequency conversion module converts the reference frequency and the system sampling frequency respectively to obtain corresponding voltage parameters, including:

Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

Wherein, the frequency conversion module includes: two frequency detection modules with the same structure, one for the conversion of the reference frequency, and one for the conversion of the system sampling frequency; each frequency detection module includes: a frequency division unit, a pulse width fixed unit and low-pass filter unit; where,

The frequency division unit is used to perform a frequency division operation on the reference frequency or the system sampling frequency, and send the frequency signal after frequency division to the pulse width fixing unit;

The pulse width fixed unit is used to generate a pulse signal with a fixed pulse width from the divided frequency signal and send it to the low-pass filter unit;

The low-pass filtering unit is configured to generate a DC voltage signal according to the pulse signal with a fixed pulse width.

Wherein, the differential current forming module includes: an OTA operational amplifier, a module Z, and a source-following amplifier circuit; wherein,

The two input stages of the OTA operational amplifier are DC voltage signals corresponding to the reference frequency and DC voltage signals corresponding to the system sampling frequency; the module Z is a compensation network of a frequency-locked loop, and the OTA The output terminal of the operational amplifier is connected; the output terminal of the OTA operational amplifier is also connected with the source follower amplifier circuit, and the source follower amplifier circuit is used to finally generate the differential current signal.

Wherein, the slope control module includes: MOS transistors M1, M2, M3 and M4, and a capacitor C, the M1 and M2 are P-type enhanced MOS transistors, and M3 and M4 are N-type enhanced MOS transistors; wherein,

The gate of the M1 is connected to the PWM signal, and the source is the input of the differential current; the gate of the M2 is connected to the PWM_N signal, and the drain is the output of the differential current; the drain of the M3 is the input of the differential current , the gate is connected to the PWM_N signal; the gate of the M4 is connected to the PWM signal, and the source is the output of the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected, And both are connected to the capacitor C, and the other end of the capacitor C is connected to the feedback voltage Vfb.

An embodiment of the present invention also provides a system on chip, the system comprising: the frequency locking device for a hysteretic mode step-down converter as described above.

The frequency locking method and device for the hysteretic mode step-down converter provided by the embodiments of the present invention respectively convert the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively; according to the The voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency are calculated to form a differential current signal; the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled by the differential current signal. In the embodiment of the present invention, when the system sampling frequency is lower than the reference frequency, the value of the formed differential current will increase, thereby increasing the slope of the voltage Vramp signal, so that the voltage Vramp can trigger the reference window voltage Vhys faster, increasing Large system operating frequency; on the contrary, it will reduce the system operating frequency, through negative feedback, to achieve the function of frequency locking.

Compared with the prior art, the embodiments of the present invention have the following advantages:

First of all, the technology commonly used now is to use the principle of phase-locked loop to lock the frequency. On the basis of frequency locking, the phase is locked at the same time, which undoubtedly increases the complexity of the system design. However, this solution uses pure frequency-locking technology. The circuit design is simplified; secondly, in the prior art, the differential signal generated by the phase-locked loop is used to adjust the hysteresis window voltage Vhys, while this solution uses the hysteresis window voltage Vhys to adjust the Vramp signal, which also simplifies the circuit design.

Description of drawings

In the drawings (which are not necessarily drawn to scale), like reference numerals may describe like parts in different views. Similar reference numbers with different letter suffixes may indicate different instances of similar components. The drawings generally illustrate the various embodiments discussed herein, by way of example and not limitation.

FIG. 1 is a schematic diagram of the implementation flow of the frequency locking method for the hysteretic mode step-down converter described in the embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a frequency locking device for a hysteretic mode step-down converter according to an embodiment of the present invention;

FIG. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention;

4 is a schematic structural diagram of a frequency detection module according to an embodiment of the present invention;

5 is a schematic structural diagram of a differential current forming module according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a slope control module according to an embodiment of the present invention.

detailed description

In the embodiment of the present invention, the reference frequency and the system sampling frequency are respectively converted to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively; according to the voltage parameters corresponding to the reference frequency and corresponding to the system sampling frequency The voltage parameters are calculated to form a differential current signal; through the differential current signal, the slope of the voltage Vramp formed according to the feedback voltage Vfb is controlled to finally achieve the function of controlling the system frequency.

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is a schematic diagram of the implementation flow of the frequency locking method for the hysteretic mode step-down converter according to the embodiment of the present invention. As shown in Fig. 1, the method includes:

Step 101: respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;

Step 102: Calculate according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;

Step 103: Control the slope of the voltage Vramp formed according to the feedback voltage Vfb through the differential current signal.

In this way, the voltage Vramp can be compared with the hysteresis window voltage Vhys to form a PWM signal, thereby adjusting and controlling the operating frequency of the system.

In the embodiment of the present invention, when the system sampling frequency is lower than the reference frequency, the value of the formed differential current will increase, thereby increasing the slope of the voltage Vramp signal, so that the voltage Vramp can trigger the reference window voltage Vhys faster, increasing Large system operating frequency; on the contrary, it will reduce the system operating frequency, through negative feedback, to achieve the function of frequency locking.

In the embodiment of the present invention, the reference frequency and the system sampling frequency are respectively converted in step 101 to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively, including:

Perform frequency division processing on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths; wherein, The frequency division processing operations for the reference frequency and the system sampling frequency are the same, for example, the same frequency divider may be used for frequency division.

In the embodiment of the present invention, the calculation in step 102 is performed based on the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

In the embodiment of the present invention, the voltage Vramp formed according to the feedback voltage Vfb is:

The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

The embodiment of the present invention also provides a frequency locking device for a hysteretic mode step-down converter, as shown in FIG. 2 , the device includes: a frequency conversion module 20, a differential current forming module 21 and a slope control module 22; wherein,

The frequency conversion module 20 is configured to convert the reference frequency and the system sampling frequency respectively to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency respectively;

The differential current forming module 21 is configured to perform calculations based on voltage parameters corresponding to the reference frequency and voltage parameters corresponding to the system sampling frequency to form differential current signals;

The slope control module 22 is configured to control the slope of the voltage Vramp formed according to the feedback voltage Vfb through the differential current signal.

In the embodiment of the present invention, the frequency conversion module 20 respectively converts the reference frequency and the system sampling frequency to obtain corresponding voltage parameters, including:

Carry out the same frequency division processing operation on the reference frequency and the system sampling frequency respectively, and generate pulse signals with fixed pulse widths respectively according to the frequency signals after frequency division, and then generate DC voltage signals respectively according to the pulse signals with fixed pulse widths .

In one embodiment, as shown in Figures 3 and 4, the frequency conversion module 20 includes: two frequency detection modules with the same structure, one for the conversion of the reference frequency and one for the conversion of the system sampling frequency, each The frequency detection module includes: a frequency dividing unit 40, a pulse width fixing unit 41 and a low-pass filter (LPF) unit 42; wherein,

The frequency division unit 40 is configured to perform a frequency division operation on the reference frequency or the system sampling frequency, and send the divided frequency signal to the pulse width fixing unit 41;

The pulse width fixing unit 41 is configured to generate a pulse signal with a fixed pulse width from the divided frequency signal and send it to the low-pass filter unit 42;

The low-pass filtering unit 42 is configured to generate a DC voltage signal according to the pulse signal with a fixed pulse width.

In the embodiment of the present invention, the differential current forming module 21 calculates according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency, including:

An error between the DC voltage signal corresponding to the reference frequency and the DC voltage signal corresponding to the system sampling frequency is operationally amplified to obtain a differential current signal.

In one embodiment, as shown in FIG. 5, the differential current forming module 21 includes: an OTA operational amplifier, a module Z, and a source-following amplifier circuit; wherein,

The two input stages of the OTA operational amplifier are DC voltage signals corresponding to the reference frequency and DC voltage signals corresponding to the system sampling frequency; the module Z is a compensation network of a frequency-locked loop, and the OTA The output terminal of the operational amplifier is connected; the output terminal of the OTA operational amplifier is connected with the source follower amplifying circuit, and finally the differential current signal is generated through the source follower amplifying circuit.

In the embodiment of the present invention, the voltage Vramp formed by the slope control module 22 according to the feedback voltage Vfb is:

The voltage Vramp is a triangular wave signal generated by charging and discharging with the quiescent operating point of the feedback voltage Vfb as an intermediate value, and the charging and discharging current is the differential current.

In one embodiment, as shown in FIG. 6, the slope control module includes: MOS transistors M1, M2, M3 and M4, and a capacitor C, the M1 and M2 are P-type enhanced MOS transistors, and M3 and M4 It is an N-type enhanced MOS tube, M1 and M4 are switches controlled by the PWM signal, and M3 and M2 are switches controlled by the PWM_N signal. Wherein, the input end of the M1, that is, the gate is connected to the PWM signal, and the source is the input of the differential current; the gate of the M2 is connected to the PWM_N signal, and the drain is the output of the differential current; the drain of the M3 is For the input of the differential current, the gate is connected to the PWM_N signal; the gate of the M4 is connected to the PWM signal, and the source is the output of the differential current; the drain of the M1, the source of the M2, the source of the M3 and the M4 The drains of the drains are connected to each other, and are connected to the capacitor C, and the other end of the capacitor C is connected to the feedback voltage Vfb.

An embodiment of the present invention also provides a system on chip, the system comprising: the frequency locking device for a hysteretic mode step-down converter as described above.

Fig. 3 is an overall architecture diagram of the application of the frequency locking device in a specific application scenario of the present invention. As shown in Fig. 3, the frequency locking device is mainly composed of three parts:

The first part consists of two frequency detection modules with the same structure, corresponding to the frequency conversion module 20 described in Figure 2, which is used to convert the reference frequency and the system sampling frequency into voltage parameters and provide them to the Gm unit;

The second part is a transconductance (GM) module, corresponding to the differential current forming module 21 described in FIG. 2, for generating current parameters for adjusting the Ramp voltage;

The third part is a Ramp module, which corresponds to the slope control module 22 in Fig. 2, and its main function is to generate a Ramp voltage parameter that changes with the system operating frequency on the basis of the DC parameter of the feedback voltage Vfb, which can increase the comparator The accuracy of the system can also be adjusted through the frequency-locked loop;

In addition, Figure 3 also includes a fast-response PWM comparator and a drive control module required by the hysteretic mode buck converter.

As shown in Figure 3, the hysteretic mode system uses a PWM comparator as the core to control the output voltage within the window voltage range, thereby controlling the output voltage and output voltage ripple. Since the output feedback voltage ripple is very small, the Ramp module is needed to amplify the ripple, which can improve the anti-interference ability of the system and reduce the jitter of the system operating frequency. On the other hand, due to different circuit parameters such as different input voltages, output voltages, or inductances, the operating frequency of the system will also be different, so the frequency-locked loop is also incorporated into the system control loop through the Ramp module. The specific control method is that the frequency detection module will process the reference frequency and the system sampling frequency separately, and the generated voltage will form a differential current through the GM module, and the slope of the voltage Vramp will be affected by the Ramp module. The greater the slope of the voltage Vramp, the system will work The faster the frequency; the smaller the slope of the voltage Vramp, the slower the system operating frequency, so that the system operating frequency can be adjusted through the negative feedback loop under different circuit parameter conditions to stabilize it near the reference frequency.

As shown in FIG. 4 , each frequency detection module includes: a frequency dividing unit 40 , a pulse width fixing unit 41 and a low-pass filter (LPF) unit 42 . Since each frequency detection unit has the same structure, the frequency detection unit corresponding to the reference frequency is taken as an example for illustration.

The reference frequency signal first enters the frequency division unit. The main purpose of the frequency division unit is to adjust the frequency of the input signal, so that the pulse width fixed unit of the subsequent stage can meet the sampling of a wider frequency range. As long as the reference frequency detection and system operating frequency adopt The same frequency divider is enough; the frequency signal after frequency division is used to generate a pulse signal with a fixed pulse width, so that at different frequencies, different DutyCycle inputs will be generated to the low-pass filter unit, thereby generating a corresponding DC output The voltage Vf, the Vf signal directly reflects the frequency.

It can be seen that the frequency detection process of the embodiment of the present invention simplifies the circuit design without using a phase-locked loop module, and at the same time simplifies the loop analysis.

FIG. 5 is a schematic structural diagram of the transconductance module shown in FIG. 3 , that is, the differential current forming module 21 . The differential current forming module inputs the voltage signals reflecting the high and low frequencies generated by the two frequency detection modules to the transconductance module, performs operational amplification on the error of the two signals, and generates a differential current output signal. As shown in Figure 5, in one embodiment, the transconductance operational amplifier circuit can be directly used, that is, the OTA operational amplifier shown in Figure 5 is used as the input stage of the transconductance module, and module Z is the compensation network of the frequency-locked loop. A source-following amplifying circuit composed of M1, M2, M3 and R is connected in stages. The source-following amplifying circuit is a prior art and will not be described in detail here. Finally, the required output error current signal is generated by the source-following amplifying circuit. Here, the gain of the OTA operational amplifier can also be set by adjusting the size of the resistor R and the mirror ratio of M2 and M3, and these parameters will affect the gain of the entire frequency-locked loop.

After that, use the above differential current signal to control the Ramp module, thereby controlling the slope of the voltage Vramp signal, and the final output Vramp signal is generated on the basis of the DC operating point of the Vfb DC voltage, and then compared with the reference voltage window to form PWM signal to adjust and control the operating frequency of the system. As shown in Figure 6, the Vramp voltage is a triangular wave signal generated by charging and discharging with the static operating point of the Vfb voltage as the intermediate value, and the charging and discharging currents are the output error currents ΔI, M1 and M2, of the transconductance module. M3 and M4 are switches controlled by the PWM signal and the PWM_N signal respectively to control the charging and discharging of the capacitor C in Figure 6. When the step-down converter system charges the inductor L in Figure 3, M1 and M3 are turned on. M2 and M4 are turned off, and the Ramp module charges the capacitor C in Figure 6; when the system discharges the inductor L, M1 and M3 are turned off, M2 and M4 are turned on, and the Ramp module discharges the capacitor C in Figure 6, so The generated voltage Vramp signal is different due to the difference between the system operating frequency and the reference operating frequency, thereby adjusting the system operating frequency.

When the system operating frequency is lower than the reference frequency, the current error signal output by the transconductance module will increase, thereby increasing the slope of the Vramp signal, so that Vramp can trigger the hysteresis window voltage Vhys faster and increase the system operating frequency; on the contrary, It will reduce the operating frequency of the system, and realize the function of frequency locking through negative feedback.

Compared with the existing technology, the embodiment of the present invention has two differences: firstly, the technology commonly used now uses the principle of phase-locked loop to lock the frequency, and locks the phase at the same time on the basis of frequency locking, which is undoubtedly Increased the complexity of the system design, and this program uses pure frequency locking technology, which simplifies the circuit design; secondly, the existing technology uses the differential signal generated by the phase-locked loop to adjust the hysteresis window voltage Vhys, and this program uses this The hysteresis window voltage Vhys is used to adjust the Vramp signal, which also simplifies the circuit design.

Those skilled in the art should understand that the embodiments of the present invention may be provided as methods, systems, or computer program products. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (10)

1. A method of frequency locking for a hysteretic mode buck converter, the method comprising:

respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency; calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal; the slope of the voltage Vramp formed from the feedback voltage Vfb is controlled by the differential current signal.

2. The method of claim 1, wherein the converting the reference frequency and the system sampling frequency to obtain the corresponding voltage parameters comprises:

and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.

3. The method of claim 2, wherein the calculating from the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency comprises:

and carrying out operational amplification on an error between the direct-current voltage signal corresponding to the reference frequency and the direct-current voltage signal corresponding to the system sampling frequency to obtain a differential current signal.

4. A method according to any of claims 1-3, characterized in that said voltage Vramp, formed from said feedback voltage Vfb, is:

the voltage Vramp is a triangular wave signal generated by charging and discharging with a static operating point of the feedback voltage Vfb as a middle value, and the current for charging and discharging is the differential current.

5. A frequency locking apparatus for a hysteretic mode buck converter, the apparatus comprising: the device comprises a frequency conversion module, a differential current forming module and a slope control module; wherein,

the frequency conversion module is used for respectively converting the reference frequency and the system sampling frequency to obtain voltage parameters corresponding to the reference frequency and the system sampling frequency;

the differential current forming module is used for calculating according to the voltage parameter corresponding to the reference frequency and the voltage parameter corresponding to the system sampling frequency to form a differential current signal;

and the slope control module is used for controlling the slope of Vramp formed according to the feedback voltage Vfb through the differential current signal.

6. The apparatus of claim 5, wherein the frequency conversion module converts the reference frequency and the system sampling frequency to obtain corresponding voltage parameters, respectively, and comprises:

and respectively carrying out the same frequency division processing operation on the reference frequency and the system sampling frequency, respectively generating pulse signals with fixed pulse width according to the frequency signals after frequency division, and respectively generating direct-current voltage signals according to the pulse signals with fixed pulse width.

7. The apparatus of claim 6, wherein the frequency conversion module comprises: two frequency detection modules with the same structure are used for converting the reference frequency and the system sampling frequency; each frequency detection module includes: the device comprises a frequency division unit, a pulse width fixing unit and a low-pass filtering unit; wherein,

the frequency dividing unit is used for executing frequency dividing operation on the reference frequency or the system sampling frequency and sending a frequency signal after frequency dividing to the pulse width fixing unit;

the pulse width fixing unit is used for generating a pulse signal with a fixed pulse width from the frequency signal after frequency division and sending the pulse signal to the low-pass filtering unit;

the low-pass filtering unit is used for generating a direct-current voltage signal according to the pulse signal with the fixed pulse width.

8. The apparatus of claim 6, wherein the differential current forming module comprises: the OTA operational amplifier, the module Z and the source follower amplifying circuit; wherein,

the two input stages of the OTA operational amplifier are a direct-current voltage signal corresponding to the reference frequency and a direct-current voltage signal corresponding to the system sampling frequency; the module Z is a compensation network of a frequency locking loop and is connected with the output end of the OTA operational amplifier; the output end of the OTA operational amplifier is also connected with the source follower amplifying circuit, and the source follower amplifying circuit is used for finally generating the differential current signal.

9. The apparatus of claim 5, wherein the slope control module comprises: MOS tubes M1, M2, M3 and M4 and a capacitor C, wherein the M1 and the M2 are P-type enhanced MOS tubes, and the M3 and the M4 are N-type enhanced MOS tubes; wherein,

the grid electrode of the M1 is connected with a PWM signal, and the source electrode is used as the input of the differential current; the grid electrode of the M2 is connected with a PWM _ N signal, and the drain electrode is used for outputting the differential current; the drain electrode of the M3 is the input of the differential current, and the grid electrode is connected with a PWM _ N signal; the grid electrode of the M4 is connected with a PWM signal, and the source electrode is used for outputting the differential current; the drain of the M1, the source of the M2, the source of the M3 and the drain of the M4 are interconnected and are connected with the capacitor C, and the other end of the capacitor C is connected with a feedback voltage Vfb.

10. A system on a chip, the system comprising: a frequency locking arrangement for a hysteretic mode buck converter as claimed in any of claims 5 to 9.