CN103618455A - Method for reducing steady state error of output voltage of single-inductor double-output converter and circuit - Google Patents

Method for reducing steady state error of output voltage of single-inductor double-output converter and circuit Download PDF

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CN103618455A
CN103618455A CN 201310666465 CN201310666465A CN103618455A CN 103618455 A CN103618455 A CN 103618455A CN 201310666465 CN201310666465 CN 201310666465 CN 201310666465 A CN201310666465 A CN 201310666465A CN 103618455 A CN103618455 A CN 103618455A
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output
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signal
terminal
gate
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CN103618455B (en )
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陆生礼
肖哲飞
于花
张力文
钱钦松
孙伟锋
时龙兴
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东南大学
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Abstract

The invention discloses a method for reducing a steady state error of output voltage of a single-inductor double-output converter. When high-capacitance-free compensation is adopted for a main loop error amplifier, a current sampling and holding circuit is additionally arranged in a main loop, direct current level Vdc output by the current sampling and holding circuit is superimposed and summated with ramp voltage Vramp1 to generate new ramp voltage Vramp2, the ramp voltage Vramp2 is superimposed and summated with a sampled inductive current signal to generate the input voltage Vsense of the in-phase input end of a comparator, direct current level Vdc0 is simultaneously superimposed with the output Vc of the error amplifier to obtain an inverting input signal Ve of the comparator, Ve is another input signal of the current sampling and holding circuit, and sufficient charging time can be provided for an inductor of the converter by a primary switching control signal output by the comparator, so that the steady state error of the output voltage of the converter is reduced.

Description

一种减小单电感双输出变换器输出电压稳态误差的方法及其电路技术领域 Method for reducing the output single inductor double inverter output voltage and steady state error circuit BACKGROUND

[0001 ] 本发明涉及单电感双输出(SIDO)降压型开关电源变换器,尤其涉及一种减小单电感双输出变换器输出电压稳态误差的方法及其电路。 [0001] The present invention relates to a dual output single inductor (SIDO) step-down switching power converter, and particularly to a method and dual output single inductor circuit inverter output voltage steady state error decreases.

背景技术 Background technique

[0002] 在SIDO电路中,通常希望电路在对负载突变做出快速响应的同时,尽可能减小输出电压的稳态误差。 [0002] In SIDO circuit, while a circuit is generally desirable to respond quickly to sudden load changes, steady-state error of the output voltage is reduced as much as possible. 在传统的SIDO降压型开关电源变换器的主级控制环路当中,由于误差放大器采用了含有大电容的PI补偿,如图1所示,电路的瞬态响应很慢。 In the conventional primary control loop SIDO buck switching power converter which, due to an error amplifier uses a PI compensator containing a large capacitance, as shown in FIG circuit's transient response is slow 1. 采用无大电容补偿的低增益误差放大器,可以带来两点好处:一是瞬态响应快;二是减少了一个大电容,芯片面积会大大减少。 No large capacitance using low-gain error amplifier compensation can bring two benefits: First, fast transient response; second is to reduce a large capacitance, the chip area can be greatly reduced. 但考虑到系统的稳定性,必须降低误差放大器的增益。 However, considering the stability of the system, the gain of the error amplifier must be reduced. 低增益的误差放大器会使输出电压的稳态误差变得较大,主要原因有以下两点:一是当负载电流增加,主环增益较小,对输出电压的下降无法灵敏地检测出来;二是当负载电流增加,主环比较器的同相输入端信号Vsense增加,导致主级开关控制信号占空比减小,由于误差放大器增益较低,无法产生足够的输出电压来调节占空比,这样就造成了比较大的电路输出电压稳态误差。 Low gain steady state error of the error amplifier output voltage will becomes larger, the following two main reasons: First, when the load current increases, the main loop gain is small, can not be detected sensitively to the drop in the output voltage; two when the load current is increased, the primary ring input comparator inverting terminal increases the Vsense signal, resulting in the duty cycle of primary switch control signal is reduced, since the error amplifier gain is not high enough to generate sufficient to adjust the duty cycle of the output voltage, so causing a large steady state error circuit output voltage.

发明内容 SUMMARY

[0003] 本发明针对在SIDO主级控制回路中采用了无大电容补偿的低增益误差放大器而造成大的输出电压稳态误差这一缺陷,为了减小稳态误差,提供了一种减小单电感双输出变换器输出电压稳态误差的方法及其电路,在主环中增加了减小稳态误差的控制电路,大大提高了输出电压的精度。 [0003] The present invention is directed to a low-gain error amplifier uses no large capacitance compensation in SIDO primary control circuit output voltage caused by a large steady state error this defect, in order to reduce steady state error, there is provided a reduced single inductor double output inverter output voltage steady state error method and circuit, the control circuit reduces the increase in steady-state error in the main ring, which greatly improves the accuracy of the output voltage.

[0004] 本发明米用的具体技术方案如下:一种减小单电感双输出变换器输出电压稳态误差的方法,单电感双输出变换器的控制电路中,主环采用峰值电流环模式,决定变换器两路负载电流之和,即流过变换器电感L的总电流平均值Iy次环采用电压模式,决定电感电流 [0004] The present invention Mingmi with specific technical solutions as follows: A method for reducing the inductance of a single dual-output inverter output voltage steady state error, the control circuit unit inductor dual output converter, the primary ring loop uses peak current mode, two decisions converter and load current, i.e. the inductor L flows through the converter total current Iy times the average voltage-mode loop, determines the inductor current

Il在两路输出中的分配,主环设有误差放大器、比较器、触发器和驱动和死区控制电路,误差放大器同相端输入参考电压Vkefi,反相端输入0.4X (Vol+Vo2),V01, V02分别是变换器的两路输出电压,误差放大器的输出V。 Il partitioned between two outputs, with the primary ring error amplifiers, comparators, flip-flops and a drive control circuit and dead, to the positive input of the error amplifier reference voltage Vkefi, the inverting input terminal of 0.4X (Vol + Vo2), V01, V02 are two inverter output voltage, the output of the error amplifier V. 连接比较器的反相输入端,斜坡电压Vrampl与米样的电感电流IA信号叠加求和后连接比较器的同相输入端,比较器的输出和时钟信号分别输入触发器,触发器的输出连接驱动和死区控制电路的输入,驱动和死区控制电路输出信号PG控制主级开关的通断,其特征在于:当主环误差放大器采用无大电容补偿的低增益误差放大器时,在主环中增设一个电流采样保持电路,该电流采样保持电路的一个输入信号为采样的电感电流IJs信号,电流采样保持电路输出的直流电平Vd。 Connected to the inverting input terminal of the comparator, and the ramp voltage Vrampl rice samples IA inductor current signal superimposed with the summing phase comparator connected to the input end, an output and a clock signal are input flip-flop, flip-flop output connection driver and deadband input control circuit of the drive and dead-time control circuit outputs a signal PG controlling the main stage switch-off, characterized in that: when the main loop error amplifier uses the low-gain error amplifier no large capacitance compensation, addition of the main ring a current sample and hold circuit, the current sampling an input signal to the sample hold circuit IJs inductor current signal, the current output from the sample hold circuit DC level Vd. 与斜坡电压Vmp1叠加求和后产生新的斜坡电压Vramp2再与采样的电感电流IJs信号叠加求和后作为比较器同相输入端的输入电压Vsense,同时将误差放大器的输出V。 Vramp2 a new ramp voltage after the ramp voltage is superimposed Vmp1 then summed with the summed signal superimposed IJs inductor current is sampled as the noninverting input of the comparator input voltage Vsense, while the output of the error amplifier V. 叠加上一个直流电平Vtkci得到比较器的反相端输入信号I,该信号I也是电流采样保持电路的另一个输入信号,所叠加直流电平Vtkci应满足比较器反相端输入信号值Ve等于变换器满负载时比较器同相端输入信号Vsense的最大值\,Vp的值随负载变化,变换器满负载时达到最大,Vsense=Vp-Vc,此时比较器输出的信号经过D触发器和驱动和死区控制电路输出的主级开关控制信号PG,能够给变换器电感足够的充电时间,从而减小变换器输出电压的稳态误差; Superimposed on a DC level obtained Vtkci comparator inverting terminal input signal I, which is a current signal I sampled signal holding circuit, the other input of the superimposed DC level Vtkci should satisfy the inverting input terminal of the inverter is equal to the signal value Ve comparator varies with load, maximum, Vsense = Vp-Vc at full load with \, the maximum value of Vp is positive input of the converter when the signal Vsense full load, this time the comparator output signal passes through D flip-flops and a drive and dead-time control circuit outputs the PG primary switch control signal, the converter can give a sufficient charging time of the inductor, thereby reducing the steady-state error of the inverter output voltage;

[0005] 上述方法中所增设的电流采样保持电路包括控制信号V1和V2产生电路、D触发器使能信号EN产生电路、电感电流采样保持选通信号S1和S2产生电路、直流电平Vd。 Current [0005] The above method of adding the sample and hold circuit includes a control signal generating circuit V1 and V2, D flip-flop circuit generating the enable signal EN, the inductor current sample and hold gate signal generating circuit S1 and S2, the DC level Vd. 产生电路和在斜坡电压Vmp1上叠加直流电压Vd。 DC voltage generating circuit and superimposed on the ramp voltage Vmp1 Vd. 叠加求和后产生新的斜坡电压Vramp2的电路; Superimposing a new ramp voltage summing circuit after Vramp2;

[0006] 控制信号V1和V2产生电路包括四个D触发器DO、Dl、D2、D3,两个与非门NANDl、NAND2,触发器DO的输入端D与输出端&短接并连接与非门NANDl的一个输入端,与非门NANDl的另一个输入端连接时钟信号CLK,与非门NANDl的输出端连接触发器DO的时钟端,触发器DO的输出端Q分别连接触发器Dl、D2的使能端,触发器Dl的输入端D与输出〗u D短接并连接触发器D2的时钟端,触发器Dl的输出端Q空接,与非门NAND2的一个输入端连接触发器D2的输入端D和输出端&,与非门NAND2的另一个输入端连接时钟信号CLK,与非门NAND2的输出端连接触发器Dl的时钟端,触发器D2的输出端Q连接触发器D3的使能端并作为控制信号V2的输出端,触发器D3的时钟端连接时钟信号CLK,触发器D3的输入端D与输出端&短接,触发器D3的输出端Q为控制信号V1的输出端; [0006] V1 and V2 control signal generating circuit comprises four D flip-flops DO, Dl, D2, D3, and two NAND gates NANDl, NAND2, and the output terminal of the input terminal D of the flip-DO & shorted and connected to non- NANDl a gate input connected to the other input of NAND gate NANDl clock signal CLK, the output of the NAND gate is connected to the clock terminal of the flip NANDl DO, the DO output Q of flip-flop are connected Dl, D2 an enable terminal, the input terminal D of the flip-flop output Dl〗 U D shorted and connected to a clock terminal of the flip-flop D2, an output terminal Q of the flip-flop to empty Dl, D2 is connected to a trigger input terminal of the NAND gate NAND2 an input terminal and an output terminal & D, clock signal CLK is connected to the other input of the NAND gate NAND2, and the output of the NAND gate NAND2 is connected to a clock terminal of the flip-flop Dl, D2 of the Q output of flip-flop connected to the flip-flop D3 an enable terminal as an output terminal and a control signal V2, D3 is connected to the clock terminal of the flip clock signal CLK, the D input terminal and the output terminal & shorted, the output of flip-flop D3 D3 of the Q output of the control signal V1 end;

[0007] D触发器使能信号EN产生电路包括两个比较器C0MP1、C0MP2和一个同或门,比较器C0MP1、C0MP2的同相端分别连接电压信号Vh和\,比较器C0MP1、C0MP2的反相端互连并连接变换器的两路输出电压差Vtll-Vtl2, Vh和\均选取为(Vtjl-VJ X (I ±2%),比较器COMPl和C0MP2的输出分别连接同或门的两个输入端,同或门的输出端产生使能信号EN连接至控制信号V1和V2产生电路中触发器DO的使能端; [0007] D flip-flop circuit generating the enable signal EN includes two comparators C0MP1, C0MP2 and a NOR gate, a comparator C0MP1, C0MP2 phase side are connected and the voltage signal Vh \ comparator C0MP1, C0MP2 inverting interconnected and connected to the end of the two-way converter output voltage difference Vtll-Vtl2, Vh and \ are selected to (Vtjl-VJ X (I ± 2%), and the comparator COMPl C0MP2 output of the oR gate connected respectively with the two an input terminal, an output terminal of the NOR gate generates the enable signal EN is connected to the control signal generation circuit V1 and V2 enable terminal of flip-flops DO;

[0008] 电感电流采样保持选通信号S1和S2产生电路包括两个或门0R1、0R2,与门AND,非门N0T,或门ORl的两个输入端分别连接主级开关控制信号PG及控制信号V2,或门ORl的输出连接与门AND的一个输入端,与门AND的另一个输入端连接控制信号V1,与门AND的输出连接或门0R2的一个输入端,或门0R2的另一个输入端连接使能信号EN,或门0R2的输出连接非门NOT的输入端并作为选通信号S1输出端,非门NOT的输出端为选通信号S2输出端; [0008] The inductor current sample holding strobe S1 and S2 generating circuit comprises two OR gates 0R1,0R2, connected to the primary control signal PG and a control switch with two inputs of the AND gate AND, NOT gate N0T, respectively, the OR gate ORl output connection signal V2, and the oR gate ORl one input terminal of aND gate is connected to the other input terminal of aND gate control signal V1, the output of gate aND is connected to one input of gate 0R2 or 0R2 of the other door an input terminal connected to an enable signal EN, the output of the oR gate 0R2 connected to the input of NAND gate NOT gate signal S1 as an output terminal, an output terminal of the NAND gate is a NOT gate signal S2 output terminal;

[0009] 直流电平Vic产生电路包括控制开关K1、K2、K3,电容Q、C2,运算放大器、缓冲器,控制开关K1的一端连接电感电流IJs信号,控制开关K1的另一端连接电容C1的一端并通过控制开关K2接地,电容C1的另一端与运算放大器的反相端、电容C2的一端以及控制开关K3的一端连接,电容C2和控制开关K3的另一端与运算放大器的输出端及缓冲器的输入端连接在一起,运算放大器的同相端接地,控制开关1、K2, K3的控制端分别连选通信号Sp S2, S1,接缓冲器的输出与信号\及斜坡电压Vmp1三者叠加求和后产生直流电平Vd。 [0009] Vic DC level generating circuit comprises a controlled switch K1, K2, K3, capacitor Q, C2, an operational amplifier, a buffer, a control switch K1 is connected to one end of the inductor current signal IJs, another end of the control switch K1 is connected to the capacitor C1 and K2 by controlling the switch to ground, the inverting terminal of the capacitor C1 and the other end of the operational amplifier, one end of the capacitor C2 and one end of a control switch K3 is connected to the output terminal of the other end of the capacitor C2 and switches K3 and control operational amplifier and a buffer input terminals are connected together, with the phase of the operational amplifier is grounded, the control switch 1, K2, K3 are respectively connected to the control terminal of the strobe signal Sp S2, S1, then the buffer output signal \ Vmp1 three superimposed ramp voltage and seek and generating the DC level Vd. 输出; Output;

[0010] 在斜坡电压Vmip1上叠加直流电压Vd。 [0010] DC voltage Vd is superimposed on the ramp voltage Vmip1. 叠加求和后产生新的斜坡电压Vranip2的电路包括电流源1、NMOS管Mn1、Mn2,PMOS管Mp1、Mp2,控制开关K4、K5及电容C3,电流源I的正端连接电源Vdd,电流源I的负端与NMOS管Mni的漏极和栅极以及NMOS管Mn2的栅极连接,NMOS管MN1、MN2的源极接地,NMOS管Mn2的漏极与PMOS管Mpi的漏极和栅极以及PMOS管Mp2的栅极连接,PMOS管MP1、MP2的源极连接电源Vdd,PM0S管Mp2的漏极连接开关K4的一端,开关K4的另一端与开关K5的一端和电容C3的一端连接并作为新的斜坡电压信号Vramp2的输出端,开关K5的另一端和电容C3的另一端连接并连接直流电平Vd。 After generating the new ramp voltage superimposed Vranip2 summing circuit comprises a current source 1, NMOS tube Mn1, Mn2, PMOS tube Mp1, Mp2, control switch K4, K5 and the capacitor C3, the positive terminal of the current source I is connected to the power supply Vdd, current sources I negative terminal and a gate connected to the gate and the drain of the NMOS transistor Mn2 and the NMOS transistor Mni is, NMOS transistor MN1, MN2 the source is grounded, and the drain of PMOS transistor Mpi drain and the gate of the NMOS transistor Mn2 and connected to the gate of the PMOS transistor Mp2, PMOS transistor MP1, MP2 connected to the power source Vdd, the drain connected to one end of the switch K4, Mp2 PM0S tube, the other end of the switch K4 and K5 of the one ends of the switching capacitor C3 is connected as the new output of the ramp voltage signal Vramp2 the other end of the switch K5 and the other end connected to the capacitor C3 is connected and the DC level Vd. ,开关K5、K4的控制端分别连接时钟控制信号CLK及CLK的反信4 ZTk。 , Switch K5, K4 are connected to the control terminal of the anti-clock control channel 4 ZTk signal CLK and CLK.

[0011] 本发明的优点及显著效果: [0011] The advantages of the present invention and the significant effect:

[0012] 本发明针对在SIDO主级控制回路中采用了无大电容补偿的低增益误差放大器而造成大的输出电压稳态误差这一缺陷,增设了电感电流采样保持电路,补偿了输出电压的直流偏差,减小了输出电压的稳态误差,提高了输出电压的精度。 [0012] The present invention is directed to a low-gain error amplifier uses no large capacitance compensation in SIDO primary control circuit output voltage caused by a large steady state error this drawback, the addition of the inductor current sample and hold circuit, the output voltage of the compensating DC offset reduced output voltage steady-state error, improves the accuracy of the output voltage.

附图说明 BRIEF DESCRIPTION

[0013] 图1为传统SIDO电路原理图; [0013] FIG. 1 is a schematic circuit diagram of a conventional SIDO;

[0014] 图2为改进后的整个SIDO电路原理图; [0014] FIG. 2 SIDO entire circuit diagram of the improvement;

[0015] 图3a为未叠加直流电压Vde的斜坡电压Vmp1波形和叠加Vde之后的斜坡电压Vranip2波形; [0015] Figure 3a is not superimposed DC voltage Vde slope of the ramp waveform after Vmp1 voltage Vde and superimposed voltage waveform Vranip2;

[0016] 图3b中定义了比较器反相端输入信号Ve值为满负载时比较器同相输入端信号 [0016] FIG. 3b defined inverting input terminal of the comparator signal of the comparator inverting input terminal of the full load value of signal Ve

Vsense的峰值Vp ; Vsense Vp of the peak;

[0017]图4为电流采样保持电路模块内部具体电路以及斜坡信号Vramp2的产生电路; [0017] FIG. 4 is a current sample and hold circuit and the internal circuit module is Vramp2 ramp signal generating circuit;

[0018]图5为电流采样保持电路模块中各信号的波形图。 [0018] FIG. 5 is a current waveform diagram of each signal sample and hold circuit module.

具体实施方式 detailed description

[0019] 图1为传统SIDO电路原理图。 [0019] FIG. 1 is a schematic circuit diagram of a conventional SIDO. 电路的控制环路分为主环和次环。 Control loop circuit primary ring and a secondary ring. 主环采用峰值电流模式,决定两路负载电流之和(即流过电感的总电流),次环采用电压模式,决定电感电流在两路中的分配。 Main loop uses peak current mode is determined and the two load currents (i.e., total current flowing through the inductor), the secondary loop voltage-mode, the inductor current determines the allocation of the two. 为了避免在占空比大于50%时出现的次谐波振荡现象,检测到的电感电流对应的电压需要与一个斜坡电压Vrampl相叠加。 To avoid subharmonic oscillation phenomenon at duty cycles greater than 50%, the detected voltage corresponding to the inductor current requires a ramp with superimposed voltage Vrampl. 主环米用有大电容补偿的误差放大器,电路瞬态响应速度慢,同时大电容占用较大的芯片面积。 M with a primary ring has a large capacitance compensation error amplifier circuit transient response is slow, while a large capacitor occupies a large chip area. 如果误差放大器采用无大电容补偿的低增益误差放大器(将图1中误差放大器输出端的虚线框电容CP1、Rp1去除),虽然可以带来两点好处:一是瞬态响应快;二是减少了一个大电容,芯片面积会大大减少。 If the error amplifier uses no large capacitance compensation of low gain error amplifier (output of the error amplifier 1 in a dashed box in FIG capacitor CP1, Rp1 is removed), although brings two advantages: First, fast transient response; the second is to reduce a large capacitance, the chip area can be greatly reduced. 但考虑到系统的稳定性,必须降低误差放大器的增益。 However, considering the stability of the system, the gain of the error amplifier must be reduced. 而低增益的误差放大器会使输出电压的稳态误差变得较大。 Low gain steady state error and an error amplifier output voltage will becomes larger.

[0020] 图2为本发明改进后整个SIDO电路工作的原理框图。 [0020] FIG. 2 is a functional block diagram of the entire circuit SIDO invention is improved. 本发明在斜坡电压Vmp1上叠加一个随负载改变的直流电平vd。 The present invention is superimposed with a load change in the DC level of ramp voltage vd Vmp1. ,得到新的斜坡电压Vmp2,Vramp2与电流检测器的输出电压求和得到Vsmse,作为比较器的同相输入端信号。 Results in a new Vmp2 ramp voltage, the output voltage of the current detector Vramp2 summing Vsmse, as with the inverting input terminal of the comparator signal. 在误差放大器的输出信号V。 The error amplifier output signal is V. 上叠加一个合适的直流电平V-,使得比较器反相端输入信号值Ve等于满负载时比较器同相端输入信号Vsmse的最大值Vp,Vp的值随负载变化,满负载时达到最大。 Suitable superimposed on a DC level V-, so that the maximum value of the inverting input terminal of comparator Vp-inverting input terminal of the signal value of the signal Ve Vsmse full load is equal, the value of Vp varies with load, maximum full load. 通过比较器产生主级开关控制信号,经过驱动和死区控制电路调节电路给电感的充电时间,从而减小输出电压的稳态误差。 Primary switch control signal generated by the comparator, through the drive control circuit and dead time adjusting circuit to the charging inductance, thereby reducing the output voltage of the steady state error. 主环的工作原理:主环误差放大器同相端输入信号为参考电SVkefi,反相端输入信号为0.4X (Vo1+Vo2),输出电压V。 Primary ring works: primary ring to the positive input of the error amplifier input signal is the reference signal SVkefi, inversion terminal of 0.4X (Vo1 + Vo2), an output voltage V. 叠加上一个直流电压Vtkci得到比较器的反相端输入信号Ve,这个直流电平Vtkci为电路满负载时比较器同相端输入信号Vsense的峰值Vp和V。 Superimposed on a DC voltage obtained Vtkci comparator inverting input terminal of the signal Ve, when the DC level Vtkci full load circuit to the positive input of the comparator signal Vsense of the peak value Vp and V. 的差值。 Difference. 通过比较器产生主级开关控制信号,经过驱动与死区控制电路控制主级开关的通断,从而调节电路给电感的充放电时间。 Primary switch control signal generated by the comparator, and via the drive control circuit controls the dead-off switch of the main stage, thereby adjusting the discharge time of the circuit to the inductor.

[0021] 当负载发生突变时,不妨假设当第一路负载增加,此时,第一路输出电压会出现一个向下的过冲,电感电流平均值增加。 [0021] When the load is mutated, it may be assumed when the first output is increased, this time, a first output voltage will be a downward overshoot, to increase the average inductor current. 因此,比较器同相端输入信号Vsmse也增加,Vsense的最大值Vp与Ne之差变小。 Thus, the comparator noninverting input terminal of Vsmse increases, the difference between the maximum value of Vp and Vsense Ne becomes smaller. 通过电感电流采样保持电路,将此时的电感电流峰值采样出来与斜坡电压Vrampl峰值相加后与Ve做减法,得出Vd。 Sample and hold circuit current through the inductor, the inductor current peak out sampling at this time is added to the peak value of the ramp voltage Ve Vrampl subtraction, derived Vd. . 最后,在斜坡电压Vrampl上叠加上vd。 Finally, on the ramp voltage Vrampl superimposed on vd. ,得到Vmp2 号。 To give Vmp2 number.

[0022] 图3a为未叠加直流电压Vdc的斜坡电压VMpl波形和叠加Vdc之后的斜坡电压Vranip2波形。 [0022] Figure 3a is not superimposing a DC ramp voltage Vdc Vranip2 ramp voltage waveform after the voltage waveform and superimposed VMpl Vdc. 图3b中定义了主环比较器反相端输入信号Ve值为满负载时比较器同相输入端信号Vsense的峰值Vp,Vdc0为主环误差放大器输出电压V。 FIG. 3b defined in the comparator inverting input terminal of the main loop signal Vsense the inverting input terminal of the full load value of the peak signal Ve Vp, Vdc0 main loop error amplifier output voltage V. 和V6的差值。 And the difference between the V6.

[0023] 图4电流采样保持电路的内部电路结构,包括控制信号V1和V2产生电路、D触发器使能信号EN产生电路、电感电流采样保持选通信号S1和S2产生电路、直流电平Vd。 [0023] FIG 4 the internal circuit configuration of a current sampling and hold circuit comprising a control circuit generating signals V1 and V2, D flip-flop circuit generating the enable signal EN, the inductor current sample and hold gate signal generating circuit S1 and S2, the DC level Vd. 产生电路和在斜坡电压Vranipl上叠加直流电压Vd。 DC voltage generating circuit and superimposed on the ramp voltage Vranipl Vd. 叠加求和后产生新的斜坡电压Vranip2的电路。 Superimposing a new ramp voltage summing circuit after Vranip2. [0024] D触发器使能信号EN产生电路:比较器I的同相端接VH,比较器2同相端接',两者反相端都接Vtjl-Vtj2,由于输出电压过冲一般小于5%,所以Vh和八可以选取为(V01-V02) X (I ±2%),设两个比较器的输出逻辑电平分别为A和B。 [0024] D flip-flop circuit generating the enable signal EN: Comparator I is in phase with the VH termination, terminating in phase comparator 2 ', both of which are connected to the inverting terminal Vtjl-Vtj2, since the output voltage overshoot is generally less than 5% , and VIII may be selected so as Vh (V01-V02) X (I ± 2%), the output logic level are provided two comparators a and B. 电路稳定时,比较器的输出电平A和B分别为“ I ”和“0”,当负载发生变化时,A和B两个信号当中有一个信号将会 When the circuit is stable, the output level of the comparator A and B are "I" and "0", when the load changes, the A and B signals among the two signals will have a

发生跳变,五况=184 I万,其中,1、云分别为A、B的反信号。 Transition occurs ten thousand five conditions = 184 I, wherein 1, respectively inverse cloud signals A, B's. 此时EN会从“0”变为 At this time EN changes from "0" to

“1”,变为有效使能信号,D触发器工作。 "1", the enable signal becomes active, D flip-flop work.

[0025] 控制信号V1和V2的产生电路:D触发器0的使能信号接EN信号,输出端&接到输入端D,同时把和CLK的与信号接到时钟信号端CLK,输出端Q接到D触发器1、2的使能端,D触发器I的输出端豆接到输入端D,并作为D触发器2的CLK信号,D触发器2的输出端&连接到输入端D,同时与上CLK后接到D触发器I的CLK输入端,D触发器2的输出端Q连到D触发器3的使能端,并作为输出信号V1输出,D触发器3的输出端g接到输入端D,输出端Q作为输出信号V2输出。 [0025] The control signal generating circuit V1 and V2: D flip-flop enable signal 0 EN signal ground, an input terminal connected to an output terminal & D, with a, and the signal CLK to the clock signal terminal CLK, the output Q 1 and 2 that the D flip-flop to enable terminal, the output terminal of the D flip-I of beans to input terminal D, and the CLK signal as a D flip-flop 2, the output of the D flip-flop 2 is connected to the input terminal D & while after the CLK to the CLK input of the D flip-flop I, D flip-flop output terminal Q 2 is connected to the D flip-flop 3 can enable terminal, and output as an output signal V1, the output of D flip-flop 3 g to the input terminal D, an output terminal Q as the output signal V2 output. D触发器0-3主要实现的功能如下:如图4所示,D触发器0主要实现EN的锁存功能,D触发器1、2主要实现计数功能,计2个周期的PG信号之后,输出高电平。 0-3 D flip-flop main function is as follows: as shown, D flip-flop 0 in FIG. 4 EN main implement the latching function, the main achievement of the D flip-1,2 counting function, PG after 2 cycles count signal, It outputs a high level. D触发器3在V1的基础上再计一个PG周期,输出V2信号。 D flip-flop 3 V1 on the basis of a further meter PG period, the output signal V2. 其中,PG信号为主级开关控制信号。 Wherein, PG-based signal level switch control signal.

[0026] 电感电流采样保持选通信号S1和S2产生电路:PG与V2求或,然后再与V1,之后和EN相或,得到S1信号,经过非门,得到S2信号。 [0026] The inductor current sample and hold gate signal generating circuit S1 and S2: PG and V2 or demand, and then V1, and after the phase or EN, the S1 signal obtained through the NAND gate, the signal S2 obtained.

[0027] 电感电流采样保持电路如图4所示,运放同相端接地,反相端接电容C1,然后通过开关K1接电感采样电流IJ?S,通过开关K2接地,运放输出端通过电容C2和开关K3两条通路接到运放的反相端。 [0027] The inductor current sample and hold circuit shown in Figure 4, with op amp is grounded, inverting the termination capacitance C1, and then sampling the inductor current IJ via a switch K1? S, by switch K2 to ground, the output terminal of the op amp through a capacitance C2 and switches K3 two paths to the inverting terminal of the operational amplifier. 运放输出端经过缓冲器,与' 和Vmp1求和,得到直流电压信号Vd。 By a buffer amplifier output terminal, and 'Vmp1 and summed to obtain a DC voltage signal Vd. . 其主要工作原理如下:首先,K1和K3接通,K2断开,运放输出端电压为0,因此C1两端电压 The main works as follows: First, Kl and K3 are turned on, K2 off op amp output voltage is 0, so the voltage across C1

C1 C1

就近似等于;然后,K1和K3断开,K2接通,输出电压就从0变为Umax ,我们取 It is approximately equal; then, Kl and K3 is disconnected, K2 is turned on, the output voltage from 0 to Umax, we take

C1=C2,则运放输出端电压最后稳定在IJ?S的最大值其中,KpK2和K3是同类型的开关,当控制信号高电平时,开关闭合。 C1 = C2, the op amp output voltage finally stabilized at IJ? S wherein the maximum value, KpK2 and K3 are the same type of switch, when the control signal is high level, the switch is closed.

[0028] 在斜坡电压I一上叠加直流电压Vd。 [0028] DC voltage Vd is superimposed on the I-ramp voltage. 的实现电路图中包括电流源I,NMOS电流镜,PMOS电流镜,电容C3,时钟控制开关K4和K5以及参考电压Vd。 Implementation of the circuit diagram includes a current source I, NMOS current mirror, the PMOS current mirror, the capacitor C3, switch K4 and K5 control the clock and a reference voltage Vd. . 电流I通过NMOS电流镜和PMOS电流镜镜像使得Mp2漏端电流为I,开关K4闭合,K5断开,电流I对电容C3充电,电容上的电压从Vd。 The current I through the PMOS and NMOS current mirror such that the mirror current mirror current drain terminal Mp2 I, closing the switch K4, K5 off, the current I charge the capacitor C3, the voltage on the capacitor from Vd. 以*的斜率上升,达到设定电压,此时时钟控制开关K4断开、K5闭合,输出 * Slope increases, reaches the set voltage so that the clock control OFF switch K4, K5 is closed, the output

电压Vmp2立刻下降为Vd。 Vmp2 voltage immediately drops to Vd. ,下一个时钟周期重复以上过程。 Next clock cycle process is repeated. 其中,K4和K5是同类型的开关,当控制信号高电平时,开关闭合。 Wherein, K4 and K5 are the same type of switch, when the control signal is high level, the switch is closed.

[0029]图5为电流采样保持电路模块中个信号的波形图,其中包括D触发器I和2的使能信号EN,V1和V2信号,主级开关控制信号PG,PG和V2的或信号,V1和PG、V2的或信号相与以及电感电流込。 [0029] FIG. 5 is a waveform diagram of the current sample hold circuit module signals, including D flip-flops I and the enable signal EN 2, V1 and V2 signals, primary switch control signal PG, PG or a signal V2 and , V1 and PG, V2 and the phase of the inductor current signal or includes the postage.

[0030] 本专利的特点及内容已揭示如上,然而本领域的技术人员可能基于本发明的说明而做种种不背离发明精神的替换及修改。 [0030] Characteristics of this patent has been disclosed above, those skilled in the art based on the description of the present invention may be made of various substitutions and modifications without departing from the spirit of the invention. 因此,本发明的保护范围应不局限于上述的实施方案,而应包含各种不背离本发明的替换和修改,并为权利要求书所涵盖。 Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be included without departing from the invention, various alterations and modifications, and is encompassed by the claims.

Claims (2)

  1. 1.一种减小单电感双输出变换器输出电压稳态误差的方法,单电感双输出变换器的控制电路中,主环采用峰值电流环模式,决定变换器两路负载电流之和,即流过变换器电感L的总电流平均值Iy次环采用电压模式,决定电感电流L在两路输出中的分配,主环设有误差放大器、比较器、触发器和驱动和死区控制电路,误差放大器同相端输入参考电压VKEF1,反相端输入0.4X (V0l+V02),U02分别是变换器的两路输出电压,误差放大器的输出V。 1. A method of reducing the inductance of a single dual-output inverter output voltage steady state error, the control circuit unit inductor dual output converter, the primary ring loop uses peak current mode, the converter determines two and load current, i.e., flowing through the transformer inductance L is the average value of the total current Iy secondary loop voltage-mode, L is the inductor current determines the output of the two distribution, with the primary ring error amplifiers, comparators, flip-flops and a drive control circuit and dead, to the positive input of the error amplifier reference voltage VKEF1, the inverting input terminal of 0.4X (V0l + V02), U02 are two inverter output voltage, the output of the error amplifier V. 连接比较器的反相输入端,斜坡电压Vrampl与采样的电感电流IJs信号叠加求和后连接比较器的同相输入端,比较器的输出和时钟信号分别输入触发器,触发器的输出连接驱动和死区控制电路的输入,驱动和死区控制电路输出信号PG控制主级开关的通断,其特征在于:当主环误差放大器采用无大电容补偿的低增益误差放大器时,在主环中增设一个电流采样保持电路,该电流采样保持电路的一个输入信号为采样的电感电流IJs信号,电流采样保持电路输出的直流电平Vd。 Inverting input terminal connected to an inverting input terminal of the comparator, the inductor current signal is superimposed summing IJs connection Vrampl ramp voltage comparator with the sampled comparator output signals and clock input flip-flop, the flip-flop output is connected to a drive and deadband control input circuit, drivers and dead-time control circuit outputs a signal PG control on and off of the main stage switches, wherein: when the main loop error amplifier uses the low-gain error amplifier no large capacitance compensation, addition of a major ring current sample and hold circuit, the current sampling an input signal to the sample hold circuit IJs inductor current signal, the current output from the sample hold circuit DC level Vd. 与斜坡电压Vrampl叠加求和后产生新的斜坡电压Vmp2再与采样的电感电流IljRs信号叠加求和后作为比较器同相输入端的输入电压Vs6ns6,同时将误差放大器的输出V。 And a new ramp voltage Vrampl Vmp2 ramp voltage superimposed upon the inductor current and then summed IljRs summing the sampled signal is superimposed as a comparator noninverting input terminal of the input voltage Vs6ns6, while the output of the error amplifier V. 叠加上一个直流电平Vdetl得到比较器的反相端输入信号Ve,该信号Ve也是电流采样保持电路的另一个输入信号,所叠加直流电平Vtkci应满足比较器反相端输入信号值Ve等于变换器满负载时比较器同相端输入信号Vsmsej的最大值Vp, Vp的值随负载变化,变换器满负载时达到最大,vs6ns6=vp-v。 Superimposed on a DC level obtained Vdetl comparator inverting input terminal of signal Ve, the signal Ve is also a current sampling signal holding circuit, the other input of the superimposed DC level Vtkci should satisfy the inverting input terminal of the inverter is equal to the signal value Ve comparator inverting input terminal of the full load maximum Vsmsej Vp, Vp is the value varies with load, maximum, vs6ns6 = vp-v converter when full load. ,此时比较器输出的信号经过D触发器和驱动和死区控制电路输出的主级开关控制信号PG,能够给变换器电感足够的充电时间,从而减小变换器输出电压的稳态误差。 , The comparator output signal at this time via the D flip-flops and a drive control circuit outputs a dead zone and a main stage the PG switching control signal, the converter inductor can give a sufficient charging time, thereby reducing the steady-state error of the inverter output voltage.
  2. 2.根据权利要求1所述方法中所增设的电流采样保持电路,其特征在于:包括控制信号V1和V2产生电路、D触发器使能信号EN产生电路、电感电流采样保持选通信号S1和S2产生电路、直流电平Vd。 A method according to the current claim as an additional sample and hold circuit comprising: a control signal generating circuit V1 and V2, D flip-flop circuit generating the enable signal EN, the inductor current sampling and holding strobe S1 S2 generating circuit, DC level Vd. 产生电路和在斜坡电压Vmp1上叠加直流电压Vd。 DC voltage generating circuit and superimposed on the ramp voltage Vmp1 Vd. 叠加求和后产生新的斜坡电压Vmip2的电路; 控制信号%和%产生电路包括四个D触发器D0、D1、D2、D3,两个与非门NAND1、NAND2,触发器DO的输入端D与输出端&短接并连接与非门NANDl的一个输入端,与非门NANDl的另一个输入端连接时钟信号CLK,与非门NANDl的输出端连接触发器DO的时钟端,触发器DO的输出端Q分别连接触发器Dl、D2的使能端,触发器Dl的输入端D与输出端^短接并连接触发器D2的时钟端,触发器Dl的输出端Q空接,与非门NAND2的一个输入端连接触发器D2的输入端D和输出端&,与非门NAND2的另一个输入端连接时钟信号CLK,与非门NAND2的输出端连接触发器Dl的时钟端,触发器D2的输出端Q连接触发器D3的使能端并作为控制信号V2的输出端,触发器D3的时钟端连接时钟信号CLK,触发器D3的输入端D与输出端g短接,触发器D3的输出端Q为控制信号V1的输出端; D触发器使能信 Superimposing a new ramp voltage summing circuit after Vmip2;% and the control signal generating circuit comprises four% D flip-flops D0, D1, D2, D3, and two NAND gates NAND1, NAND2, the input terminal D of the flip-flop DO & shorted and connected to one input of NAND gate NANDl connected to the output of the other input terminal of the NAND gate NANDl clock signal CLK, the output of the NAND gate is connected to the clock terminal of the flip NANDl DO, the DO of the flip-flop a clock terminal flip-flop output Q is connected Dl, D2 enable terminal, an output terminal and the input terminal D of the flip-Dl ^ shorted and connected to the flip-flop D2, an output terminal Q of the flip-flop Dl empty then, NAND gate a trigger input of NAND2 is connected to an input terminal D2 of the D & and an output terminal connected to the clock signal CLK to the other input of the NAND gate NAND2, and the output of the NAND gate NAND2 is connected to a clock terminal of the flip-flop Dl, D2 trigger the output terminal Q of the flip-flop that the connected terminal D3 can be used as an output terminal and a control signal V2, the flip-flop clock terminal D3 is connected to the clock signal CLK, the D flip-flop D3 the input terminal and the output terminal g shorted, the flip-flop D3 output Q output of the control signal V1; D flip-flop enable signal 号EN产生电路包括两个比较器COMP1、COMP2和一个同或门,比较器COMPU COMP2的同相端分别连接电压信号Vh和\,比较器COMPl、C0MP2的反相端互连并连接变换器的两路输出电压差Vtll-Vtl2, Vh和\均选取为(Vtjl-VJ X (I ±2%),比较器COMPl和C0MP2的输出分别连接同或门的两个输入端,同或门的输出端产生使能信号EN连接至控制信号V1和V2产生电路中触发器DO的使能端; 电感电流采样保持选通信号S1和S2产生电路包括两个或门0R1、0R2,与门AND,非门N0T,或门ORl的两个输入端分别连接主级开关控制信号PG及控制信号V2,或门ORl的输出连接与门AND的一个输入端,与门AND的另一个输入端连接控制信号V1,与门AND的输出连接或门0R2的一个输入端,或门0R2的另一个输入端连接使能信号EN,或门0R2的输出连接非门NOT的输入端并作为选通信号S1输出端,非门NOT的输出端为选通信号S2输出端; 直流 No. EN generation circuit comprises a noninverting terminal of two comparators COMP1, COMP2 and a NOR gate, the comparator COMPU COMP2 are connected to the voltage signal Vh and \ comparator COMPl, and an inverting terminal connected to the inverter C0MP2 interconnect two the output terminal of the voltage difference output Vtll-Vtl2, Vh and \ are selected to (Vtjl-VJ X (I ± 2%), and the comparator COMPl C0MP2 output respectively connected with two inputs of the oR gate, the oR gate with generates an enable signal EN coupled to the control signal generation circuit V1 and V2 enable terminal of flip-flops DO; inductor current sample and hold gate signal S1 and S2 generating circuit comprises two oR gates 0R1,0R2, the aND gate aND, NAND gate N0T, or the two input terminals respectively connected to the gate ORl primary switch control signal PG and the control signal V2, a first input terminal connected to the output of the aND gate aND gate ORl, and connected to the other input terminal of aND gate control signal V1, aND gate connected to an output terminal or an input gate 0R2 or 0R2 other input terminal of gate connected to the enable signal EN, the output of the oR gate 0R2 connected to the input of NAND gate NOT gate signal S1 as an output terminal, the non- NOT output of AND gate strobe signal S2 is output; DC 平1产生电路包括控制开关1(1、1(2、1(3,电容(:1、(:2,运算放大器、缓冲器,控制开关1^的一端连接电感电流IJs信号,控制开关K1的另一端连接电容C1的一端并通过控制开关K2接地,电容C1的另一端与运算放大器的反相端、电容C2的一端以及控制开关K3的一端连接,电容C2和控制开关K3的另一端与运算放大器的输出端及缓冲器的输入端连接在一起,运算放大器的同相端接地,控制开关1、K2, K3的控制端分别连选通信号Sp S2, S1,接缓冲器的输出与信号V6及斜坡电压Vraiipl三者叠加求和后产生直流电平vd。 A level generating circuit 1 includes a control switch (1,1 (2,1 (3, capacitor (: 1, (: 2, an operational amplifier, a buffer, a control switch connected to one end of the inductor current ^ IJs signal control switch K1 is the other end is connected to one end of capacitor C1 and ground K2 by controlling the switch, the inverting terminal of the capacitor C1 and the other end of the operational amplifier, and one end of capacitor C2 is connected to one end of a control switch K3, K3 capacitor C2 and the other end of the control switch of the operational an input terminal and an output terminal of the buffer amplifier are connected together, with the phase of the operational amplifier is grounded, a control switch, a control terminal K2, K3 are respectively connected strobe signal Sp S2, S1, and then the buffer output signals V6 and ramp voltage generating Vraiipl three superimposed DC level vd after summation. 输出; 在斜坡电压Vrampl上叠加直流电压Vd。 Output; DC voltage Vd is superimposed on the ramp voltage Vrampl. 后产生新的斜坡电压Vramp2的电路包括电流源1、NMOS管MN1、Mn2, PMOS管MP1、Mp2,控制开关K4、K5及电容C3,电流源I的正端连接电源Vdd,电流源I的负端与NMOS管Mni的漏极和栅极以及NMOS管Mn2的栅极连接,NMOS管MN1、MN2的源极接地,NMOS管Mn2的漏极与PMOS管Mpi的漏极和栅极以及PMOS管Mp2的栅极连接,PMOS管Mn、Mp2的源极连接电源Vdd,PMOS管Mp2的漏极连接开关K4的一端,开关K4的另一端与开关K5的一端和电容C3的一端连接并作为新的斜坡电压信号Vramp2的输出端,开关K5的另一端和电容C3的另一端连接并连接直流电平Vd。 Negative After generating a new ramp voltage Vramp2 circuit includes a current source 1, NMOS tube MN1, Mn2, PMOS tube MP1, Mp2, control switch K4, K5 and the capacitor C3, the positive terminal of the current source I is connected to the power supply Vdd, the current source I is the gate terminal of the NMOS transistor Mni and the gate and drain of the NMOS transistor Mn2, NMOS transistors MN1, MN2 of the source is grounded, and the drain of PMOS transistor Mpi drain and the gate of the NMOS transistor Mn2 and the PMOS transistor Mp2 a source connected to the gate, PMOS transistor Mn, Mp2 is connected to the power supply Vdd, the drain connected to one end of the switching PMOS transistor Mp2 and K4, K4 switch and the other end connected to one end of the end of the switch K5 of the capacitor C3 as a new ramp Vramp2 the output of the voltage signal, the other terminal of the switch K5 and the other end connected to the capacitor C3 is connected and the DC level Vd. ,开关K5、K4的控制端分别连接时钟控制信号CLK及CLK的反信号 , Switch K5, K4 are connected to the control terminal of the control clock signal CLK and the inverted signal CLK
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106208684A (en) * 2016-08-24 2016-12-07 西南交通大学 Combined dynamic continuous-flow control method and device of pseudo-continuous conduction mode single-inductor double-output switching converter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2437556A (en) * 2006-04-26 2007-10-31 Wolfson Microelectronics Plc Current mode switching regulator
CN101795070A (en) * 2010-04-02 2010-08-04 日银Imp微电子有限公司 System for linearly adjusting slope compensation voltage slope
CN102324845A (en) * 2011-09-23 2012-01-18 东南大学 Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2437556A (en) * 2006-04-26 2007-10-31 Wolfson Microelectronics Plc Current mode switching regulator
CN101795070A (en) * 2010-04-02 2010-08-04 日银Imp微电子有限公司 System for linearly adjusting slope compensation voltage slope
CN102324845A (en) * 2011-09-23 2012-01-18 东南大学 Control method for single-inductance double-output DC-DC (direct current) switching power supply and circuit thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
刘松: "电源变换器中电流模式和电压模式相互转化", 《电焊机》, vol. 41, no. 3, 31 March 2011 (2011-03-31), pages 28 - 31 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106208684A (en) * 2016-08-24 2016-12-07 西南交通大学 Combined dynamic continuous-flow control method and device of pseudo-continuous conduction mode single-inductor double-output switching converter

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