CN105515558A - Method for controlling soft start time by multiple times of charging - Google Patents
Method for controlling soft start time by multiple times of charging Download PDFInfo
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- CN105515558A CN105515558A CN201510916111.1A CN201510916111A CN105515558A CN 105515558 A CN105515558 A CN 105515558A CN 201510916111 A CN201510916111 A CN 201510916111A CN 105515558 A CN105515558 A CN 105515558A
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- effect transistor
- field effect
- type field
- inverter
- signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Abstract
The invention discloses a method for controlling soft start time by multiple times of charging. A ramp signal generating circuit, a ramp signal reshaping circuit, a soft start control signal generating circuit and a feedback control circuit, which charge an MOS (Metal Oxide Semiconductor) capacitor, charge initial signals for multiple times, so as to fulfill the purpose of controlling the soft start time. The method can ensure the operation time of following modules, so that the following modules make an accurate judgment and then the reliability of a system is improved.
Description
Technical field
The present invention relates to technical field of integrated circuits, be specifically related to a kind of method that utilization repeatedly charges to control soft-start time.
Background technology
Along with the flourishing discovery of hyundai electronics information industry, electronic product is to development in pluralism.Do not have to charge or the soft starting device that for once charges has lacked the flexibility of design and effective utilization of resource in system, in the design of Modern New electronic system, just embodied significant limitation.Because soft starting device judges for subsequent module provides enough time to do, namely a time-delay mechanism is equivalent to, the soft starting device so not charging or for once charge, because the operation time of subsequent module cannot be ensured, thus accurate judgement cannot be made, thus reduce the reliability of system.
Summary of the invention
Object of the present invention is just to provide a kind of utilization repeatedly to charge to control the method for soft-start time to solve the problem.
The present invention is achieved through the following technical solutions above-mentioned purpose:
The method controlling soft-start time is repeatedly charged in a kind of utilization, by the ramp generator, ramp signal shaping circuit, soft start control signal circuit for generating and the feedback control circuit that charge to mos capacitance, initialize signal is repeatedly charged, to reach the object controlling soft-start time.
Particularly, the ramp signal output of the described ramp generator to mos capacitance charging is connected with the ramp signal input of described ramp signal shaping circuit, the feedback signal terminal of described feedback control circuit is connected with the described feedback signal terminal to the ramp generator that mos capacitance charges, the signal output part of described ramp signal shaping circuit is connected with the signal input part of described soft start control signal circuit for generating, the signal input part access reset signal of the described ramp generator to mos capacitance charging, the signal output part of described soft start control signal circuit for generating is as the output control signal end of whole circuit module.
More specifically, the described ramp generator to mos capacitance charging comprises three N-type field effect transistor and two P type field effect transistor, the drain electrode of N-type field effect transistor described in first simultaneously with the source electrode of P type field effect transistor described in first, the drain electrode of P type field effect transistor described in second is connected with the drain electrode of N-type field effect transistor described in second, the source electrode of N-type field effect transistor described in first is connected with the grid of N-type field effect transistor described in the drain electrode and the 3rd of P type field effect transistor described in first simultaneously, the source electrode of P type field effect transistor described in second is connected with the drain electrode of P type field effect transistor described in the 3rd, the source electrode of P type field effect transistor described in 3rd, the substrate pole of P type field effect transistor described in 3rd, described in the substrate pole and first of P type field effect transistor described in second, the substrate of P type field effect transistor extremely all accesses power supply, the substrate pole of N-type field effect transistor described in first, the source electrode of N-type field effect transistor described in 3rd, the drain electrode of N-type field effect transistor described in 3rd, the substrate pole of N-type field effect transistor described in the 3rd, the substrate of N-type field effect transistor described in the source electrode and second of N-type field effect transistor described in second is ground connection extremely all.
More specifically, described ramp signal shaping circuit comprises four inverters I and a NAND gate I, described in inverter I described in first and second, inverter I is connected on two inputs of described NAND gate I respectively, inverter I described in inverter I described in 3rd and the 4th is connected on the output of described NAND gate I after connecting, and inverter I described in inverter I described in first and second is by the PMOS composition of a NMOS tube and multiple series connection.
More specifically, described soft start control signal circuit for generating comprises three inverters II, a d type flip flop, a chain of inverters, a NOR gate I and a NAND gate II, described in first, inverter II is connected on the trigger end of described d type flip flop, the output of described d type flip flop is connected with the input of described chain of inverters and the first input end of described NOR gate I simultaneously, the output of described chain of inverters is connected with the second input of described NOR gate I, the output of described NOR gate I is connected with the input of inverter described in second II, the output of inverter II described in second is connected on one of them input of described NAND gate II, described 3rd inverter II is connected on the output of described NAND gate II, described chain of inverters is formed by multiple inverter series.
More specifically, described feedback control circuit comprises five inverters III and a NOR gate II, described first inverter III is connected on the first input end of described NOR gate II, described second inverter III, described 3rd inverter III and described 4th inverter III are connected successively and are attempted by the second input of described NOR gate II, described second inverter III is made up of the NMOS tube of a PMOS and multiple series connection, and described 5th inverter III is connected on the output of described NOR gate II.
Beneficial effect of the present invention is:
The present invention can ensure the operation time of subsequent module, thus makes subsequent module make accurate judgement, thus improves the reliability of system, and involved hardware configuration is simple, can save control port to reduce the cost of system.
Accompanying drawing explanation
Fig. 1 is logic diagram of the present invention;
Fig. 2 is the ramp generator to mos capacitance charging of the present invention;
Fig. 3 is ramp signal shaping circuit of the present invention;
Fig. 4 is soft start control signal circuit for generating of the present invention;
Fig. 5 is feedback control circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 1, the present invention is repeatedly charged to initialize signal by ramp generator, ramp signal shaping circuit, soft start control signal circuit for generating and the feedback control circuit charged to mos capacitance, to reach the object controlling soft-start time.The ramp signal output of ramp generator of mos capacitance charging is connected with the ramp signal input of ramp signal shaping circuit, the feedback signal terminal of feedback control circuit is connected with the feedback signal terminal of the ramp generator of charging to mos capacitance, the signal output part of ramp signal shaping circuit is connected with the signal input part of soft start control signal circuit for generating, to the signal input part access reset signal of the ramp generator of mos capacitance charging, the signal output part of soft start control signal circuit for generating is as the output control signal end of whole circuit module.
As shown in Figure 2, three N-type field effect transistor and two P type field effect transistor are comprised to the ramp generator of mos capacitance charging, the drain electrode of the first N-type field effect transistor simultaneously with the source electrode of a P type field effect transistor, the drain electrode of the 2nd P type field effect transistor is connected with the drain electrode of the second N-type field effect transistor, the source electrode of the first N-type field effect transistor is connected with the drain electrode of a P type field effect transistor and the grid of the 3rd N-type field effect transistor simultaneously, the source electrode of the 2nd P type field effect transistor is connected with the drain electrode of the 3rd P type field effect transistor, the source electrode of the 3rd P type field effect transistor, the substrate pole of the 3rd P type field effect transistor, the substrate pole of the 2nd P type field effect transistor and the substrate of a P type field effect transistor extremely all access power supply, the substrate pole of the first N-type field effect transistor, the source electrode of the 3rd N-type field effect transistor, the drain electrode of the 3rd N-type field effect transistor, the substrate pole of the 3rd N-type field effect transistor, the source electrode of the second N-type field effect transistor and the substrate of the second N-type field effect transistor be ground connection extremely all.
To the ramp generator of mos capacitance charging, mainly by charging to mos capacitance, produce ramp signal, and pass through the level value of corresponding control signals initialize signal, reach the object of repeatedly charging.
As shown in Figure 3, ramp signal shaping circuit comprises four inverters I and a NAND gate I, first inverter I and the second inverter I are connected on two inputs of NAND gate I respectively, be connected on the output of NAND gate I after 3rd inverter I and the series connection of the 4th inverter I, the first inverter I and the second inverter I are by the PMOS composition of a NMOS tube and multiple series connection.
Ramp signal shaping circuit carries out shaping by a logical circuit (being equivalent to or computing) to initialize signal, and the output signal of generation is as the control signal of soft start control signal circuit for generating.
As shown in Figure 4, soft start control signal circuit for generating comprises three inverters II, a d type flip flop, a chain of inverters, a NOR gate I and a NAND gate II, first inverter II is connected on the trigger end of d type flip flop, the output of d type flip flop is connected with the input of chain of inverters and the first input end of NOR gate I simultaneously, second input of the output AND OR NOT gate I of chain of inverters connects, the output of NOR gate I is connected with the input of the second inverter II, the output of the second inverter II is connected on one of them input of NAND gate II, 3rd inverter II is connected on the output of NAND gate II, chain of inverters is formed by multiple inverter series.
Soft start control signal circuit for generating produces a control signal, as the input signal of feedback control circuit by a d type flip flop and corresponding logical circuit.
As shown in Figure 5, feedback control circuit comprises five inverters III and a NOR gate II, first inverter III is connected on the first input end of NOR gate II, second inverter III, the 3rd inverter III and the 4th inverter III are connected successively and are attempted by the second input of NOR gate II, second inverter III is made up of the NMOS tube of a PMOS and multiple series connection, and the 5th inverter III is connected on the output of NOR gate II.
Feedback control circuit is by carrying out logical operation (being equivalent to NAND operation) to initialize signal and soft start control signal, the output signal produced is as the control signal of the ramp generator of charging to mos capacitance, control the level of initialize signal, thus reach the object of repeatedly charging.
Roman number in foregoing is for distinguishing the identical components and parts in different circuit section.
Involved in the present invention to hardware architecture be the logic diagram shown in Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 are respectively the concrete schematic diagram of four involved circuit, and being linked together by the identical characters end marked out in Fig. 2, Fig. 3, Fig. 4 and Fig. 5 just constitutes the whole hardware structure circuit arrived involved in the present invention.
As Fig. 2, Fig. 3, circuit theory diagrams shown in Fig. 4 and Fig. 5, initial time, initialize signal (IBIAS signal) is low level, and grid (the connecing READY_L signal) voltage receiving the NMOS tube on ground is low level, this NMOS tube is ended, the PMOS conducting controlled by READY_L, receive PMOS cut-off (initial condition because of CTR signal is high level) of power supply, now, initialize signal (IBIAS signal) by charging to mos capacitance, voltage is made slowly to increase, produce a ramp voltage signal, when voltage rise is to a certain set point (regulating this set point by regulating in inverter INV_H the number of PMOS of connecting), READY_L is made to become high level by feedback control circuit, receive the NMOS tube conducting on ground, now initialize signal (IBIAS signal) is connected to the ground, its voltage becomes low level, this process is boost process 1, after initialize signal (IBIAS signal) becomes low level again, after feedback control circuit by initialize signal (IBIAS signal), READY_L signal becomes high level again, now, initialize signal (IBIAS signal) slowly boosts, but this time when signal boosts to a certain set point, can not suddenly change to low level again, this is the principle of the edging trigger utilizing d type flip flop (DFF), namely there is not saltus step due to the level of the clock end of d type flip flop in this, so, in this boost process, initialize signal (IBIAS signal) boosts to a certain fixed voltage value (number of the NMOS tube that this fixed voltage value and the inverter INV_L that is connected with initialize signal (IBIAS signal) connect is relevant) always, this process is boost process 2, when being enough to when initialize signal (IBIAS signal) boosts to fixed voltage value, inverter overturns, now, pass through feedback control circuit, the signal CTR receiving the PMOS of power supply in the ramp signal generating circuit to mos capacitance charging is made to become low level, now, this PMOS conducting, initialize signal (IBIAS signal) directly receives power supply, the voltage jump of initialize signal (IBIAS signal) is to supply voltage, and this process is boost process 3.Owing to being by charging to mos capacitance, so voltage slowly rises; And in first time boost process, become low level again when voltage is raised to fixed value, i.e. repeatedly boost charge.Above two reasons, make soft-start time be controlled, thus ensure that the reliability of system.
Two kinds of communication protocols that the present invention is compatible, to control multi-center selection, for system provides sizable flexibility, can adapt to more system.Reasonably control mode can be selected according to the situation of I/O resource when system.Can select to carry out controlling with specific pin the complexity that is conducive to like this reducing system in the resourceful situation of I/O; Then can select when I/O resource scarcity to control by the mode of a key pulse complexing pin, control port can be saved to reduce the cost of system.
Illustrate: the components and parts in this patent do not limit model, be applicable to general components and parts, wherein, NMOS represents N-type field effect transistor, PMOS represents P type field effect transistor, INV represents inverter, INV_CHAIN represents the chain of inverters (number of the inverter of series connection is determined on a case-by-case basis) of multiple inverter series composition, the inverter (number of the NMOS tube of series connection is determined on a case-by-case basis) that INV_L representative is made up of the NMOS tube of a PMOS and multiple series connection, the inverter (number of the PMOS of series connection is determined on a case-by-case basis) that INV_H representative is made up of the PMOS of a NMOS tube and multiple series connection, NAND represents NAND gate, NOR represents NOR gate, DFF represents d type flip flop.
These are only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included in protection scope of the present invention.
Claims (6)
1. the method controlling soft-start time is repeatedly charged in a utilization, it is characterized in that: by the ramp generator, ramp signal shaping circuit, soft start control signal circuit for generating and the feedback control circuit that charge to mos capacitance, initialize signal is repeatedly charged, to reach the object controlling soft-start time.
2. the method controlling soft-start time is repeatedly charged in utilization according to claim 1, it is characterized in that: the ramp signal output of the described ramp generator to mos capacitance charging is connected with the ramp signal input of described ramp signal shaping circuit, the feedback signal terminal of described feedback control circuit is connected with the described feedback signal terminal to the ramp generator that mos capacitance charges, the signal output part of described ramp signal shaping circuit is connected with the signal input part of described soft start control signal circuit for generating, the signal input part access reset signal of the described ramp generator to mos capacitance charging, the signal output part of described soft start control signal circuit for generating is as the output control signal end of whole circuit module.
3. the method controlling soft-start time is repeatedly charged in utilization according to claim 2, it is characterized in that: the described ramp generator to mos capacitance charging comprises three N-type field effect transistor and two P type field effect transistor, the drain electrode of N-type field effect transistor described in first simultaneously with the source electrode of P type field effect transistor described in first, the drain electrode of P type field effect transistor described in second is connected with the drain electrode of N-type field effect transistor described in second, the source electrode of N-type field effect transistor described in first is connected with the grid of N-type field effect transistor described in the drain electrode and the 3rd of P type field effect transistor described in first simultaneously, the source electrode of P type field effect transistor described in second is connected with the drain electrode of P type field effect transistor described in the 3rd, the source electrode of P type field effect transistor described in 3rd, the substrate pole of P type field effect transistor described in 3rd, described in the substrate pole and first of P type field effect transistor described in second, the substrate of P type field effect transistor extremely all accesses power supply, the substrate pole of N-type field effect transistor described in first, the source electrode of N-type field effect transistor described in 3rd, the drain electrode of N-type field effect transistor described in 3rd, the substrate pole of N-type field effect transistor described in the 3rd, the substrate of N-type field effect transistor described in the source electrode and second of N-type field effect transistor described in second is ground connection extremely all.
4. the method controlling soft-start time is repeatedly charged in utilization according to claim 2, it is characterized in that: described ramp signal shaping circuit comprises four inverters I and a NAND gate I, described in inverter I described in first and second, inverter I is connected on two inputs of described NAND gate I respectively, inverter I described in inverter I described in 3rd and the 4th is connected on the output of described NAND gate I after connecting, and inverter I described in inverter I described in first and second is by the PMOS composition of a NMOS tube and multiple series connection.
5. the method controlling soft-start time is repeatedly charged in utilization according to claim 2, it is characterized in that: described soft start control signal circuit for generating comprises three inverters II, a d type flip flop, a chain of inverters, a NOR gate I and a NAND gate II, described in first, inverter II is connected on the trigger end of described d type flip flop, the output of described d type flip flop is connected with the input of described chain of inverters and the first input end of described NOR gate I simultaneously, the output of described chain of inverters is connected with the second input of described NOR gate I, the output of described NOR gate I is connected with the input of inverter described in second II, the output of inverter II described in second is connected on one of them input of described NAND gate II, described 3rd inverter II is connected on the output of described NAND gate II, described chain of inverters is formed by multiple inverter series.
6. the method controlling soft-start time is repeatedly charged in utilization according to claim 2, it is characterized in that: described feedback control circuit comprises five inverters III and a NOR gate II, described first inverter III is connected on the first input end of described NOR gate II, described second inverter III, described 3rd inverter III and described 4th inverter III are connected successively and are attempted by the second input of described NOR gate II, described second inverter III is made up of the NMOS tube of a PMOS and multiple series connection, and described 5th inverter III is connected on the output of described NOR gate II.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510916111.1A CN105515558B (en) | 2015-12-10 | 2015-12-10 | A method of using repeatedly charging to control soft-start time |
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| CN201510916111.1A CN105515558B (en) | 2015-12-10 | 2015-12-10 | A method of using repeatedly charging to control soft-start time |
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| CN105515558A true CN105515558A (en) | 2016-04-20 |
| CN105515558B CN105515558B (en) | 2018-11-02 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060158170A1 (en) * | 2005-01-18 | 2006-07-20 | Thompsen Brett J | Clocked ramp apparatus for voltage regulator softstart and method for softstarting voltage regulators |
| US20110279045A1 (en) * | 2010-04-23 | 2011-11-17 | Rohm Co., Ltd. | Control circuit for switching power supply |
| US20120126765A1 (en) * | 2010-11-24 | 2012-05-24 | Stone John D | Circuit and system with soft-start functionality |
| CN103904875A (en) * | 2014-03-24 | 2014-07-02 | 合肥工业大学 | Digital soft start circuit in switching power source |
| CN104135146A (en) * | 2014-07-29 | 2014-11-05 | 广州金升阳科技有限公司 | Soft starting method and circuit |
-
2015
- 2015-12-10 CN CN201510916111.1A patent/CN105515558B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060158170A1 (en) * | 2005-01-18 | 2006-07-20 | Thompsen Brett J | Clocked ramp apparatus for voltage regulator softstart and method for softstarting voltage regulators |
| US20110279045A1 (en) * | 2010-04-23 | 2011-11-17 | Rohm Co., Ltd. | Control circuit for switching power supply |
| US20120126765A1 (en) * | 2010-11-24 | 2012-05-24 | Stone John D | Circuit and system with soft-start functionality |
| CN103904875A (en) * | 2014-03-24 | 2014-07-02 | 合肥工业大学 | Digital soft start circuit in switching power source |
| CN104135146A (en) * | 2014-07-29 | 2014-11-05 | 广州金升阳科技有限公司 | Soft starting method and circuit |
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| CN105515558B (en) | 2018-11-02 |
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Effective date of registration: 20191115 Address after: 710000 Room 0702, Unit 1, Block A, Jinqiao International Plaza, Science and Technology Road, Xi'an High-tech Zone, Shaanxi Province Patentee after: Shaanxi Zhongyou Silk Road Energy Co., Ltd. Address before: High tech Zone Gaopeng road in Chengdu city of Sichuan province 610041 5 block A No. 2 A-320 Patentee before: Chengdu Moyi Technology Co., Ltd. |