CN205015387U - Anti -interference low -voltage detection chip - Google Patents
Anti -interference low -voltage detection chip Download PDFInfo
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- CN205015387U CN205015387U CN201520764730.9U CN201520764730U CN205015387U CN 205015387 U CN205015387 U CN 205015387U CN 201520764730 U CN201520764730 U CN 201520764730U CN 205015387 U CN205015387 U CN 205015387U
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Abstract
The utility model belongs to the technical field of the integrated circuit technique and specifically relates to an anti -interference low -voltage detection chip. It is connected with recovery voltage and sets for the circuit including resistive voltage divider circuit, logical combination circuit, capacitor charging and discharging circuit and schmidt shaping circuit that the order is connected between resistive voltage divider circuit and the schmidt shaping circuit, logical combination circuit's input still is connected with circuit for generating a reference voltage. The utility model discloses a schmidt shaping circuit who sets up can make the wave form of whole chip output more stable, though utilize capacitor charging and discharging circuit to have certain time delay when whole chip moves, strengthened the interference immunity of chip, it is very little to make it receive external interference to make voltage detecting's result more accurate, set for recovery voltage that the circuit can greatly weaken and the relation between starting voltage and the resistive voltage divider circuit through the recovery voltage who sets up, strengthened input voltage's change nature, improve the detection precision, its circuit structure is simple, has very strong practical value and market spreading value.
Description
Technical field
The utility model relates to technical field of integrated circuits, especially a kind of anti-interference low voltage test chip.
Background technology
As everyone knows, voltage detecting circuit is for detecting service voltage, and when this change in voltage is to a certain setting value, voltage detecting circuit exports control signal; When we set this standard voltage value, wish that circuit accurately can detect and export corresponding control signal, existing voltage detecting circuit is easy to accomplish this point.
Fig. 1 shows the electrical schematic diagram of existing a kind of voltage detecting circuit, in the circuit, the input voltage of VIN end is through resistance R1, the dividing potential drop of resistance R2 and resistance R3 obtains voltage V1, connect with the positive pole of comparer, the negative pole of comparer and the VREF of reference voltage circuit hold pin to connect, the input of phase inverter connects the output of comparer, the output of phase inverter connects the grid of metal-oxide-semiconductor M2 in output circuit, the source electrode of metal-oxide-semiconductor M2 and Substrate ground, drain electrode is output signal, meanwhile, metal-oxide-semiconductor M2 is connected with the grid of metal-oxide-semiconductor M1, the source electrode of metal-oxide-semiconductor M1 and Substrate ground, drain electrode is connected between resistance R2 and resistance R3.When the voltage of setting VIN end makes V1 lower than (VIN is now cut-in voltage) during VREF, VOUT is high-impedance state; When the voltage setting VIN end makes V1 higher than VREF, VOUT is low level, but, once VOUT is low level (that is: the output of phase inverter is high level), when the voltage of setting VIN end makes V1 lower than VREF again, because the cut-in voltage of metal-oxide-semiconductor M1 has uprised than voltage during the first situation, this new magnitude of voltage is recovery voltage; In the process, the VREF that reference voltage circuit exports can not change with VIN change, thus realizes voltage detecting function according to the exporting change of VOUT.
But, although all voltage detecting circuits as shown in Figure 1 can produce when service voltage changes to setting value export control signal, also can setting recovery magnitude of voltage, the but following defect of ubiquity in actual applications:
1, anti-interference is weak, due to the existence of the undesired signal in the external world, makes testing result not accurate enough;
2, the ratio of recovery voltage and original cut-in voltage and resistance R1, resistance R2 and resistance R3 have relation, and variation inconvenience of getting up is also accurate not;
3, owing to being the detection to input voltage instantaneous value, thus cause outputing signal extremely unstable.
Therefore, how improving existing voltage detecting circuit, is relevant industries technical matterss urgently to be resolved hurrily.
Utility model content
For the deficiency that above-mentioned prior art exists, the purpose of this utility model is that a kind of circuit structure is simple, strong interference immunity, accuracy of detection are high, the anti-interference low voltage test chip of stable output signal.
To achieve these goals, the utility model adopts following technical scheme:
A kind of anti-interference low voltage test chip, it comprises:
For being realized the capacitor charge and discharge circuit that voltage exports by the discharge and recharge of electric capacity, described capacitor charge and discharge circuit is provided with power input;
For the logic combination circuit that control capacitance charge-discharge circuit opens and closes, the output terminal of described logic combination circuit is connected to the input end of capacitor charge and discharge circuit;
For providing the reference voltage generating circuit of reference voltage to logic combination circuit, the output terminal of described reference voltage generating circuit is connected to the input end of logic combination circuit;
For setting the resistor voltage divider circuit of the magnitude of voltage inputed in logic combination circuit, described resistor voltage divider circuit is connected to the input end of logic combination circuit, described resistor voltage divider circuit is provided with voltage sets end;
The schmidt shaping circuit that detection signal exports is realized after voltage for exporting capacitor charge and discharge circuit carries out Shape correction, described schmidt shaping circuit is connected to the output terminal of capacitor charge and discharge circuit, described schmidt shaping circuit is provided with detection signal output terminal;
With
Magnitude of voltage for exporting according to schmidt shaping circuit sets the recovery voltage initialization circuit of the ratio of resistor voltage divider circuit, and described recovery voltage initialization circuit is connected between the output terminal of schmidt shaping circuit and resistor voltage divider circuit.
Preferably, described capacitor charge and discharge circuit comprises the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, charge and discharge capacitance and the 5th resistance, grid and the grid of the 4th metal-oxide-semiconductor of described 3rd metal-oxide-semiconductor are connected the output terminal of logic combination circuit simultaneously, the drain electrode of described 3rd metal-oxide-semiconductor and the drain electrode of the 4th metal-oxide-semiconductor are connected to the two ends of the 5th resistance, the source electrode of described 3rd metal-oxide-semiconductor is connected power input with substrate simultaneously, the source electrode of described 4th metal-oxide-semiconductor and substrate ground connection simultaneously, one end ground connection of described charge and discharge capacitance, the other end are connected to the input end of schmidt shaping circuit.
Preferably, described recovery voltage initialization circuit comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor is connected the output terminal of schmidt shaping circuit with the grid of the second metal-oxide-semiconductor simultaneously, the source electrode of described first metal-oxide-semiconductor is connected voltage sets end with substrate simultaneously, the source electrode of described second metal-oxide-semiconductor and substrate ground connection simultaneously, the drain electrode of described first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor contact resistance bleeder circuit respectively.
Preferably, described schmidt shaping circuit comprises the Schmidt's shaping unit and the second phase inverter that are linked in sequence, the input end of described Schmidt's shaping unit is connected to the output terminal of capacitor charge and discharge circuit, the output terminal of described second phase inverter is as detection signal output terminal, and the grid of described first metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor are connected between the input end of the second phase inverter and the output terminal of Schmidt's shaping unit simultaneously.
Preferably, described resistor voltage divider circuit comprises first resistance of sequential series between voltage sets end and earth terminal, the second resistance, the 3rd resistance and the 4th resistance;
The input end of described logic combination circuit is connected between the second resistance and the 3rd resistance, and the drain electrode of described first metal-oxide-semiconductor is connected between the first resistance and the second resistance, and the drain electrode of described second metal-oxide-semiconductor is connected between the 3rd resistance and the 4th resistance.
Preferably, the resistance of described first resistance equals the resistance of the 4th resistance.
Preferably, described logic combination circuit comprises comparer and the first phase inverter, the output terminal that the positive pole of described comparer is connected between the first resistance and the second resistance, negative pole connects reference voltage generating circuit, output terminal connect the input end of the first phase inverter, and the output terminal of described first phase inverter connects the input end of capacitor charge and discharge circuit.
Owing to have employed such scheme, the waveform that the utility model can make whole chip export by the schmidt shaping circuit arranged is more stable; Although utilize capacitor charge and discharge circuit to have certain time delay when whole chip runs, enhance the anti-interference of chip, make it be subject to extraneous interference very little, thus make the result of voltage detecting more accurate; The recovery voltage that can greatly be weakened by the recovery voltage initialization circuit arranged and the relation between trigger voltage and resistor voltage divider circuit, enhance the mobility of input voltage, improves accuracy of detection; Its circuit structure is simple, strong interference immunity, accuracy of detection are high, accurately it is easy to adjustment to testing result, has very strong practical value and market popularization value.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of voltage detecting circuit of the prior art;
Fig. 2 is the schematic diagram of the utility model embodiment;
Fig. 3 is the circuit structure diagram of the utility model embodiment.
Embodiment
Be described in detail to embodiment of the present utility model below in conjunction with accompanying drawing, the multitude of different ways that requirement limits and covers but the utility model can be had the right is implemented.
As shown in Figures 2 and 3, the anti-interference low voltage test chip of the one that the utility model embodiment provides, it comprises:
Capacitor charge and discharge circuit 1, is mainly used in the output being realized voltage by the discharge and recharge of electric capacity, capacitor charge and discharge circuit 1 is provided with power input VDD;
Logic combination circuit 2, is mainly used in control capacitance charge-discharge circuit 1 open/close states, thus the charging and discharging state of the electric capacity of control capacitance charge-discharge circuit 1, its output terminal is connected to the input end of capacitor charge and discharge circuit 1;
Reference voltage generating circuit 3, be mainly used in providing reference voltage V ref to logic combination circuit 2, its output terminal is connected to the input end of logic combination circuit 2;
Resistor voltage divider circuit 4, be mainly used in setting the magnitude of voltage inputed in logic combination circuit 2, thus make logic combination circuit 2 by benchmark voltage Vref and set the charging and discharging state that the voltage inputted carrys out the electric capacity of control capacitance charge-discharge circuit 1, resistor voltage divider circuit 4 is connected to the input end of logic combination circuit 2, is provided with voltage sets end Vin on resistor voltage divider circuit 4 simultaneously;
Schmidt shaping circuit 5, the output of detection signal is realized after being mainly used in that Shape correction is carried out to the voltage that capacitor charge and discharge circuit 1 exports, it is connected to the output terminal of capacitor charge and discharge circuit 1, is provided with detection signal output end vo ut on schmidt shaping circuit 5 simultaneously;
With
Recovery voltage initialization circuit 6, the magnitude of voltage being mainly used in exporting according to schmidt shaping circuit 5 sets the ratio of resistor voltage divider circuit 4, it is connected between the output terminal of schmidt shaping circuit 5 and resistor voltage divider circuit 4, operationally, the magnitude of voltage of the detection signal exported by schmidt shaping circuit 5 controls the on off state of recovery voltage initialization circuit 6, thus sets trigger voltage and recovery voltage by recovery voltage initialization circuit 6.
So, schmidt shaping circuit 5 waveform that whole chip can be made to export by arranging is more stable; Although utilize capacitor charge and discharge circuit 1 to have certain time delay when whole chip runs, enhance the anti-interference of chip, make it be subject to extraneous interference very little, thus make the result of voltage detecting more accurate; The recovery voltage that can greatly be weakened by the recovery voltage initialization circuit 6 arranged and the relation between trigger voltage and resistor voltage divider circuit 4, enhance the mobility of input voltage.
For optimizing the circuit structure of whole chip, ensure the performance of whole chip, the capacitor charge and discharge circuit 1 of the present embodiment comprises the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, charge and discharge capacitance C1 and the 5th resistance R5; Wherein, 3rd metal-oxide-semiconductor M3 is enhancing P channel MOS transistor, the 4th metal-oxide-semiconductor M4 is enhancement mode N-channel MOS transistor, grid and the grid of the 4th metal-oxide-semiconductor M4 of the 3rd metal-oxide-semiconductor M3 are connected the output terminal of logic combination circuit 2 simultaneously, the drain electrode of the 3rd metal-oxide-semiconductor M3 and the drain electrode of the 4th metal-oxide-semiconductor M4 are connected to the two ends of the 5th resistance R5, the source electrode of the 3rd metal-oxide-semiconductor M3 is connected power input VDD with substrate simultaneously, the source electrode of the 4th metal-oxide-semiconductor M4 and substrate ground connection simultaneously, one end ground connection of charge and discharge capacitance C1, the other end are connected to the input end of schmidt shaping circuit 5.
The recovery voltage initialization circuit 6 of the present embodiment comprises the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2; Wherein, first metal-oxide-semiconductor M1 is for strengthening P channel MOS transistor, the second metal-oxide-semiconductor M2 for strengthening N-channel MOS transistor, grid and the grid of the second metal-oxide-semiconductor M2 of the first metal-oxide-semiconductor M1 are connected the output terminal of schmidt shaping circuit 5 simultaneously, and the source electrode of the first metal-oxide-semiconductor M1 and substrate are connected voltage sets end Vin simultaneously, the source electrode of the second metal-oxide-semiconductor M2 and substrate ground connection simultaneously, the drain electrode of the first metal-oxide-semiconductor M1 and the drain electrode of the second metal-oxide-semiconductor M1 contact resistance bleeder circuit 4 respectively.
The schmidt shaping circuit 5 of the present embodiment comprises the Schmidt's shaping unit 51 and the second phase inverter A2 that are linked in sequence, the input end of Schmidt's shaping unit 51 is connected to the output terminal of capacitor charge and discharge circuit 1, the output terminal of the second phase inverter A2 as detection signal output end vo ut, between the input end that the grid of the first metal-oxide-semiconductor M1 and the grid of the second metal-oxide-semiconductor M2 are connected to the second phase inverter A2 simultaneously and the output terminal of Schmidt's shaping unit 51.
The resistor voltage divider circuit 4 of the present embodiment comprises the first resistance R1 of sequential series between voltage sets end Vin and earth terminal, the second resistance R2, the 3rd resistance R3 and the 4th resistance R4; Wherein, the input end of logic combination circuit 2 is connected between the second resistance R2 and the 3rd resistance R3, the drain electrode of the first metal-oxide-semiconductor M1 is connected between the first resistance R1 and the second resistance R2, and the drain electrode of the second metal-oxide-semiconductor M2 is connected between the 3rd resistance R3 and the 4th resistance R4.For improving the variability of input voltage, weaken recovery voltage and the relation between cut-in voltage and each resistance, to improve the precision of voltage detecting, the first resistance R1 of the present embodiment is equal with the resistance of the 4th resistance R4.
Further, the logic combination circuit 2 of the present embodiment comprises comparer Q and the first phase inverter A1, the output terminal that the positive pole of comparer Q is connected between the first resistance R1 and the second resistance R2, negative pole connects reference voltage generating circuit 3, output terminal connect the input end of the first phase inverter A1, and the output terminal of the first phase inverter A1 then connects the input end of capacitor charge and discharge circuit 1 (i.e. the grid of the 3rd metal-oxide-semiconductor M3 and the grid of the 4th metal-oxide-semiconductor M4).
For the superiority of the detection chip of the present embodiment clearly can be showed, its principle of work is as follows: resistor voltage divider circuit 4 is used for producing the voltage V1 of input comparator Q, the output of the first phase inverter A1 in logic combination circuit 2 is used for controlling the charging and discharging state of charge and discharge capacitance C1, the voltage produced at the two ends of charge and discharge capacitance C1 exports control signal by detection signal output end vo ut after schmidt shaping circuit 5 carries out shaping, meanwhile, the voltage that schmidt shaping circuit 5 exports controls the unlatching of the first metal-oxide-semiconductor M1 in recovery voltage initialization circuit 6 and the second metal-oxide-semiconductor M2 simultaneously, so that setting recovery voltage.When the voltage of setting voltage setting end Vin makes V1 lower than Verf, power input VDD is charged to charge and discharge capacitance C1 by the 3rd metal-oxide-semiconductor M3 and the 5th resistance R5, if in official hour, when the voltage rising of voltage sets end Vin makes V1 higher than Verf, charge and discharge capacitance C1 is electric discharge at once, and the time is recalculated; If in official hour, when the voltage rising of voltage sets end Vin could not make V1 higher than Verf, detection signal output end vo ut is in low level and charge and discharge capacitance C1 continues charging until after the voltage of voltage sets end Vin is elevated to recovery voltage, detection signal output end vo ut recovers high level, charge and discharge capacitance C1 discharges, and the time is recalculated; In the process, when detection signal output end vo ut is high level, the first metal-oxide-semiconductor M1 opens, and the second metal-oxide-semiconductor M2 closes, and the first resistance R1 is shorted, and the 4th resistance R4 participates in dividing potential drop; When detection signal output end vo ut is low level, the first metal-oxide-semiconductor M1 closes, and the second metal-oxide-semiconductor M2 opens, and the first resistance R1 participates in dividing potential drop, and the 4th resistance R4 is shorted.
In addition, because the resistance of the first resistance R1 and the 4th resistance R4 is equal, as the voltage Vout=1 of detection signal output end vo ut (when being in high level), branch pressure voltage V1 equals the cut-in voltage needed for reference voltage V erf:
As the voltage Vout=0 of detection signal output end vo ut (when being in low level), branch pressure voltage V1 equals the recovery voltage needed for reference voltage V erf:
And the ratio of cut-in voltage and recovery voltage:
The foregoing is only preferred embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model instructions and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.
Claims (7)
1. an anti-interference low voltage test chip, is characterized in that: it comprises:
For being realized the capacitor charge and discharge circuit that voltage exports by the discharge and recharge of electric capacity, described capacitor charge and discharge circuit is provided with power input;
For the logic combination circuit that control capacitance charge-discharge circuit opens and closes, the output terminal of described logic combination circuit is connected to the input end of capacitor charge and discharge circuit;
For providing the reference voltage generating circuit of reference voltage to logic combination circuit, the output terminal of described reference voltage generating circuit is connected to the input end of logic combination circuit;
For setting the resistor voltage divider circuit of the magnitude of voltage inputed in logic combination circuit, described resistor voltage divider circuit is connected to the input end of logic combination circuit, described resistor voltage divider circuit is provided with voltage sets end;
The schmidt shaping circuit that detection signal exports is realized after voltage for exporting capacitor charge and discharge circuit carries out Shape correction, described schmidt shaping circuit is connected to the output terminal of capacitor charge and discharge circuit, described schmidt shaping circuit is provided with detection signal output terminal;
With
Magnitude of voltage for exporting according to schmidt shaping circuit sets the recovery voltage initialization circuit of the ratio of resistor voltage divider circuit, and described recovery voltage initialization circuit is connected between the output terminal of schmidt shaping circuit and resistor voltage divider circuit.
2. a kind of anti-interference low voltage test chip as claimed in claim 1, it is characterized in that: described capacitor charge and discharge circuit comprises the 3rd metal-oxide-semiconductor, 4th metal-oxide-semiconductor, charge and discharge capacitance and the 5th resistance, grid and the grid of the 4th metal-oxide-semiconductor of described 3rd metal-oxide-semiconductor are connected the output terminal of logic combination circuit simultaneously, the drain electrode of described 3rd metal-oxide-semiconductor and the drain electrode of the 4th metal-oxide-semiconductor are connected to the two ends of the 5th resistance, the source electrode of described 3rd metal-oxide-semiconductor is connected power input with substrate simultaneously, the source electrode of described 4th metal-oxide-semiconductor and substrate ground connection simultaneously, one end ground connection of described charge and discharge capacitance, the other end is connected to the input end of schmidt shaping circuit.
3. a kind of anti-interference low voltage test chip as claimed in claim 1 or 2, it is characterized in that: described recovery voltage initialization circuit comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, the grid of described first metal-oxide-semiconductor is connected the output terminal of schmidt shaping circuit with the grid of the second metal-oxide-semiconductor simultaneously, the source electrode of described first metal-oxide-semiconductor is connected voltage sets end with substrate simultaneously, the source electrode of described second metal-oxide-semiconductor and substrate ground connection simultaneously, the drain electrode of described first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor contact resistance bleeder circuit respectively.
4. a kind of anti-interference low voltage test chip as claimed in claim 3, it is characterized in that: described schmidt shaping circuit comprises the Schmidt's shaping unit and the second phase inverter that are linked in sequence, the input end of described Schmidt's shaping unit is connected to the output terminal of capacitor charge and discharge circuit, the output terminal of described second phase inverter is as detection signal output terminal, and the grid of described first metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor are connected between the input end of the second phase inverter and the output terminal of Schmidt's shaping unit simultaneously.
5. a kind of anti-interference low voltage test chip as claimed in claim 3, is characterized in that: described resistor voltage divider circuit comprises first resistance of sequential series between voltage sets end and earth terminal, the second resistance, the 3rd resistance and the 4th resistance;
The input end of described logic combination circuit is connected between the second resistance and the 3rd resistance, and the drain electrode of described first metal-oxide-semiconductor is connected between the first resistance and the second resistance, and the drain electrode of described second metal-oxide-semiconductor is connected between the 3rd resistance and the 4th resistance.
6. a kind of anti-interference low voltage test chip as claimed in claim 5, is characterized in that: the resistance of described first resistance equals the resistance of the 4th resistance.
7. a kind of anti-interference low voltage test chip as claimed in claim 5, it is characterized in that: described logic combination circuit comprises comparer and the first phase inverter, the output terminal that the positive pole of described comparer is connected between the first resistance and the second resistance, negative pole connects reference voltage generating circuit, output terminal connect the input end of the first phase inverter, and the output terminal of described first phase inverter connects the input end of capacitor charge and discharge circuit.
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| CN201520764730.9U CN205015387U (en) | 2015-09-29 | 2015-09-29 | Anti -interference low -voltage detection chip |
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| CN201520764730.9U CN205015387U (en) | 2015-09-29 | 2015-09-29 | Anti -interference low -voltage detection chip |
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| CN205015387U true CN205015387U (en) | 2016-02-03 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109981083A (en) * | 2019-03-19 | 2019-07-05 | 上海林果实业股份有限公司 | Waveform shaping circuit and electronic equipment |
| CN110320957A (en) * | 2019-08-05 | 2019-10-11 | 北京中科银河芯科技有限公司 | A kind of voltage selecting circuit |
| WO2020142956A1 (en) * | 2019-01-09 | 2020-07-16 | 深圳市大疆创新科技有限公司 | Discharge circuit for distance measuring device, distributed radar system and mobile platform |
| CN112947660A (en) * | 2021-02-20 | 2021-06-11 | 上海韦玏微电子有限公司 | Preprocessing circuit and preprocessing method for power supply voltage |
| CN113484589A (en) * | 2021-06-30 | 2021-10-08 | 杭州加速科技有限公司 | Power-off detection circuit with hysteresis function and control system |
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2015
- 2015-09-29 CN CN201520764730.9U patent/CN205015387U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020142956A1 (en) * | 2019-01-09 | 2020-07-16 | 深圳市大疆创新科技有限公司 | Discharge circuit for distance measuring device, distributed radar system and mobile platform |
| CN111670527A (en) * | 2019-01-09 | 2020-09-15 | 深圳市大疆创新科技有限公司 | Discharging circuit for distance measuring device, distributed radar system and movable platform |
| CN109981083A (en) * | 2019-03-19 | 2019-07-05 | 上海林果实业股份有限公司 | Waveform shaping circuit and electronic equipment |
| CN110320957A (en) * | 2019-08-05 | 2019-10-11 | 北京中科银河芯科技有限公司 | A kind of voltage selecting circuit |
| CN112947660A (en) * | 2021-02-20 | 2021-06-11 | 上海韦玏微电子有限公司 | Preprocessing circuit and preprocessing method for power supply voltage |
| CN112947660B (en) * | 2021-02-20 | 2024-03-19 | 上海韦玏微电子有限公司 | Pretreatment circuit and pretreatment method for power supply voltage |
| CN113484589A (en) * | 2021-06-30 | 2021-10-08 | 杭州加速科技有限公司 | Power-off detection circuit with hysteresis function and control system |
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