CN218771776U - Linear voltage reduction circuit and electronic equipment - Google Patents

Linear voltage reduction circuit and electronic equipment Download PDF

Info

Publication number
CN218771776U
CN218771776U CN202222617934.2U CN202222617934U CN218771776U CN 218771776 U CN218771776 U CN 218771776U CN 202222617934 U CN202222617934 U CN 202222617934U CN 218771776 U CN218771776 U CN 218771776U
Authority
CN
China
Prior art keywords
voltage
resistor
linear
switching device
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202222617934.2U
Other languages
Chinese (zh)
Inventor
彭庆
江锦标
邹伟宏
蒋志勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Muguang Intelligent Lighting Co ltd
Original Assignee
Guangdong Muguang Intelligent Lighting Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Muguang Intelligent Lighting Co ltd filed Critical Guangdong Muguang Intelligent Lighting Co ltd
Priority to CN202222617934.2U priority Critical patent/CN218771776U/en
Application granted granted Critical
Publication of CN218771776U publication Critical patent/CN218771776U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Dc-Dc Converters (AREA)

Abstract

The application relates to the technical field of electronic circuits, and discloses a linear voltage reduction circuit and electronic equipment, and the linear voltage reduction circuit includes: a switching device having an input terminal for connection to an input voltage; the input end of the low dropout linear regulator is respectively connected with the output end of the switching device and the energy storage capacitor, the output end of the low dropout linear regulator is connected with the filter capacitor, and the low dropout linear regulator is used for linear voltage reduction; and the switch driving unit is connected with the control end of the switching device and used for driving the switching device to be switched on or switched off so as to control the voltage of the energy storage capacitor, so that the voltage of the input end of the low-dropout linear voltage regulator is in a preset voltage range. The circuit has the advantages of low cost, high conversion efficiency, no EMI interference and the like, and is suitable for being applied to a low-power voltage reduction circuit with large input-output voltage difference.

Description

Linear voltage reduction circuit and electronic equipment
Technical Field
The present application relates to the field of electronic circuit technology, and in particular, to a linear voltage reduction circuit and an electronic device.
Background
The current power supply voltage reduction technology is mature and has wide application fields, and the main application technologies are the switching power supply voltage reduction technology, such as a Buck voltage converter, and the linear voltage reduction technology, such as the typical LDO U1 (low dropout linear voltage regulator) application. The Buck voltage converter has the advantages of large input-output voltage difference, high conversion efficiency, large output power and the like, but the Buck voltage converter is high in cost and complex in principle, can bring problems of EMI interference and the like, and particularly brings higher cost pressure to circuits with small power and low cost. The LDO U1 voltage reduction circuit has the advantages of simple circuit, low cost and no EMI interference, but the defects are more prominent, namely, the output power is not high, the larger the input and output voltage difference is, the lower the conversion efficiency is, therefore, the LDO U1 voltage reduction circuit is generally applied to circuits with lower input and output voltage difference and cannot be directly applied to small-power circuits with higher input and output voltage difference.
SUMMERY OF THE UTILITY MODEL
In view of the above, embodiments of the present application provide a linear voltage reduction circuit and an electronic device.
In a first aspect, an embodiment of the present application provides a linear voltage reduction circuit, including:
the input end of the switching device is used for connecting an input voltage;
the input end of the low dropout regulator is respectively connected with the output end of the switching device and the energy storage capacitor, the output end of the low dropout regulator is connected with the filter capacitor, and the low dropout regulator is used for linear voltage reduction;
and the switch driving unit is connected with the control end of the switch device and used for driving the switch device to be switched on or switched off so as to control the voltage of the energy storage capacitor, so that the voltage of the input end of the low-dropout linear voltage regulator is in a preset voltage range.
In some embodiments, the switch driving unit includes a first transistor, a first resistor, a second resistor, and a third resistor;
the base electrode of the first triode is respectively connected with one end of each of the first resistor and the second resistor, the base electrode is also used for accessing a switch control signal, the collector electrode of the first triode is respectively connected with the control end of the switch device and one end of the third resistor, and the emitter electrode of the first triode is grounded;
the other end of each of the first resistor and the third resistor is connected to the input end of the switching device, and the other end of the second resistor is grounded.
In some embodiments, the linear voltage reduction circuit further comprises:
the power supply end of the microcontroller is connected with the output end of the low dropout linear regulator, the signal output end of the microcontroller is connected with the switch driving unit, and the microcontroller is used for outputting the switch control signal so as to drive the switching device to be switched on or switched off.
In some embodiments, the linear voltage reduction circuit further comprises:
the microcontroller is also used for collecting the voltage of the input end of the low dropout regulator through an internal integrated or externally connected analog-digital conversion module and detecting the voltage of the input end so as to adjust the frequency and/or duty ratio of the switch control signal.
In some embodiments, the linear voltage reduction circuit further comprises:
the voltage sampling end of the hysteresis comparator is connected with the input end of the low dropout linear regulator, and the voltage reference end of the hysteresis comparator is connected to the input end of the switching device through a voltage dividing resistor;
and the driving amplifier is connected with the output end of the hysteresis comparator, the output end of the driving amplifier is connected with the switch driving unit, and the driving amplifier is used for amplifying the output signal of the hysteresis comparator and then using the amplified output signal as the switch control signal so as to drive the switching device to be switched on or switched off.
In some embodiments, the driver amplifier comprises a second transistor, a fourth resistor, and a fifth resistor;
the base electrode of the second triode is respectively connected with one end of each of the fourth resistor and the fifth resistor, the collector electrode of the second triode is connected with the base electrode of the first triode, and the emitting electrode of the second triode and the other end of the fifth resistor are both grounded; the other end of the four resistors is connected with the output end of the hysteresis comparator.
In some embodiments, the hysteresis comparator comprises a voltage comparator, a sixth resistor, and a seventh resistor;
the non-inverting input end of the voltage comparator is respectively connected with one end of each of the sixth resistor and the seventh resistor, and the inverting input end of the voltage comparator is used for accessing a reference voltage;
the other end of the sixth resistor is connected with the output end of the voltage comparator, and the other end of the seventh resistor is connected with the input end of the low dropout regulator.
In some embodiments, the hysteresis comparator is provided with a first voltage threshold and a second voltage threshold, the first voltage threshold is greater than the second voltage threshold, and the second voltage threshold is not less than the minimum input voltage of the low dropout linear regulator.
In some embodiments, the switching device is an MOS transistor, a gate of the MOS transistor is connected to the switch driving unit, a source of the MOS transistor is used for connecting an input voltage, and a drain of the MOS transistor is connected to the input terminal of the low dropout linear regulator.
In a second aspect, an embodiment of the present application further provides an electronic device, which includes the above linear voltage-reducing circuit.
The embodiment of the application has the following beneficial effects:
the linear voltage reduction circuit is improved based on a low dropout linear regulator (LDO U1), a switching device and an energy storage capacitor are added at the input end of the LDO U1, and the switching device is controlled to be switched on or switched off by utilizing a switching control signal, so that the voltage of the energy storage capacitor is controlled, the voltage at the input end and the voltage at the output end of the LDO U1 meet a low dropout condition, namely the voltage at the input end of the LDO U1 is close to the voltage at the output end, and the conversion efficiency of the whole circuit is improved; in addition, the voltage of the input end of the LDO U1 is controlled by combining the switching device and the energy storage capacitor, and high-efficiency linear voltage reduction can be realized even when higher voltage difference exists between the input voltage of the circuit and the output voltage of the LDO U1.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 shows a schematic structural diagram of a linear voltage reduction circuit according to an embodiment of the present application;
FIG. 2 shows a timing diagram of charging and discharging of an energy storage capacitor based on MCU control;
FIG. 3 shows a first circuit diagram of a linear voltage reduction circuit according to an embodiment of the present application;
FIG. 4 shows a second circuit diagram of a linear buck circuit in accordance with an embodiment of the present application;
FIG. 5 is a schematic diagram of another embodiment of a linear voltage reduction circuit;
FIG. 6 shows a timing diagram of charging and discharging of an energy storage capacitor based on hysteresis comparator control;
fig. 7 shows a third circuit diagram of a linear voltage-reducing circuit according to an embodiment of the present application.
Description of the main element symbols:
10-a linear voltage step-down circuit; q1-switching device; u1-low dropout linear regulator; c1-energy storage capacitor; c2-filter capacitance; 101-a switch drive unit; q2-a first triode; r1-a first resistor; r2-a second resistor; r3-a third resistor; 201-hysteresis comparator; 202-a driver amplifier; q3-a second triode; r4-a fourth resistor; r5-a fifth resistor; u2-voltage comparator; r6-a sixth resistor; r7-seventh resistor.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The linear voltage reduction circuit can be applied to some low-power voltage reduction equipment, particularly to a circuit with higher voltage difference between input voltage and output voltage, and the linear voltage reduction circuit 10 is characterized in that on the basis of a low-voltage difference linear voltage regulator (namely LDO U1), a switch device, an energy storage capacitor and the like are additionally arranged in front of the input end of the LDO U1, and a switch control signal is utilized to control the switch device to be switched on or switched off at a proper moment, so that the purpose of limiting the input voltage of the LDO U1 to improve the conversion efficiency of the LDO U1 can be achieved, the heat of the circuit can be reduced, and the reliability of the circuit can be improved; meanwhile, compared with the BUCK circuit, the cost is reduced, and EMI and the like are not generated. The low dropout regulator described in the present application is mainly used for linearly stepping down the voltage at the input terminal thereof, and the specific structure may be implemented by using an existing integrated chip, or may be obtained by using a circuit formed by separate devices, which is not limited herein.
Fig. 1 is a schematic structural diagram of a linear voltage-reducing circuit 10 according to an embodiment of the present disclosure. Exemplarily, the linear voltage-reducing circuit 10 includes a switching device Q1, an LDO U1, and a switch driving unit 101, wherein an input terminal of the switching device Q1 is used for connecting an input voltage, and output terminals thereof are respectively connected to an input terminal of the LDO U1 (corresponding to pin 3 of U1 in fig. 1) and an energy-storing capacitor C1; the output end (corresponding to pin 2 of U1 in fig. 1) of LDO U1 is connected to filter capacitor C2; the switch driving unit 101 is connected to the control end of the switching device Q1, and the switch driving unit 101 is configured to drive the switching device Q1 to be turned on or off according to the received switch control signal to control the voltage of the energy storage capacitor C1, so that the input end of the LDO U1 is within a preset voltage range, that is, the voltage of the input end of the LDO U1 is as close as possible to the voltage of the output end, that is, the voltage of the input end and the voltage of the output end of the LDO U1 are within a low voltage difference range, thereby improving the conversion efficiency of the whole circuit. It can be understood that the output terminal of LDO U1 is used to connect to a load and provide a required operating voltage for the load.
With reference to fig. 1, the principle of the linear voltage-reducing circuit 10 of the present embodiment is as follows: let Vin + be the input voltage of the whole circuit, and Vout + be the output voltage of the whole circuit, which is also the output voltage of the LDO U1, where Vin + and Vout + have a higher voltage difference, and Vu represents the voltage of the energy storage capacitor C1, which is also the input voltage of the LDO U1. In order to make the circuit work normally, the on or off of the switching device Q1 can be controlled by inputting a switching control signal (such as a PWM signal output by a microcontroller, etc.), so as to control the magnitude of the voltage Vu of the energy storage capacitor C1. Fig. 2 is a timing chart of charging and discharging of the energy storage capacitor C1. When the input voltage Vin + is much higher than the voltage Vu of the energy storage capacitor C1, when the switch control signal is at a high level, the switching device Q1 is turned on, the energy storage capacitor C1 starts to charge, the voltage Vu rises, when the voltage Vumax rises to a preset maximum voltage Vumax, the switch control signal is converted into a low level, at this time, the switching device Q1 is turned off, the energy storage capacitor C1 starts to discharge, the voltage Vu starts to fall, when the voltage Vumin falls to a preset minimum voltage Vumin, the switch control signal is converted into a high level again, and the process is repeated.
Since the conversion efficiency of LDO U1 can be calculated as
Figure BDA0003872236060000071
It can be seen that the conversion efficiency is higher as the voltage Vu is closer to Vout +. Thus, the linear voltage-reducing circuit 10 can realize a high dropout voltage-reducing function with high efficiency. It should be understood that the frequency and duty ratio of the switch control signal should ensure that the maximum voltage Vumax of the energy storage capacitor C1 is much lower than the input voltage Vin +, and the minimum voltage Vumin should meet the minimum operating voltage of the LDO U1 to ensure normal operation.
The linear voltage reduction circuit 10 will be described with reference to some possible specific circuit configurations.
In one embodiment, as shown in fig. 3, the switch driving unit 101 includes a first transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3, specifically, a base of the first transistor Q2 is connected to one end of each of the first resistor R1 and the second resistor R2, and is further used for receiving a switch control signal, a collector of the first transistor Q2 is connected to a control end of the switching device Q1 and one end of the third resistor R3, and an emitter of the first transistor Q2 is grounded; the other ends of the first resistor R1 and the third resistor R3 are connected to the input end of the switching device Q1, and the other end of the second resistor R2 is grounded. It can be understood that the first resistor R1 and the second resistor R2 provide bias for the first transistor Q2 and the switching device Q1, respectively. In addition, the switching device Q1 may be an MOS transistor, such as a PMOS transistor or an NMOS transistor, and may be specifically selected according to actual requirements. The PMOS transistor is mainly used as an example for explanation, specifically, the gate of the MOS transistor is used as the control terminal of the switching device, and is connected to the switch driving unit 101, the source of the MOS transistor is used for connecting the input voltage Vin +, and the drain of the MOS transistor is connected to the input terminal of the LDO. Of course, the switching device Q1 may also be another type of controllable device having a switching characteristic, and is not limited herein.
Alternatively, the switch control signal is a Pulse Width Modulation (PWM) signal, which can be preset and output to the switch driving unit 101 by a microcontroller (also called MCU) on the load side or the power supply side. In an optional scheme, the linear voltage-reducing circuit 10 further includes the MCU, wherein a power supply terminal of the MCU is connected to an output terminal of the low dropout regulator U1, and is configured to obtain a required operating voltage from the output terminal; meanwhile, a signal output end of the MCU is connected to the switch driving unit 101, such as the base of the first transistor Q2. In this embodiment, the MCU may be used to output a PWM signal to drive the switching device Q1 on or off.
In conjunction with the circuit diagram shown in fig. 3, the operation of the linear voltage-reducing circuit 10 is as follows: the circuit is electrified for the first time, the input voltage Vin + is applied, and at the moment, the voltage output does not exist in the output of the circuit, so that the MCU does not work; the circuit makes first triode Q2 switch on after first resistance R1 and second resistance R2 partial pressure, makes MOS pipe Q1's grid voltage be drawn down to ground after first triode Q2 switches on to make MOS pipe Q1 switch on. After the MOS transistor Q1 is turned on, the energy storage capacitor C1 starts to charge, the terminal voltage Vu rises, the LDO U1 starts to output a stable voltage Vout +, and the MCU starts to operate. Therefore, after the MCU works, a preset PWM signal with a frequency F and a duty ratio D can be output, when the PWM signal is at a low level, the first triode Q2 is turned off, and then the gate voltage of the MOS transistor Q1 is pulled up to be equal to the input voltage Vin + by the third resistor R3, so that the MOS transistor Q1 is turned off, and at this time, the LDO U1 is powered (i.e., discharged) by the energy storage capacitor C1, and the voltage Vu starts to drop; when the voltage Vu is reduced to a certain degree, the PWM signal outputs a high level again, so that the first triode Q2 and the MOS transistor Q1 are turned on again, and the energy storage capacitor C1 is charged, and the voltage Vu starts to rise, and when the low level of the next PWM signal comes, a cycle is completed. It can be understood that the PWM signal can maintain the voltage Vu of the energy storage capacitor C1 at a certain height and close to the output voltage Vout +, thereby improving the conversion efficiency of the U1 LDO U1. The voltage Vu of the energy storage capacitor C1 can be obtained properly by setting the frequency and duty ratio of the PWM signal, and can be obtained specifically according to an actual test.
Further, considering that the voltage Vu of the energy storage capacitor C1 is affected by the frequency and duty ratio of PWM during charging, but the discharging is affected by the load, when the load is light (the required power is small), the discharging speed (voltage drop) of the energy storage capacitor C1 is slow, and the charging starts again when the optimal minimum voltage Vumin is not discharged, so that the efficiency of the LDO U1 cannot be maximized. When the load is heavy (the required power is high), the discharging speed of the energy storage capacitor C1 is high, if the PWM signal is not charged in time, the energy storage capacitor C1 is discharged to a minimum working voltage lower than the minimum working voltage of the LDO U1, so that the LDO U1 cannot normally work, and at this time, the output voltage Vout + is abnormal, and the load cannot be normally carried.
Therefore, the method is further optimized, and whether the optimal Vumax and Vuman are achieved or not can be accurately detected by increasing the detection of the voltage of the input end of the LDO U1, so that the frequency and/or the duty ratio of the PWM signal can be automatically adjusted along with the change of the load, and the efficiency maximization of the LDO U1 is realized.
In one embodiment, as shown in fig. 4, when the ADC module is integrated inside the MCU, the voltage at the input end of the LDO U1 may be collected by the internally integrated ADC, and the voltage at the input end is detected to adjust the frequency and/or duty ratio of the PWM signal. Optionally, the ADC module may also be externally connected to the MCU, so that the MCU obtains the voltage at the input end of the LDO U1.
As an alternative, for the above-mentioned linear voltage-reducing circuit 10, besides the MCU generates the PWM signal to control the on/off of the switching device Q1, other structures such as the hysteresis comparator 201 may be used to detect the voltage of the energy-storage capacitor C1 and further control the on/off of the switching device Q1, so that the voltage of the energy-storage capacitor C1 approaches the preset minimum voltage Vumin of the LDO U1, thereby improving the conversion efficiency of the circuit.
Fig. 5 is a schematic diagram illustrating a structure of the linear voltage-reducing circuit 10 implemented based on the hysteresis comparator 201. In the present embodiment, in addition to the components shown in fig. 1, the linear voltage step-down circuit 10 further includes: the voltage sampling end of the hysteresis comparator 201 is connected with the input end of the low dropout regulator U1, and the voltage reference end of the hysteresis comparator 201 is connected with the input end of the switching device Q1 through a voltage dividing resistor; the output end of the hysteresis comparator 201 is connected to the input end of the driving amplifier 202, and the output end of the driving amplifier 202 is connected to the switch driving unit 101. The hysteresis comparator 201 is configured to detect a voltage at an input end of the LDO U1, and output a corresponding flip signal according to the voltage at the input end; the driving amplifier 202 is configured to amplify the flip signal output by the hysteresis comparator 201 to serve as the above-mentioned switch control signal, so as to drive the switching device Q1 to be turned on or off.
In this embodiment, the hysteresis comparator 201 is provided with a first voltage threshold and a second voltage threshold, wherein the first voltage threshold is greater than the second voltage threshold, and the second voltage threshold is not less than the minimum input voltage of the LDO U1. The minimum input voltage of the LDO U1 is the minimum working voltage when the LDO U1 is guaranteed to work normally. When the hysteresis comparator 201 samples that the voltage at the input end of the LDO U1 reaches the first voltage threshold or the second voltage threshold, a corresponding level signal inversion is performed. Fig. 6 is a timing chart illustrating charging and discharging of the energy storage capacitor C1 controlled by the hysteresis comparator 201. Assuming that Vin + is recorded as the input voltage of the circuit, vout + is recorded as the output voltage of the circuit, a large voltage difference exists between Vin + and Vout +, vu represents the voltage of the energy storage capacitor C1, i.e., the voltage at the input end of the LDO U1, vth is a first voltage threshold, vth1 is a second voltage threshold, and it can be seen that, in the rising process, when the voltage Vu is greater than the second voltage threshold Vth1 and less than the first voltage threshold Vth, the output of the hysteresis comparator 201 is at a high level; during the falling process of the voltage Vu, when it is greater than the second voltage threshold Vth1 and less than the first voltage threshold Vth, the output of the hysteresis comparator 201 is at a low level. Meanwhile, when the output of the hysteresis comparator 201 is at a high level, the switching device Q1 is turned off, so that the energy storage capacitor C1 is discharged and the voltage Vu is decreased; when the output of the hysteresis comparator 201 is at a low level, the switching device Q1 is turned on, so that the energy storage capacitor C1 is charged and the voltage Vu is increased.
In one embodiment, as shown in fig. 7, the driving amplifier 202 includes a second transistor Q3, a fourth resistor R4 and a fifth resistor R5, and the hysteresis comparator 201 includes a voltage comparator U2, a sixth resistor R6 and a seventh resistor R7; the base electrode of the second triode Q3 is respectively connected with one end of each of a fourth resistor R4 and a fifth resistor R5, the collector electrode of the second triode Q3 is connected with the base electrode of the first triode Q2, and the emitting electrode of the second triode Q3 and the other end of the fifth resistor R5 are grounded; the other end of the fourth resistor R4 is connected to the output end of the hysteresis comparator 201. The non-inverting input terminal of the voltage comparator U2 is connected to one end of each of the sixth resistor R6 and the seventh resistor R7, and the inverting input terminal of the voltage comparator U2 is used for accessing the reference voltage Vref, and for example, the non-inverting input terminal can be obtained by connecting the resistors R9 and R10 in series, then connecting to the input voltage Vin + and dividing the voltage, or can be accessed directly by other means, which is not limited herein. The other end of the sixth resistor R6 is connected with the output end of the voltage comparator U2, and the other end of the seventh resistor R7 is connected with the input end of the LDO U1. Optionally, a current-limiting resistor R8 and the like may be further disposed between the energy-storage capacitor C1 and the switching device Q1, which is not limited herein.
In conjunction with the circuit diagram shown in fig. 7, the operation of the linear voltage-reducing circuit 10 is as follows: when the circuit is powered on for the first time, the voltage Vu of the energy storage capacitor C1 is 0, the output of the hysteresis comparator 201 is 0 at this time, the second triode Q3 is not conducted, the first resistor R1 makes the base of the first triode Q2 biased, the first triode Q2 is conducted, and the gate of the MOS transistor Q1 is pulled down, so that the MOS transistor Q1 is conducted. After the MOS tube Q1 is conducted, the voltage Vu starts to rise, the energy storage capacitor C1 starts to charge, and when the voltage Vu rises to the minimum input voltage of the LDO U1, the LDO U1 outputs a stable voltage Vout +; as the voltage Vu continues to rise to reach the first voltage threshold Vth of the hysteresis comparator 201, the hysteresis comparator 201 outputs a high level and turns on the second transistor Q3, the base of the first transistor Q2 is pulled down after the second transistor Q3 is turned on, so that the second transistor Q3 is turned off, and the gate of the MOS transistor Q1 is pulled up to the input voltage Vin + after the second transistor Q3 is turned off, so that the MOS transistor Q1 is turned off. When the MOS transistor Q1 is turned off, the output of the LDO U1 is supplied with energy by the energy storage capacitor C1, the energy storage capacitor C1 starts discharging, the voltage Vu starts to fall, and when the voltage falls to the second voltage threshold Vtl for hysteresis comparison, the hysteresis comparator 201 starts to turn over and outputs a low level, so that the second triode Q3 is turned off, the first triode Q2 is turned on with the MOS transistor Q1, the MOS transistor Q1 starts to charge after being turned on, the voltage Vu rises, and the above cycle is repeated.
The linear buck circuit 10 of the embodiment is obtained by improving the LDO U1, that is, a switching device Q1 and an energy storage capacitor C1 are added to an input end of the LDO U1, and a PWM signal is used to control the on/off of the switching device Q1, so as to control the voltage of the energy storage capacitor C1, and the voltage of the input end of the LDO U1 is as close as possible to the voltage of the output end thereof, thereby not only generating no EMI interference, but also greatly improving the conversion efficiency of the whole circuit and reducing the cost; meanwhile, by combining the switching device Q1 and the energy storage capacitor C1, even when a higher voltage difference exists between the input voltage of the whole circuit and the output voltage of the LDO U1, the high-efficiency linear voltage reduction function can be realized. Furthermore, the magnitude of the input turbulent voltage of the LDO U1 can be detected by combining the MCU or the hysteresis comparator 201, etc., and the frequency or duty ratio of the PWM signal is changed, so that the LDO U1 can automatically adjust the output capability along with the change of the load, thereby maximizing the efficiency of the LDO U1, etc.
Based on the method of the foregoing embodiment, the present embodiment provides an electronic device, such as a power converter, a power device, and the like, and may also be a load device directly integrated with a voltage reduction function, such as a lighting device, a charging socket, and the like, which is not limited herein. It is to be understood that the alternatives described above with respect to the linear voltage step-down circuit 10 are equally applicable to this embodiment and will not be described again here.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.

Claims (9)

1. A linear voltage reduction circuit, comprising:
the input end of the switching device is used for connecting an input voltage;
the input end of the low dropout linear regulator is respectively connected with the output end of the switching device and the energy storage capacitor, the output end of the low dropout linear regulator is connected with the filter capacitor, and the low dropout linear regulator is used for linear voltage reduction;
the switch driving unit is connected with the control end of the switching device and used for driving the switching device to be switched on or switched off so as to control the voltage of the energy storage capacitor, so that the voltage of the input end of the low-dropout linear voltage regulator is in a preset voltage range;
the power supply end of the microcontroller is connected with the output end of the low dropout linear regulator, the signal output end of the microcontroller is connected with the switch driving unit, and the microcontroller is used for outputting a switch control signal to the switch driving unit so as to enable the switch driving unit to drive the switching device to be switched on or switched off.
2. The linear buck circuit of claim 1, wherein the switch driving unit includes a first transistor, a first resistor, a second resistor, and a third resistor;
a base electrode of the first triode is respectively connected with one end of the first resistor and one end of the second resistor, the base electrode is used for accessing the switch control signal, a collector electrode of the first triode is respectively connected with a control end of the switch device and one end of the third resistor, and an emitting electrode of the first triode is grounded;
the other end of each of the first resistor and the third resistor is connected to the input end of the switching device, and the other end of the second resistor is grounded.
3. The linear buck circuit according to claim 1, wherein the microcontroller is further configured to collect a voltage at an input terminal of the low dropout regulator through an internal integrated or externally connected analog-to-digital conversion module, and detect a voltage at the input terminal to adjust a frequency and/or a duty cycle of the switching control signal.
4. The linear buck circuit of claim 2, further comprising:
the voltage sampling end of the hysteresis comparator is connected with the input end of the low dropout linear regulator, and the voltage reference end of the hysteresis comparator is connected to the input end of the switching device through a voltage dividing resistor;
and the driving amplifier is connected with the output end of the hysteresis comparator, the output end of the driving amplifier is connected with the switch driving unit, and the driving amplifier is used for amplifying the output signal of the hysteresis comparator and then using the amplified output signal as the switch control signal so as to drive the switching device to be switched on or switched off.
5. The linear buck circuit of claim 4, wherein the driver amplifier includes a second transistor, a fourth resistor, and a fifth resistor;
the base electrode of the second triode is respectively connected with one end of each of the fourth resistor and the fifth resistor, the collector electrode of the second triode is connected with the base electrode of the first triode, and the emitter electrode of the second triode and the other end of the fifth resistor are both grounded; and the other end of the four resistors is connected with the output end of the hysteresis comparator.
6. The linear buck circuit of claim 4, wherein the hysteresis comparator comprises a voltage comparator, a sixth resistor and a seventh resistor;
the non-inverting input end of the voltage comparator is respectively connected with one end of each of the sixth resistor and the seventh resistor, and the inverting input end of the voltage comparator is used for accessing a reference voltage;
the other end of the sixth resistor is connected with the output end of the voltage comparator, and the other end of the seventh resistor is connected with the input end of the low dropout regulator.
7. The linear buck circuit of claim 4, wherein the hysteresis comparator has a first voltage threshold and a second voltage threshold, the first voltage threshold being greater than the second voltage threshold, the second voltage threshold being not less than a minimum input voltage of the low dropout linear regulator.
8. The linear buck circuit according to claim 1, wherein the switching device is a MOS transistor, a gate of the MOS transistor is connected to the switch driving unit, a source of the MOS transistor is used for connecting an input voltage, and a drain of the MOS transistor is connected to the input terminal of the low dropout linear regulator.
9. An electronic device, comprising: the linear buck circuit of any one of claims 1 to 8.
CN202222617934.2U 2022-09-29 2022-09-29 Linear voltage reduction circuit and electronic equipment Active CN218771776U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202222617934.2U CN218771776U (en) 2022-09-29 2022-09-29 Linear voltage reduction circuit and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202222617934.2U CN218771776U (en) 2022-09-29 2022-09-29 Linear voltage reduction circuit and electronic equipment

Publications (1)

Publication Number Publication Date
CN218771776U true CN218771776U (en) 2023-03-28

Family

ID=85695433

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202222617934.2U Active CN218771776U (en) 2022-09-29 2022-09-29 Linear voltage reduction circuit and electronic equipment

Country Status (1)

Country Link
CN (1) CN218771776U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116404891A (en) * 2023-04-24 2023-07-07 成都吉瓦特科技有限公司 Output voltage-stabilizing and current-limiting loop control circuit of linear direct-current stabilized power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116404891A (en) * 2023-04-24 2023-07-07 成都吉瓦特科技有限公司 Output voltage-stabilizing and current-limiting loop control circuit of linear direct-current stabilized power supply

Similar Documents

Publication Publication Date Title
CN101924469B (en) Switching power supply with fast transient response
CN201750340U (en) Switch power supply with quick transient response
CN107656124B (en) Boost load current detection circuit and method without external sampling resistor
CN103956896A (en) Voltage conversion circuit and control method
CN114977736B (en) Current detection circuit and controller for switching conversion circuit
CN218771776U (en) Linear voltage reduction circuit and electronic equipment
CN101764520A (en) DC-DC control circuit with large range of load current
CN204131395U (en) Control circuit for switching converter
CN102832915A (en) Programmable power-on reset system
CN102196621A (en) LED dimming circuit
CN100421067C (en) Switched charge multiplier-divider
CN112290646A (en) Lithium battery charging method and device
CN106160458A (en) Improve the BOOST circuit of transient response
CN204652222U (en) A kind of booster type dc-dc
US8476942B2 (en) Summation circuit in DC-DC converter
CN109470908B (en) Peak current detection method of CS-free sampling resistor
CN104185345A (en) Control device used for LED constant-current driving circuit
CN114614538B (en) Switch type charging circuit
CN108496291B (en) Farad capacitor charging circuit and electronic equipment
CN201364513Y (en) Expandable constant current source device
CN109525013B (en) Charging and voltage reduction conversion integrated chip
CN113241940A (en) Overcurrent protection circuit and switching power supply chip
CN204013219U (en) Control circuit for switching converter
CN102931830A (en) inductance charging time control circuit and method and chip and on-off power source
CN101615844A (en) Circuit with the charge pump that is conditioned

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant