CN210274006U - Clock generating circuit and chip for providing arbitrary frequency and duty ratio - Google Patents
Clock generating circuit and chip for providing arbitrary frequency and duty ratio Download PDFInfo
- Publication number
- CN210274006U CN210274006U CN201921696308.9U CN201921696308U CN210274006U CN 210274006 U CN210274006 U CN 210274006U CN 201921696308 U CN201921696308 U CN 201921696308U CN 210274006 U CN210274006 U CN 210274006U
- Authority
- CN
- China
- Prior art keywords
- type mos
- mos tube
- power supply
- voltage
- feedback signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The utility model provides a clock generating circuit and chip of arbitrary frequency and duty cycle is provided, its method includes: a comparator, a first inverter and a second inverter; a reference voltage source for providing a high level or a low level; a charge and discharge module for controlling duty cycle and frequency; a first input end of the comparator is connected with a reference voltage source, and a second input end of the comparator is connected with the charge-discharge module; the output end of the comparator is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the first inverter outputs a control feedback signal and transmits the control feedback signal to a reference voltage source; the output end of the second phase inverter outputs a charge-discharge feedback signal and transmits the charge-discharge feedback signal to the charge-discharge module. The utility model discloses obtain stable adjustable frequency, adjustable duty ratio's clock signal output, effectively solved the problem that traditional clock circuit design is complicated, the area is big, the consumption is big.
Description
Technical Field
The utility model relates to an integrated circuit designs technical field, indicates especially a clock generation circuit and chip that provide arbitrary frequency and duty cycle.
Background
In the art, circuits in electronic systems require clocks for timing operations, such as digital timing circuits, digital/analog hybrids, and the like. The required clock frequencies in different circuits often differ, and for synchronous operation, these different clocks are required to be provided by the same clock source.
The ever-evolving market for portable electronic products has facilitated the academic community's research into high-performance, low-power, low-voltage electronic systems. The traditional clock signal is generated by an external crystal oscillator, an oscillation signal of the external crystal oscillator is input into a chip, and a required clock signal is generated through a chip internal clock recovery and shaping circuit. The mode has large overall power consumption and complex structure and is not beneficial to the miniaturization of the whole system. In addition, for applications where the clock frequency and duty cycle of the system need to be adjustable, circuit modifications of the conventional crystal oscillator are difficult.
Therefore, the clock generation circuit with the frequency and duty ratio adjustable function and excellent performance has great application prospect.
Disclosure of Invention
The utility model aims at providing a clock generating circuit and chip that provide arbitrary frequency and duty cycle realize obtaining stable adjustable frequency, adjustable duty cycle's clock signal output, have effectively solved the problem that traditional clock circuit design is complicated, the area is big, the consumption is big.
The utility model provides a technical scheme as follows:
a clock generation circuit providing arbitrary frequency and duty cycle, comprising:
a comparator, a first inverter and a second inverter;
a reference voltage source for providing a high level or a low level;
a charge and discharge module for controlling duty cycle and frequency;
a first input end of the comparator is connected with the reference voltage source, and a second input end of the comparator is connected with the charge and discharge module;
the output end of the comparator is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the input end of the second phase inverter;
the output end of the first inverter outputs a control feedback signal and transmits the control feedback signal to the reference voltage source;
and the output end of the second phase inverter outputs a charge-discharge feedback signal and transmits the charge-discharge feedback signal to the charge-discharge module.
Further, the comparator is configured to compare a voltage of the reference voltage source with a voltage of the charge-discharge module;
the comparator is further used for outputting a first level signal to the first inverter when the voltage of the charge-discharge module is greater than the voltage of the reference voltage source; when the voltage of the charge-discharge module is smaller than the voltage of the reference voltage source, outputting a second level signal to the first inverter;
the first inverter is used for outputting a first control feedback signal according to the first level signal and outputting a second control feedback signal according to the second level signal;
the second inverter is used for outputting a discharging feedback signal according to the first control feedback signal and outputting a charging feedback signal according to the second control feedback signal.
Further, the charge and discharge module includes:
the device comprises a duty ratio and frequency control unit, a charge and discharge control unit, an energy storage unit, a first N-type MOS (metal oxide semiconductor) tube and a first P-type MOS tube;
the duty ratio and frequency control unit comprises a plurality of first reference current sources connected in parallel and a plurality of second reference current sources connected in parallel;
the energy storage unit comprises a plurality of energy storage capacitors connected in parallel;
the plurality of first reference current sources are connected to the source electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube is connected to the drain electrode of the first P-type MOS tube, the grid electrodes of the first N-type MOS tube and the first P-type MOS tube are respectively connected to the charge and discharge control unit, and the source electrode of the first P-type MOS tube is connected to the plurality of second reference current sources connected in parallel;
the first end of each energy storage capacitor is connected with the drain electrodes of the first N-type MOS tube and the first P-type MOS tube, and the second end of each energy storage capacitor is grounded.
Further, the reference voltage source includes:
and the power supply unit is used for outputting a high level in an initial period, outputting a low level when the first control feedback signal is received, and outputting a high level when the second control feedback signal is received.
Further, the power supply unit includes:
a power supply unit for outputting the high level and the low level;
a first control switch and a second control switch;
the high-level output end of the power supply electronic unit is connected with the first control switch, and the low-level output end of the power supply electronic unit is connected with the second control switch;
the first control switch is used for switching to a conducting state in an initial period and when the second control feedback signal is received, and switching to a disconnecting state when the first control feedback signal is received;
the second control switch is used for switching to a disconnection state when receiving the second control feedback signal and switching to a conduction state when receiving the first control feedback signal.
Further, the power supply unit includes:
and the external power supply is used for outputting the high level and the low level, a high level output end of the external power supply is connected with the first control switch, and a low level output end of the external power supply is connected with the second control switch.
Further, the power supply unit includes:
an internal power supply for outputting the high level and the low level;
the high level output end of the internal power supply is connected with the first control switch, and the low level output end of the internal power supply is connected with the second control switch;
and the output end of the second inverter outputs a clock signal.
Further, the internal power supply includes: a first internal power supply;
the first internal power supply includes: a power supply and a plurality of resistors;
the power supply is connected with a first end of a first resistor, a second end of the first resistor is connected with a first end of a second resistor, a second end of the second resistor is connected with a first end of a third resistor, the third resistor is connected with a first end of a fourth resistor, and a second end of the fourth resistor is grounded;
a first voltage sampling point between the first resistor and the second resistor outputs a first voltage, and a second voltage sampling point between the third resistor and the fourth resistor outputs a second voltage; the first voltage is at a high level and the second voltage is at a low level.
Further, the internal power supply includes: a second internal power supply;
the second internal power supply includes: the power supply comprises a power supply source, a P-type MOS tube, an N-type MOS tube and a capacitor;
the power supply is connected with a source electrode of a second P-type MOS tube, a drain electrode of the second P-type MOS tube and a source electrode of a second N-type MOS tube are respectively connected with a first end of a first capacitor, the second P-type MOS tube and the second N-type MOS tube share a grid electrode, and the clock signal is accessed to the grid electrode sharing position;
the drain electrode of the second N-type MOS tube is connected with the source electrode of a third P-type MOS tube, the source electrode of the third P-type MOS tube is connected with the first end of a second capacitor, the second end of the second capacitor is grounded, the third P-type MOS tube and the third N-type MOS tube share a grid electrode, the clock signal is accessed to the grid electrode, and the drain electrodes of the third P-type MOS tube and the third N-type MOS tube are respectively connected with the second end of the first capacitor;
the power supply is connected with the source electrode of the fourth P-type MOS tube,
the source electrode of the third N-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube, the drain electrode of the fourth P-type MOS tube and the source electrode of the fourth N-type MOS tube are respectively connected with the first end of the third capacitor, the fourth P-type MOS tube and the fourth N-type MOS tube share a grid electrode, and the clock signal is accessed to the grid electrode sharing position;
a second end of the third capacitor is connected with a source electrode of a fifth P-type MOS tube and a drain electrode of a fifth N-type MOS tube respectively, the source electrode of the fifth N-type MOS tube is grounded, and the fifth N-type MOS tube is connected with the clock signal;
the drain electrode of the fifth P-type MOS tube and the source electrode of the sixth N-type MOS tube are respectively connected with the first end of the fourth capacitor, the fifth P-type MOS tube and the sixth N-type MOS tube share a grid, and the clock signal is accessed to the grid;
a second end of the fourth capacitor is respectively connected with a drain electrode of a sixth P-type MOS tube and a drain electrode of a seventh N-type MOS tube, the sixth P-type MOS tube and the seventh N-type MOS tube share a grid electrode, and a source electrode of the seventh N-type MOS tube is grounded;
the drain electrode of the fourth N-type MOS tube, the drain electrode of the sixth N-type MOS tube and the source electrode of the sixth P-type MOS tube are respectively connected with the first end of a fifth capacitor, and the second end of the fifth capacitor is grounded;
a third voltage sampling point is arranged at a connecting line of the drain electrode of the second N-type MOS tube and the source electrode of the third P-type MOS tube, the third voltage sampling point outputs a third voltage, and the third voltage is a high level;
and a fourth voltage sampling point is arranged at a connecting line of the drain electrode of the fourth N-type MOS tube and the drain electrode of the sixth N-type MOS tube, the fourth voltage sampling point outputs a fourth voltage, and the fourth voltage is a low level.
The utility model also provides a chip, include: the clock generating circuit for providing any frequency and duty ratio is integrated.
Through the utility model provides a pair of clock generating circuit and chip that provide arbitrary frequency and duty cycle can obtain stable adjustable frequency, the clock signal output of adjustable duty cycle, has effectively solved the problem that traditional clock circuit design is complicated, the area is big, the consumption is big.
Drawings
The above features, technical features, advantages and implementations of a clock generation circuit and chip providing arbitrary frequency and duty ratio will be further described in the following preferred embodiments in a clearly understandable manner with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an embodiment of a clock generation circuit for providing an arbitrary frequency and a duty ratio according to the present invention;
fig. 2 is a schematic diagram of another embodiment of a clock generation circuit for providing arbitrary frequency and duty ratio according to the present invention;
fig. 3 is a schematic diagram of another embodiment of a clock generation circuit for providing arbitrary frequency and duty ratio according to the present invention;
fig. 4 is a schematic diagram of another embodiment of a clock generation circuit for providing arbitrary frequency and duty ratio according to the present invention;
fig. 5 is a waveform diagram of a clock generator providing arbitrary frequency and duty cycle according to the present invention;
fig. 6 is a waveform diagram of a clock generator providing arbitrary frequency and duty cycle according to the present invention;
fig. 7 is a waveform diagram of a clock generator providing arbitrary frequency and duty cycle in accordance with the present invention;
fig. 8 is a schematic diagram of a first internal power supply of the present invention providing an arbitrary frequency and duty ratio;
fig. 9 is a schematic diagram of a second internal power supply of the present invention providing an arbitrary frequency and duty ratio;
fig. 10 is a schematic diagram of another embodiment of a clock generation circuit for providing arbitrary frequency and duty cycle according to the present invention;
fig. 11 is a schematic structural diagram of another embodiment of a clock generating circuit for providing an arbitrary frequency and a duty ratio according to the present invention.
Detailed Description
In order to more clearly illustrate embodiments of the present invention or technical solutions in the prior art, specific embodiments of the present invention will be described below with reference to the accompanying drawings. It is obvious that the drawings in the following description are only examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be obtained from these drawings without inventive effort.
For the sake of simplicity, only the parts relevant to the present invention are schematically shown in the drawings, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
An embodiment of the present invention, as shown in fig. 1, is a clock generating circuit for providing arbitrary frequency and duty ratio, including:
a Comparator40, a first inverter1, and a second inverter 2;
a reference voltage source 20 for providing a high level (Verf1 or 2/3VDD) or a low level (Verf2 or 1/3 VDD);
a charge and discharge module 10 for controlling duty ratio and frequency;
a first input terminal (+) of the Comparator40 is connected to the reference voltage source 20, and a second input terminal (-) of the Comparator40 is connected to the charge and discharge module 10;
an output terminal of the Comparator40 is connected to an input terminal of the first inverter1, and an output terminal of the first inverter1 is connected to an input terminal of the second inverter 2;
an output terminal of the first inverter1 outputs a control feedback signal, and transmits the control feedback signal to the reference voltage source 20;
the output end of the second inverter2 outputs a charge/discharge feedback signal, and transmits the charge/discharge feedback signal to the charge/discharge module 10.
Specifically, in this embodiment, the first input terminal and the second input terminal of the comparator may be positive phase input terminals or negative phase input terminals. That is, as shown in fig. 10, when the first input terminal is a non-inverting input terminal and the second input terminal is an inverting input terminal, the non-inverting input terminal (+) of the Comparator40 is connected to the reference voltage source 20, the inverting input terminal (-) of the Comparator40 is connected to the charge/discharge module 10, and the output terminal of the Comparator40 is connected to the input terminal of the first inverter 1. As shown in fig. 11, when the first input terminal is an inverting input terminal and the second input terminal is a non-inverting input terminal, an inverting input terminal (+) of the Comparator40 is connected to the reference voltage source 20, a non-inverting input terminal (+) of the Comparator40 is connected to the charge/discharge module 10, an output terminal of the Comparator40 is connected to an input terminal of the third inverter0, and an output terminal of the third inverter0 is connected to an input terminal of the first inverter 1.
Based on the foregoing embodiment, further comprising:
the Comparator40 for comparing the voltage of the reference voltage source 20 with the voltage of the charge and discharge module 10;
the Comparator40 is further configured to output a first level signal to the first inverter1 when the voltage of the charge/discharge module 10 is greater than the voltage of the reference voltage source 20; when the voltage of the charge and discharge module 10 is less than the voltage of the reference voltage source 20, outputting a second level signal to the first inverter 1;
the first inverter1 is configured to output a first control feedback signal according to the first level signal and output a second control feedback signal according to the second level signal;
the second inverter2 is configured to output a discharge feedback signal according to the first control feedback signal, and output a charge feedback signal according to the second control feedback signal.
Based on the foregoing embodiment, as shown in fig. 2, the charge and discharge module 10 includes:
the device comprises a duty ratio and frequency control unit 11, a charging and discharging control unit 12, an energy storage unit 13, a first N-type MOS (metal oxide semiconductor) transistor MN1 and a first P-type MOS transistor MP 1;
the duty cycle and frequency control unit 11 includes a number of first reference current sources (I11, I12, …, I1n) connected in parallel and a number of second reference current sources (I21, I22, …, I2n) connected in parallel;
the energy storage unit 13 comprises a plurality of energy storage capacitors (C11, C12, … and C1m) connected in parallel;
the plurality of first reference current sources are connected to the source of the first N-type MOS transistor MN1, the drain of the first N-type MOS transistor MN1 is connected to the drain of the first P-type MOS transistor MP1, the gates of the first N-type MOS transistor MN1 and the first P-type MOS transistor MP1 are respectively connected to the charge and discharge control unit 12, and the source of the first P-type MOS transistor MP1 is connected to the plurality of second reference current sources connected in parallel;
the first end of each energy storage capacitor is connected with the drains of the first N-type MOS transistor MN1 and the first P-type MOS transistor MP1, and the second end of each energy storage capacitor is grounded.
Based on the foregoing embodiment, the reference voltage source 20 includes:
and a power supply unit for outputting a high level (Verf1 or 2/3VDD) in an initial period, and outputting a low level (Verf2 or 1/3VDD) when the first control feedback signal is received, and outputting a high level (Verf1 or 2/3VDD) when the second control feedback signal is received.
Based on the foregoing embodiment, the power supply unit includes:
a power supply unit for outputting the high level (Verf1 or 2/3VDD) and the low level (Verf2 or 1/3 VDD);
a first control switch SW1 and a second control switch SW 2;
a high-level (Verf1 or 2/3VDD) output end of the power supply electronic unit is connected with the first control switch SW1, and a low-level (Verf2 or 1/3VDD) output end of the power supply electronic unit is connected with the second control switch SW 2;
the first control switch SW1 is used for switching to a conducting state in an initial period and when the second control feedback signal is received, and switching to a disconnecting state when the first control feedback signal is received;
the second control switch SW2 is configured to switch to an off state when receiving the second control feedback signal and switch to an on state when receiving the first control feedback signal.
Based on the foregoing embodiment, as shown in fig. 3, the power supply unit includes:
and the external power supply 21 is used for outputting the high level (Verf1 or 2/3VDD) and the low level (Verf2 or 1/3VDD), the high level (Verf1 or 2/3VDD) output end of the external power supply 21 is connected with the first control switch SW1, and the low level (Verf2 or 1/3VDD) output end is connected with the second control switch SW 2.
Based on the foregoing embodiment, as shown in fig. 4, the power supply unit includes:
an internal power supply 22 for outputting the high level (Verf1 or 2/3VDD) and the low level (Verf2 or 1/3 VDD);
a high level (Verf1 or 2/3VDD) output terminal of the internal power supply 22 is connected to the first control switch SW1, and a low level (Verf2 or 1/3VDD) output terminal is connected to the second control switch SW 2;
an output terminal of the second inverter2 outputs a clock signal CLK, and transfers the clock signal CLK to the internal power supply 22.
Based on the foregoing embodiment, as shown in fig. 8, the internal power supply 22 includes: a first internal power supply 22;
the first internal power supply 22 includes: a power supply VDD and a plurality of resistors;
the power supply VDD is connected to a first end of a first resistor R11, a second end of the first resistor R11 is connected to a first end of a second resistor R12, a second end of the second resistor R12 is connected to a first end of a third resistor R21, the third resistor R21 is connected to a first end of a fourth resistor R22, and a second end of the fourth resistor R22 is grounded;
a first voltage sampling point between the first resistor R11 and the second resistor R12 outputs a first voltage, and a second voltage sampling point between the third resistor R21 and the fourth resistor R22 outputs a second voltage; the first voltage is at a high level (Verf1 or 2/3VDD), and the second voltage is at a low level (Verf2 or 1/3 VDD).
Based on the foregoing embodiment, as shown in fig. 9, the internal power supply 22 includes: a second internal power supply 22;
the second internal power supply 22 includes: the power supply VDD, the P-type MOS tube, the N-type MOS tube and the capacitor are arranged;
the power supply VDD is connected with a source electrode of a second P-type MOS tube MP2, a drain electrode of the second P-type MOS tube MP2 and a source electrode of a second N-type MOS tube MN2 are respectively connected with a first end of a first capacitor, the second P-type MOS tube MP2 and the second N-type MOS tube MN2 share a grid electrode, and a clock signal is accessed to the common grid electrode;
the drain of the second N-type MOS transistor MN2 is connected to the source of a third P-type MOS transistor MP3, the source of the third P-type MOS transistor MP3 is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the third P-type MOS transistor MP3 and the third N-type MOS transistor MN3 share a gate, and a clock signal is accessed to the common gate, and the drains of the third P-type MOS transistor MP3 and the third N-type MOS transistor MN3 are respectively connected to the second end of the first capacitor;
the power supply VDD is connected to the source of the fourth P-type MOS transistor MP4,
the source of the third N-type MOS transistor MN3 is connected to the drain of a fourth N-type MOS transistor MN4, the drain of the fourth P-type MOS transistor MP4 and the source of the fourth N-type MOS transistor MN4 are respectively connected to the first end of a third capacitor, the fourth P-type MOS transistor MP4 and the fourth N-type MOS transistor MN4 share a gate, and a clock signal is accessed to the common gate;
a second end of the third capacitor is connected with a source electrode of a fifth P-type MOS transistor MP5 and a drain electrode of a fifth N-type MOS transistor MN5, respectively, a source electrode of the fifth N-type MOS transistor MN5 is grounded, and the fifth N-type MOS transistor MN5 is connected to the clock signal CLK;
the drain of the fifth P-type MOS transistor MP5 and the source of the sixth N-type MOS transistor MN6 are respectively connected to the first end of the fourth capacitor, the fifth P-type MOS transistor MP5 and the sixth N-type MOS transistor MN6 share a gate, and a clock signal is accessed to the common gate;
a second end of the fourth capacitor is respectively connected with a drain electrode of a sixth P-type MOS transistor MP6 and a drain electrode of a seventh N-type MOS transistor MN7, the sixth P-type MOS transistor MP6 and the seventh N-type MOS transistor MN7 share a gate, and a source electrode of the seventh N-type MOS transistor MN7 is grounded;
the drain of the fourth N-type MOS transistor MN4, the drain of the sixth N-type MOS transistor MN6, and the source of the sixth P-type MOS transistor MP6 are respectively connected to the first end of a fifth capacitor, and the second end of the fifth capacitor is grounded;
a third voltage sampling point is arranged at a connection line between the drain of the second N-type MOS transistor MN2 and the source of the third P-type MOS transistor MP3, the third voltage sampling point outputs a third voltage, and the third voltage is a high level (Verf1 or 2/3 VDD);
a fourth voltage sampling point is arranged at a connection line between the drain of the fourth N-type MOS transistor MN4 and the drain of the sixth N-type MOS transistor MN6, the fourth voltage sampling point outputs a fourth voltage, and the fourth voltage is a low level (Verf2 or 1/3 VDD).
Specifically, initially, the reference voltage source 20 selects to output a high level (Verf1 or 2/3VDD), the charge/discharge control unit 12 in the charge/discharge module 10 selects a charge mode, the reference current source in the charge/discharge module 10 controls the charge of the energy storage unit 13, and the energy storage unit 13 includes a plurality of energy storage capacitors (C11, C12, …, and C1m) connected in parallel, so as to charge the energy storage capacitors. When the voltage of the charge-discharge module 10 exceeds a high level (Verf1 or 2/3VDD), the Comparator40 is inverted, so that the reference voltage source 20 selects to output a low level (Verf2 or 1/3VDD), the charge-discharge control unit 12 in the charge-discharge module 10 selects a discharge mode, the reference current source controls the discharge of the energy storage unit 13, and the energy storage unit 13 includes a plurality of energy storage capacitors (C11, C12, …, C1m) connected in parallel, so as to discharge the energy storage capacitors.
As shown in fig. 5-7, the reference voltage source 20 is divided into an internal mode and an external mode, and when the internal reference mode is selected, a clock is provided, and the clock is outputted from the Comparator40, and then the first inverter1 and the second inverter2 are inverted. As shown in fig. 4, when the reference voltage source 20 is powered by the internal power source 22, the second inverter2 inverts the first control feedback signal to obtain the discharging clock signal CLK provided to the power supply unit, and when the level of the reference voltage source 20 drops to a low level (Verf2 or 1/3VDD) after discharging, the Comparator40 flips, the clock circuit switches to a high level (Verf1 or 2/3VDD), and the charge/discharge control logic switches to a charge mode. The second inverter2 inverts the second control feedback signal to obtain the charging clock signal CLK provided to the electronic unit, when the level of the charged reference voltage source 20 rises to a high level (Verf1 or 2/3VDD), the Comparator Comparator40 inverts, the clock circuit switches to a low level (Verf2 or 1/3VDD), and the charging and discharging control logic switches to a discharging mode, so that a complete charging and discharging period is formed, the above mode is cycled, and a periodic inversion is formed, so as to achieve a periodic clock output.
According to the period calculation formula CV-IT, since the period and frequency conversion formula are combined with the period calculation formula to obtain the frequency calculation formula f-I/CV, the frequency is determined by the capacitance of the energy storage capacitor, the current intensity of the charging and discharging current, and the output voltage difference of the reference voltage source 20, so the frequency generated by the clock generation circuit can be changed by changing the output voltage difference △ V of the reference voltage source 20 to high level (Verf1 or 2/3VDD) -low level (Verf2 or 1/3VDD), the larger the voltage difference △ V, the smaller the frequency f, the frequency generated by the clock generation circuit can be changed by changing the capacitance of the energy storage capacitor, the larger the capacitance of the energy storage capacitor, the smaller the frequency f, the larger the current intensity of the charging and discharging current, the larger the frequency f, the larger the output voltage difference △ V of the reference voltage source 20, the current intensity of the energy storage capacitor, the current intensity of the charging and discharging current can obtain a relatively accurate value for the clock generation circuit, and the frequency deviation of the clock generation circuit is relatively small with the PVT.
Therefore, the utility model discloses can realize the production of arbitrary frequency through changing voltage difference △ V, energy storage capacitor's electric capacity, three kinds of variables of the current strength of charge-discharge current, whole clock output is accomplished in a charge-discharge, and the electric current of consumption is used for the comparative voltage of clock completely, does not release to ground, so this clock generating circuit's consumption itself is very little.
In the charging and discharging process, when the charging current is smaller than the discharging current, because the charging current is small, the time for charging to reach a high level (Verf1 or 2/3VDD) is lengthened, so that the charging time is longer than the discharging time, and the final output frequency is larger than 50%.
The utility model discloses an adjust reference current source's electric current, can obtain comparatively accurate clock frequency output, regulating circuit charge-discharge current's size because reference voltage source 20's output voltage difference △ V, energy storage capacitor's electric capacity, charge-discharge current's current strength can obtain a more accurate value to this clock generating circuit itself, consequently, the utility model discloses can obtain stable adjustable frequency, the clock signal CLK output of adjustable duty cycle.
The utility model discloses a clock of low-power consumption adjustable frequency, adjustable duty cycle produces the theory of operation of circuit does: when the reference voltage source 20 outputs a high level (Verf1 or 2/3VDD), the P-type MOS transistor is turned on, the N-type MOS transistor is turned off, and the energy storage unit 13 is charged. The magnitude of the charging current of the energy storage unit 13 is controlled by controlling the magnitude of the current of the reference current source. When the voltage of the energy storage unit 13 exceeds the high level (Verf1 or 2/3VDD) output by the reference voltage source 20, the Comparator40 is inverted, and at this time, when the reference voltage source 20 outputs the low level (Verf2 or 1/3VDD), the P-type MOS transistor is turned off, the N-type MOS transistor is turned on, and the energy storage unit 13 is discharged. The magnitude of the discharge current of the energy storage unit 13 is controlled by controlling the magnitude of the current of the reference current source. When the voltage of the energy storage unit 13 is lower than the low level (Verf2 or 1/3VDD) output by the reference voltage source 20, the Comparator40 continues to flip, so that the reference voltage source 20 outputs a high level (Verf1 or 2/3VDD), and the charging process is continued. In this manner, the energy storage unit 13 is controlled to charge (discharge) by controlling the output voltage level of the reference voltage source 20 to be high (low), and the energy storage unit 13 is controlled to charge (discharge) current by controlling the current of the reference current source.
Referring to fig. 5, fig. 5 is a waveform diagram of a simulation with a duty ratio of 50% according to an embodiment of the present invention. It can be seen that the charging time T1 and the discharging time T2 of the energy storage unit 13 are the same, the charging time T1 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the high level (Verf1 or 2/3VDD), the discharging time T2 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the low level (Verf2 or 1/3VDD), the charging and discharging waveforms are changed in a triangular wave, and the frequency of the triangular wave is determined by the current magnitude of the reference current source.
Referring to fig. 6, fig. 6 is a simulated waveform diagram with a duty ratio of 70% according to an embodiment of the present invention. It can be seen that the charging time T1 of the energy storage unit 13 is 3 × the discharging time T2, the charging time T1 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the high level (Verf1 or 2/3VDD), the discharging time T2 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the low level (Verf2 or 1/3VDD), the charging and discharging waveforms change in a triangular wave, and the frequency of the triangular wave is determined by the current magnitude of the reference current source.
Referring to fig. 7, fig. 7 is a waveform diagram of a simulation with a duty ratio of 30% according to an embodiment of the present invention. It can be seen that the charging time T1 of the energy storage unit 13 is 1/3 × discharging time T2, the charging time T1 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the high level (Verf1 or 2/3VDD), the discharging time T2 of the energy storage unit 13 is in a linear relationship with the time when the reference voltage source 20 continuously outputs the low level (Verf2 or 1/3VDD), the charging and discharging waveforms change in a triangular wave, and the frequency of the triangular wave is determined by the current magnitude of the reference current source.
Through the embodiment, the utility model discloses a clock generation circuit can obtain stable high performance, low-power consumption, adjustable frequency, the clock signal CLK output of adjustable duty cycle, has effectively solved the problem that traditional clock circuit design is complicated, the area is big, the consumption is big. By controlling the current of the reference current source, the reference current source has small relevance with the power supply voltage and the temperature, so that more accurate clock frequency output can be obtained. In addition, the electric current size through control reference current source adjusts the magnitude of charging current, the discharge current of energy storage unit 13, realizes clock signal CLK's duty cycle adjustment function, consequently, the utility model discloses the adjustable frequency of production, adjustable duty cycle clock signal CLK output path are extremely simple, have the characteristic of low jitter. The utility model discloses a clock generating circuit adopts two (three) feedback loop designs, and frequency output accomplishes in a charge-discharge cycle, can realize the design of ultra-low power consumption circuit.
An embodiment of the utility model discloses a chip, include: the integration is provided with the clock generating circuit which provides any frequency and duty ratio.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A clock generation circuit providing an arbitrary frequency and duty cycle, comprising:
a comparator, a first inverter and a second inverter;
a reference voltage source for providing a high level or a low level;
a charge and discharge module for controlling duty cycle and frequency;
a first input end of the comparator is connected with the reference voltage source, and a second input end of the comparator is connected with the charge and discharge module;
the output end of the comparator is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the input end of the second phase inverter;
the output end of the first inverter outputs a control feedback signal and transmits the control feedback signal to the reference voltage source;
and the output end of the second phase inverter outputs a charge-discharge feedback signal and transmits the charge-discharge feedback signal to the charge-discharge module.
2. The clock generation circuit of claim 1, wherein:
the comparator is used for comparing the voltage of the reference voltage source with the voltage of the charge-discharge module;
the comparator is further used for outputting a first level signal to the first inverter when the voltage of the charge-discharge module is greater than the voltage of the reference voltage source; when the voltage of the charge-discharge module is smaller than the voltage of the reference voltage source, outputting a second level signal to the first inverter;
the first inverter is used for outputting a first control feedback signal according to the first level signal and outputting a second control feedback signal according to the second level signal;
the second inverter is used for outputting a discharging feedback signal according to the first control feedback signal and outputting a charging feedback signal according to the second control feedback signal.
3. The clock generation circuit of claim 2, wherein the charge-discharge module comprises:
the device comprises a duty ratio and frequency control unit, a charge and discharge control unit, an energy storage unit, a first N-type MOS (metal oxide semiconductor) tube and a first P-type MOS tube;
the duty ratio and frequency control unit comprises a plurality of first reference current sources connected in parallel and a plurality of second reference current sources connected in parallel;
the energy storage unit comprises a plurality of energy storage capacitors connected in parallel;
the plurality of first reference current sources are connected to the source electrode of the first N-type MOS tube, the drain electrode of the first N-type MOS tube is connected to the drain electrode of the first P-type MOS tube, the grid electrodes of the first N-type MOS tube and the first P-type MOS tube are respectively connected to the charge and discharge control unit, and the source electrode of the first P-type MOS tube is connected to the plurality of second reference current sources connected in parallel;
the first end of each energy storage capacitor is connected with the drain electrodes of the first N-type MOS tube and the first P-type MOS tube, and the second end of each energy storage capacitor is grounded.
4. The clock generation circuit of claim 3, wherein the reference voltage source comprises:
and the power supply unit is used for outputting a high level in an initial period, outputting a low level when the first control feedback signal is received, and outputting a high level when the second control feedback signal is received.
5. The clock generation circuit of claim 4, wherein the power supply unit comprises:
a power supply unit for outputting the high level and the low level;
a first control switch and a second control switch;
the high-level output end of the power supply electronic unit is connected with the first control switch, and the low-level output end of the power supply electronic unit is connected with the second control switch;
the first control switch is used for switching to a conducting state in an initial period and when the second control feedback signal is received, and switching to a disconnecting state when the first control feedback signal is received;
the second control switch is used for switching to a disconnection state when receiving the second control feedback signal and switching to a conduction state when receiving the first control feedback signal.
6. The clock generation circuit of claim 5, wherein the power supply unit comprises:
and the external power supply is used for outputting the high level and the low level, a high level output end of the external power supply is connected with the first control switch, and a low level output end of the external power supply is connected with the second control switch.
7. The clock generation circuit of claim 5, wherein the power supply unit comprises:
an internal power supply for outputting the high level and the low level;
the high level output end of the internal power supply is connected with the first control switch, and the low level output end of the internal power supply is connected with the second control switch;
and the output end of the second inverter outputs a clock signal.
8. The clock generation circuit of claim 7, wherein the internal power supply comprises: a first internal power supply;
the first internal power supply includes: a power supply and a plurality of resistors;
the power supply is connected with a first end of a first resistor, a second end of the first resistor is connected with a first end of a second resistor, a second end of the second resistor is connected with a first end of a third resistor, the third resistor is connected with a first end of a fourth resistor, and a second end of the fourth resistor is grounded;
a first voltage sampling point between the first resistor and the second resistor outputs a first voltage, and a second voltage sampling point between the third resistor and the fourth resistor outputs a second voltage; the first voltage is at a high level and the second voltage is at a low level.
9. The clock generation circuit of claim 7, wherein the internal power supply comprises: a second internal power supply;
the second internal power supply includes: the power supply comprises a power supply source, a P-type MOS tube, an N-type MOS tube and a capacitor;
the power supply is connected with a source electrode of a second P-type MOS tube, a drain electrode of the second P-type MOS tube and a source electrode of a second N-type MOS tube are respectively connected with a first end of a first capacitor, the second P-type MOS tube and the second N-type MOS tube share a grid electrode, and the clock signal is accessed to the grid electrode sharing position;
the drain electrode of the second N-type MOS tube is connected with the source electrode of a third P-type MOS tube, the source electrode of the third P-type MOS tube is connected with the first end of a second capacitor, the second end of the second capacitor is grounded, the third P-type MOS tube and the third N-type MOS tube share a grid electrode, the clock signal is accessed to the grid electrode, and the drain electrodes of the third P-type MOS tube and the third N-type MOS tube are respectively connected with the second end of the first capacitor;
the power supply is connected with the source electrode of the fourth P-type MOS tube,
the source electrode of the third N-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube, the drain electrode of the fourth P-type MOS tube and the source electrode of the fourth N-type MOS tube are respectively connected with the first end of the third capacitor, the fourth P-type MOS tube and the fourth N-type MOS tube share a grid electrode, and the clock signal is accessed to the grid electrode sharing position;
a second end of the third capacitor is connected with a source electrode of a fifth P-type MOS tube and a drain electrode of a fifth N-type MOS tube respectively, the source electrode of the fifth N-type MOS tube is grounded, and the fifth N-type MOS tube is connected with the clock signal;
the drain electrode of the fifth P-type MOS tube and the source electrode of the sixth N-type MOS tube are respectively connected with the first end of the fourth capacitor, the fifth P-type MOS tube and the sixth N-type MOS tube share a grid, and the clock signal is accessed to the grid;
a second end of the fourth capacitor is respectively connected with a drain electrode of a sixth P-type MOS tube and a drain electrode of a seventh N-type MOS tube, the sixth P-type MOS tube and the seventh N-type MOS tube share a grid electrode, and a source electrode of the seventh N-type MOS tube is grounded;
the drain electrode of the fourth N-type MOS tube, the drain electrode of the sixth N-type MOS tube and the source electrode of the sixth P-type MOS tube are respectively connected with the first end of a fifth capacitor, and the second end of the fifth capacitor is grounded;
a third voltage sampling point is arranged at a connecting line of the drain electrode of the second N-type MOS tube and the source electrode of the third P-type MOS tube, the third voltage sampling point outputs a third voltage, and the third voltage is a high level;
and a fourth voltage sampling point is arranged at a connecting line of the drain electrode of the fourth N-type MOS tube and the drain electrode of the sixth N-type MOS tube, the fourth voltage sampling point outputs a fourth voltage, and the fourth voltage is a low level.
10. A chip, comprising: integrated with a clock generation circuit providing an arbitrary frequency and duty cycle as claimed in any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921696308.9U CN210274006U (en) | 2019-10-11 | 2019-10-11 | Clock generating circuit and chip for providing arbitrary frequency and duty ratio |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921696308.9U CN210274006U (en) | 2019-10-11 | 2019-10-11 | Clock generating circuit and chip for providing arbitrary frequency and duty ratio |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210274006U true CN210274006U (en) | 2020-04-07 |
Family
ID=70020156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921696308.9U Active CN210274006U (en) | 2019-10-11 | 2019-10-11 | Clock generating circuit and chip for providing arbitrary frequency and duty ratio |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210274006U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346878A (en) * | 2021-06-17 | 2021-09-03 | 南京英锐创电子科技有限公司 | Clock circuit and electronic device |
-
2019
- 2019-10-11 CN CN201921696308.9U patent/CN210274006U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346878A (en) * | 2021-06-17 | 2021-09-03 | 南京英锐创电子科技有限公司 | Clock circuit and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110518896B (en) | Clock generating circuit and chip for providing arbitrary frequency and duty ratio | |
| CN103036537A (en) | Generation method for phase interpolator and multiphase interpolation device and interpolation clock | |
| CN104124921A (en) | Current mode comparator based low voltage low power consumption CMOS (Complementary Metal Oxide Semiconductors) relaxation oscillator and method | |
| CN101356732A (en) | Pulse generator, electronic device using the same, and pulse generating method | |
| CN104184469A (en) | Ring oscillator with low power consumption and low temperature coefficient | |
| CN105144579A (en) | Low power architectures | |
| CN103904875A (en) | Digital soft start circuit in switching power source | |
| Yoon et al. | A continuously-scalable-conversion-ratio step-up/down SC energy-harvesting interface with MPPT enabled by real-time power monitoring with frequency-mapped capacitor DAC | |
| CN103546121A (en) | Rc oscillator | |
| Ozaki et al. | A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters | |
| CN105720946B (en) | Relaxation oscillator | |
| CN106961260A (en) | The clock generation circuit of low-power consumption adjustable frequency, adjustable duty cycle | |
| CN110149045B (en) | High-energy-efficiency switch capacitor power converter | |
| CN210274006U (en) | Clock generating circuit and chip for providing arbitrary frequency and duty ratio | |
| CN108933581A (en) | A kind of pierce circuit | |
| WO2019036177A1 (en) | Low-power low-duty-cycle switched-capacitor voltage divider | |
| CN103312267B (en) | A kind of high precision oscillator and frequency generating method | |
| CN105703712B (en) | High-precision RC oscillator | |
| US10581416B2 (en) | External and dual ramp clock synchronization | |
| CN204633599U (en) | Power charge pump and use the electric power management circuit of this power charge pump | |
| CN103825555B (en) | A kind of oscillating circuit | |
| CN203590176U (en) | Rc oscillator | |
| Pham | A high-efficient power converter for thermoelectric energy harvesting | |
| CN215072364U (en) | Annular oscillation circuit and integrated chip | |
| CN108011590A (en) | A kind of high-precision low-power consumption RC oscillators |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |