CN104460933A - Protection circuit for control over digital power source - Google Patents
Protection circuit for control over digital power source Download PDFInfo
- Publication number
- CN104460933A CN104460933A CN201410796286.9A CN201410796286A CN104460933A CN 104460933 A CN104460933 A CN 104460933A CN 201410796286 A CN201410796286 A CN 201410796286A CN 104460933 A CN104460933 A CN 104460933A
- Authority
- CN
- China
- Prior art keywords
- digital power
- protection circuit
- sheffer stroke
- stroke gate
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
Abstract
The invention discloses a protection circuit for control over a digital power source. The protection circuit is characterized in that a pulse input signal of the digital power source passes through a time delay network with a resistor R1 and a capacitor C1 connected in series and then is connected into the input end of a NAND gate N1-A, and the output end of the NAND gate N1-A and the pulse input signal of the digital power source are included in the input end of a NAND gate N1-B together; an output signal of the NAND gate N1-B passes through a phase inverter N1-D, a triode V1 is controlled to be turned on and off, and then a level trigger N2 is controlled to output a high level or a low level to a diode V2, a diode V3 and a diode V4. Due to the structure, control over the digital power source is protected with low cost, complexity of unequal level deign from a digital circuit to an analog circuit is lowered, and the reliability of the protection circuit is improved.
Description
Technical field
The present invention relates to the control field of digital power, particularly a kind of protection circuit controlled for digital power.
Background technology
Along with the development of Power Electronic Technique, Switching Power Supply is just towards intelligent, digitized future development, and digital power, with its good characteristic and complete monitoring function, is more and more widely used.But digital control chip (as dsp chip TMS320F28335PGFA) operating voltage is all lower at present, be low to moderate 3.3V or even 1.8V, there is digital power so at work, do not occur numerical control program fleet or deadlock phenomenon by electromagnetic interference (EMI) unavoidably, now control circuit can go out uncertain control shape; Have several milliseconds when digit chip program powers in addition to hundreds of milli start-up study, and in electrifying startup, export state of a control existence uncertain.Run at digital power Program fly, crash and power-up state uncertain, often need power supply to increase buffer circuit especially and protection circuit, add circuit complexity and cost so undoubtedly.
The house dog processing mode of current employing is that the software watchdog relying on digit chip to carry carrys out reset routine, be equipped with high speed electrifying startup chip FPGA (or CPLD) simultaneously, solve problem, but software can only settlement procedure reset issues, can not settlement procedure crash before state uncertain, and FPGA (or CPLD) cost high, need to programme in addition.
For the problems referred to above, providing a kind of protection circuit of relative inexpensiveness, is the problem that prior art needs to solve to digital Energy control protection.
Summary of the invention
Technical matters to be solved by this invention is, provides a kind of protection circuit controlled for digital power, realizes the object protected digital Energy control with lower cost.
For achieving the above object, technical scheme of the present invention is, a kind of protection circuit controlled for digital power, it is characterized in that: described protection circuit is the input end that the pulse input signal of digital power accesses Sheffer stroke gate N1-A after the time delay network that resistance R1 connects with electric capacity C1, and the output terminal of Sheffer stroke gate N1-A and the pulse input signal of digital power together count the input end of Sheffer stroke gate N1-B; The output signal of Sheffer stroke gate N1-B exports high level or low level to diode V2, V3, V4 through phase inverter N1-D by the break-make and then control level trigger N2 controlling triode V1.
The input end of the pulse input signal Sheffer stroke gate N1-B of described digital power is provided with resistance R2.
Described triode V1 is in parallel with electric capacity C2 accesses power supply.
A kind of protection circuit controlled for digital power; owing to adopting above-mentioned structure; the present invention protects digital Energy control with lower cost, reduces digital circuit does not wait design complicacy to mimic channel level, improves the reliability of protection circuit.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation;
Fig. 1 is the circuit diagram of a kind of protection circuit for digital power control of the present invention;
Fig. 2 is a kind of sequential chart normally worked for the protection circuit of digital power control of the present invention.
Embodiment
The invention provides a kind of house dog formula protection circuit adopting low cost, it is simple and reliable, and input signal must be certain frequency pulse signal; otherwise export one and be decided to be low level; for program crashes with electrifying startup, the not true sex chromosome mosaicism of state of a control, provides a kind of well protected mode.
The present invention forms pulse recognition shaping circuit primarily of Sheffer stroke gate, level trigger forms pulse signal and forms to level signal translation circuit.It is characterized in that input must be certain frequency pulse signal (being exactly the feeding-dog signal of usual indication), output side is high level, otherwise, no matter input is high level or low level, Zong exporting is low level.Circuit of the present invention is simple and practical; because Sheffer stroke gate in circuit and level trigger can use 5V Power supply; also can be powered by 5V and 12V respectively; number is facilitated to solve digital circuit to the unequal problem of mimic channel signal high level; be easy to access in digital control protection circuit; reduce digital circuit does not wait design complicacy to mimic channel level, improve the reliability of protection circuit.
The present invention is the input end that the pulse input signal of digital power accesses Sheffer stroke gate N1-A after the time delay network that resistance R1 connects with electric capacity C1, and the output terminal of Sheffer stroke gate N1-A and the pulse input signal of digital power together count the input end of Sheffer stroke gate N1-B; The output signal of Sheffer stroke gate N1-B exports high level or low level to diode V2, V3, V4 through phase inverter N1-D by the break-make and then control level trigger N2 controlling triode V1.The input end of the pulse input signal Sheffer stroke gate N1-B of digital power is provided with resistance R2.Triode V1 is in parallel with electric capacity C2, and control capacitance C2 discharges.
Specifically as shown in Figure 1-2, time normal, pulse signal P1 adds output terminal, pulse signal is loaded on input 1 and 2 pin of Sheffer stroke gate N1-A after resistance R1 and the time delay of electric capacity C1 time delay network, output 3 pin of Sheffer stroke gate N1-A obtains relative P1 there is the pulse signal P2 of front and back along time delay, P2 reloads on the input pin 4 of Sheffer stroke gate N1-B, P1 is loaded on the input pin 5 of Sheffer stroke gate N1-B through resistance R2 simultaneously, a pulse signal P3 is obtained like this on Sheffer stroke gate N1-B output pin 6, P3 is by controlling the break-make of triode V1 by resistance R4 after the anti-phase shaping of phase inverter N1-D, to carry out discharging to electric capacity C2, level on trigging control pin 2 and 6 pin of level trigger N2 is made not reach triggering inverse values, and then the output pin 3 of level trigger N2 keeps high level, diode V2, V3, V4 blocks this high electricity, normally work with the not protected circuit of shadow.During fault, input pulse signal becomes high level or low level signal, input pin 4 and 5 pin being then carried in Sheffer stroke gate N1-B is inversion signal, and then obtain being high level signal at the output pin 6 of Sheffer stroke gate N1-B, anti-phase through phase inverter N1-D, triode V1 is made to be in off-state, resistance R5 charges to level on trigging control pin 2 and 6 pin of level trigger N2 to electric capacity C2 and reaches triggering inverse values, and then make the output pin 3 of level trigger N2 keep low level, by diode V2, V3, protected circuit level drags down by V4, thus reach protection object.
Above by reference to the accompanying drawings to invention has been exemplary description; obvious specific implementation of the present invention is not subject to the restrictions described above; as long as have employed the various improvement that technical solution of the present invention is carried out, or directly apply to other occasion, all within protection scope of the present invention without improving.
Claims (3)
1. the protection circuit controlled for digital power, it is characterized in that: described protection circuit is the input end that the pulse input signal of digital power accesses Sheffer stroke gate N1-A after the time delay network that resistance R1 connects with electric capacity C1, and the output terminal of Sheffer stroke gate N1-A and the pulse input signal of digital power together count the input end of Sheffer stroke gate N1-B; The output signal of Sheffer stroke gate N1-B exports high level or low level to two adapter V2, V3, V4 through phase inverter N1-D by the break-make and then control level trigger N2 controlling triode V1.
2. a kind of protection circuit controlled for digital power according to claim 1, is characterized in that: the input end of the pulse input signal Sheffer stroke gate N1-B of described digital power is provided with resistance R2.
3. a kind of protection circuit controlled for digital power according to claim 1, is characterized in that: described triode V1 is in parallel with electric capacity C2 accesses power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410796286.9A CN104460933B (en) | 2014-12-19 | 2014-12-19 | A kind of protection circuit controlled for digital power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410796286.9A CN104460933B (en) | 2014-12-19 | 2014-12-19 | A kind of protection circuit controlled for digital power |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104460933A true CN104460933A (en) | 2015-03-25 |
| CN104460933B CN104460933B (en) | 2017-09-12 |
Family
ID=52907140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410796286.9A Active CN104460933B (en) | 2014-12-19 | 2014-12-19 | A kind of protection circuit controlled for digital power |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104460933B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020089801A1 (en) * | 2001-01-09 | 2002-07-11 | Exar Corporation | Short circuit power limiter |
| CN202857068U (en) * | 2012-09-28 | 2013-04-03 | 深圳市明微电子股份有限公司 | LED control circuit and LED lighting device |
| CN103904875A (en) * | 2014-03-24 | 2014-07-02 | 合肥工业大学 | Digital soft start circuit in switching power source |
-
2014
- 2014-12-19 CN CN201410796286.9A patent/CN104460933B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020089801A1 (en) * | 2001-01-09 | 2002-07-11 | Exar Corporation | Short circuit power limiter |
| CN202857068U (en) * | 2012-09-28 | 2013-04-03 | 深圳市明微电子股份有限公司 | LED control circuit and LED lighting device |
| CN103904875A (en) * | 2014-03-24 | 2014-07-02 | 合肥工业大学 | Digital soft start circuit in switching power source |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104460933B (en) | 2017-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101968756B (en) | Satellite-borne computer autonomously computer switching system based on field programmable gata array (FPGA) | |
| CN109194317B (en) | Reset circuit and wearable equipment | |
| CN104201652A (en) | Power protection control method | |
| CN106532629B (en) | A kind of current foldback circuit with self-recovering function | |
| CN101106264A (en) | Waterproof automatic protection device of electronic device | |
| US10355590B2 (en) | Boost converter with pre-charge current | |
| CN105718012B (en) | Method and circuit for automatically switching Vbus voltage in master-slave mode of OTG (on-the-go) equipment | |
| CN207732497U (en) | A kind of robot control system power down preservation circuit | |
| CN204463019U (en) | A kind of power-supplying circuit | |
| CN202649409U (en) | Total dose irradiation test device for 1553B bus communication device | |
| US20140095916A1 (en) | Power supply circuit for pci-e and motherboard having same | |
| CN104850182A (en) | Circuit structure applied to embedded system and power-fail protection method | |
| CN203909782U (en) | Watchdog circuit control module for state of self-adaption processor | |
| CN204256036U (en) | The power-off signal that power supply interrupts produces circuit | |
| CN203537356U (en) | Power on reset circuit | |
| CN203054660U (en) | Rapid power-cut controlling circuit applied to power supply managing circuit | |
| CN104460933A (en) | Protection circuit for control over digital power source | |
| CN204928095U (en) | Protection circuit of intelligence power module | |
| CN205015670U (en) | Dual power supply and outage time schedule control device | |
| CN109842401B (en) | Latch-up resistant device and CMOS chip | |
| CN110581530A (en) | Power bus protection circuit based on intelligent fuse | |
| CN107037866B (en) | Terminal reset circuit and terminal | |
| CN204650218U (en) | A kind of single-chip microcomputer Self-disconnecting restarts circuit | |
| CN204119195U (en) | A kind of anti-interference reset circuit | |
| CN204116848U (en) | A kind of many power control circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |