CN204463019U - A kind of power-supplying circuit - Google Patents
A kind of power-supplying circuit Download PDFInfo
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- CN204463019U CN204463019U CN201420873043.6U CN201420873043U CN204463019U CN 204463019 U CN204463019 U CN 204463019U CN 201420873043 U CN201420873043 U CN 201420873043U CN 204463019 U CN204463019 U CN 204463019U
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Abstract
The utility model relates to electronic circuit field, particularly relate to a kind of power-supplying circuit, comprise: a state latch unit, one switch element and a power supply unit, the input end of state latch unit is connected with the output terminal of CPU (central processing unit), the output terminal of state latch unit is connected with the input end of switch element, and the output terminal of switch element is connected with power supply unit; Power supply unit is connected with state latch unit and switch element respectively, for state latch unit and switch element are powered; CPU (central processing unit) is outputed signal is sent to state latch unit, and state latch cell response outputs signal, and the enable signal simultaneously exported latches, and whether the enable signal judgement that switch element receives according to it is that power supply unit is powered.Whole power-supplying circuit only only used simple and reliable logical circuit, with the break-make of simple structure by gauge tap unit, achieves when after CPU (central processing unit) power-off, the function still can powered for follow-up power supply unit.
Description
Technical field
The utility model relates to electronic circuit field, can be embodied as the control circuit that network chip is powered after particularly relating to a kind of system cut-off.
Background technology
Universal along with computer and network, people more and more be unable to do without cyber-net, although notebook computer can conveniently be carried with and use, the development of Internet more makes people all have ready conditions everywhere and obtains required resource by network, but people are as meeting, due to resource storage and call problem, in order to improve efficiency of doing things, people often not only think to use computing machine at one's side at any time, also think to use at any time not computing machine at one's side, as: family or the computing machine in office, Wake-up on LAN and the remote control of computer progressively receive concern.
The electronic product with network function conventional on market, in order to realize the object of remote control, need, after the CPU (Central Processing Unit, CPU (central processing unit)) of electronic product closes, by operable network product waken up and manipulated.In order to realize this purpose, just need product can determine whether be that network portion chip is powered according to the steering order before CPU power-off when CPU does not power on.
In existing product, after CPU power-off, be all generally use mcu programming to control whether to be that network portion is powered, but its cost is higher, and needs to be coordinated with it by the hardware configuration of complexity.
Utility model content
For the problems referred to above, the utility model provides a kind of power-supplying circuit, and it have employed simple logical circuit and controls power supply to replace traditional single-chip microcomputer, and its structure is simple, and significantly reduces cost.
The utility model provides a kind of power-supplying circuit, and main contents comprise:
A kind of power-supplying circuit, be connected with CPU (central processing unit) and power supply unit respectively, comprise: a state latch unit, one switch element and a power supply unit, the input end of described state latch unit is connected with the output terminal of described CPU (central processing unit), the output terminal of described state latch unit is connected with the input end of described switch element, and the output terminal of described switch element is connected with described power supply unit; Described power supply unit is connected with described state latch unit and described switch element respectively, for described state latch unit and described switch element are powered;
Described CPU (central processing unit) is outputed signal is sent to described state latch unit, output signal described in described state latch cell response, the enable signal simultaneously exported latches, and whether the described enable signal judgement that described switch element receives according to it is that described power supply unit is powered.
In the present embodiment, the output state of power-supplying circuit being controlled the state at the current needs of user by state latch unit, namely when needs wake power supply unit work up, then export high level by the cooperation of state latch unit and switch element, is its power supply; When not needing to power for power supply unit, then by state latch unit cut-off switch unit, in the utility model, the project organization of whole power-supplying circuit is simple, is easy in actual applications realize.
Preferably, described state latch unit comprises: a trigger, first resistance, and first electric capacity, and the output signal of described CPU (central processing unit) comprises control signal and input signal, wherein, the signal input part of described trigger is connected with described CPU (central processing unit) respectively with control signal end, receives the described input signal of described CPU (central processing unit) transmission and described control signal; Signal output part is connected with the first end of described first resistance, and power end is connected with described power supply unit, earth terminal ground connection; Second end of described first resistance is connected with described power supply unit, and the first end ground connection of described first electric capacity, the second end is connected with described power supply unit.
In the present embodiment, CPU (central processing unit) is controlled state latch unit by control signal and input signal, by control signal, state latch unit is triggered, enable operation is carried out to it, namely only have when control signal meets certain condition, state latch unit just responds the input signal of input.Two kinds of signals with the use of, realize the switching of state according to the demand of user, increase the dirigibility of power-supplying circuit.
Preferably, described trigger is d type flip flop, when the control signal of the end of control signal described in d type flip flop input rises, described d type flip flop is triggered, its signal output part exports the enable signal identical with signal input part level, described enable signal is latched simultaneously and keep export, until described control signal again there is rising signals, then described in described d type flip flop Resurvey, the state of input signal makes response.
As illustrated in figs. 2-7, the signal input part in the corresponding the utility model of the difference of D, CP and Q shown in figure, control signal end and signal output part.When only having control signal to be in rising edge as can be known from Fig. 2, output signal just the state of Gather and input signal can make corresponding response, until output just can export by Gather and input again during the arrival of control signal rising edge next time.Such CPU (central processing unit) before closing can by exporting the input signal (elder generation) and control signal (afterwards) two signals that there are successively sequential, d type flip flop will keep required output, CPU (central processing unit) is closed again afterwards, and such d type flip flop just can keep output signal for required level.Like this, namely achieve and in without control chip work, the duty of electronic product is latched, ensure the normal operation of product during system closedown.
Preferably, described switch element comprises: the first transistor and transistor seconds, and wherein, the grid of described the first transistor is connected with the output terminal of described state latch unit, source ground, and drain electrode is connected with the grid of described transistor seconds; The source electrode of described transistor seconds is connected with described power supply unit, and drain electrode is connected with described power supply unit.
Preferably, described the first transistor is a nmos pass transistor, and described transistor seconds is a PMOS transistor
Preferably, described switch element also comprises a RC delay circuit, comprising: the first divider resistance, the second divider resistance, and the second electric capacity; Wherein, described first divider resistance is connected with described second Capacitance parallel connection, its first end be connected in parallel is connected with the source electrode of described power supply unit and described transistor seconds respectively, and its second end connected is connected with the first end of described second divider resistance and the grid of described transistor seconds respectively; Second end of described second divider resistance is connected with the drain electrode of described the first transistor.
Preferably, described switch element comprises: transistor seconds, third transistor, and second resistance, wherein, the first end of described second resistance is connected with described power supply unit, and the second end is connected with the source electrode of described third transistor, the grid of described third transistor is connected with the output terminal of described state latch unit, and drain electrode is connected with the grid of described transistor seconds; The source electrode of described transistor seconds is connected with described power supply unit, and drain electrode is connected with described power supply unit.
Preferably, described transistor seconds and described third transistor are PMOS transistor.
Preferably, described switch element also comprises a RC delay circuit, comprising: the first divider resistance, the second divider resistance, and the second electric capacity; Wherein, described first divider resistance is connected with described second Capacitance parallel connection, its first end be connected in parallel is connected with the source electrode of described power supply unit and described transistor seconds respectively, and its second end connected is connected with the first end of described second divider resistance and the grid of described transistor seconds respectively; Second end ground connection of described second divider resistance.
Preferably, in described switch element, also comprise the 3rd electric capacity, the 4th electric capacity, and the 5th electric capacity, wherein,
The first end of described 3rd electric capacity is connected with described power supply unit, the second end ground connection.
Described 4th electric capacity is connected with described 5th Capacitance parallel connection, and the first end of its parallel connection is connected with the drain electrode of described transistor seconds, the second end ground connection.
In sum, the power-supplying circuit that the utility model provides at least can bring following a kind of beneficial effect:
1. in the utility model, by cooperatively interacting of the trigger in state latch unit and the transistor in switch element, have effectively achieved switching means conductive and closedown, namely when needs for follow-up power supply unit is powered, then gauge tap cell conduction, do not need for follow-up power supply unit power time, gauge tap unit close.The design of whole circuit only only used simply but the logical circuit of high-reliability, the function of powering for follow-up power supply unit after realizing CPU (central processing unit) power-off;
2. in the utility model, instead of conventional single-chip microcomputer with simple logical circuit, not only reduce hardware cost, more can reduce the workload of software engineer, reduce product error probability;
3. in the utility model, the power-supplying circuit of design is widely used, and it can be transplanted to major part and have in the electronic product of WOL (Wake On LAN) and use, highly versatile; And without the need to designing separately for different product and testing, greatly reduce the time cost of design and test.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail:
Fig. 1 is the structured flowchart schematic diagram of power-supplying circuit in the utility model;
Fig. 2 is state latch element circuit schematic diagram in the utility model;
Fig. 3 is the circuit diagram of a kind of embodiment in the utility model breaker in middle unit;
Fig. 4 is the circuit diagram of a kind of embodiment of power-supplying circuit in the utility model;
Fig. 5 is the power-supplying circuit figure adding RC delay circuit in the utility model;
Fig. 6 is the circuit diagram of the complete embodiment of power-supplying circuit in the utility model;
Fig. 7 is the another kind of embodiment circuit diagram of power-supplying circuit in the utility model.
Embodiment
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, below in conjunction with drawings and Examples, the utility model is specifically described.Accompanying drawing in the following describes is only embodiments more of the present utility model.For those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
As a specific embodiment, as shown in Figure 1, the power-supplying circuit that the utility model provides is connected with CPU (central processing unit) and power supply unit respectively, and power-supplying circuit mainly comprises: a state latch unit, one switch element and a power supply unit, the input end of state latch unit is connected with the output terminal of CPU (central processing unit), and the output terminal of state latch unit is connected with the input end of switch element, and the output terminal of switch element is connected with power supply unit; Power supply unit is connected with state latch unit and switch element respectively, for state latch unit and switch element are powered.In actual applications, output signal is sent to state latch unit by CPU (central processing unit), the output signal of the above-mentioned CPU (central processing unit) of state latch cell response, the signal simultaneously exported latches, and whether the enable signal judgement that switch element receives according to it is that power supply unit is powered.
Switch element generally comprises two kinds of forms, and the first uses the enable pin of the direct control voltage conversion chip of output signal of trigger, if enable signal is not enable, then power supply chip entirety does not work and drops to minimum by the power consumption of integral product simultaneously; Another situation is that portion voltage conversion chip needs all to work under all situations, and such as the real-time clock of product is powered, the output of trigger will remove control switch element in this case, and switch element is opened, for power supply unit is powered; Switch element is closed then only for real-time clock is powered.In the utility model, above-mentioned power supply unit provides for the voltage conversion chip of a 3.3V, and it has electricity under any state, as illustrated in figs. 2-7, in figure, V_S_3V3 is power supply unit, and its each device be not only in switch element is powered, simultaneously for state latch unit is powered; Power supply unit is the network chip needing power supply, namely as the PHY_3V3 in Fig. 3-7; CPU (central processing unit) is the CPU (Central Processing Unit) in computing machine.Especially, the utility model is not construed as limiting the voltage conversion chip that power supply unit comprises, as long as it can be powered for the power-supplying circuit in the utility model, is all included in content of the present utility model.
Further, the output signal of CPU (central processing unit) specifically comprises control signal and input signal, and control signal and input signal are sent to state latch unit.In order to enable state latch unit be latched by its output state, in the utility model, employing control signal and its output state is effectively controlled.
As a specific embodiment, as shown in Figure 2, state latch unit comprises: a trigger, first resistance R1, and the first electric capacity C1, and the output signal of CPU (central processing unit) comprises control signal and input signal, wherein, the signal input part of trigger is connected with CPU (central processing unit) respectively with control signal end, receives input signal and the control signal of CPU (central processing unit) transmission; Signal output part is connected with the first end of the first resistance R1, and power end is connected with power supply unit, earth terminal ground connection; Second end of the first resistance R1 is connected with power supply unit, and the first end ground connection of the first electric capacity C1, the second end is connected with power supply unit.Particularly, the control signal exported when CPU (central processing unit) reaches the trigger condition of trigger, then trigger is made according to the input signal received and is exported response accordingly, carry out state latch according to by current enable output signal, until the next one meets the arrival of the trigger condition of trigger simultaneously.In specific implementation process, in the utility model, the resistance of the first resistance R1 is 1K, and the capability value at the first electric capacity C1 two ends is 0.1U.
Further, in the utility model, trigger U1 is a d type flip flop, as shown in Figure 2 and Table 1, wherein, table 1 is the truth table of d type flip flop, particularly, when the control signal of control signal end input in d type flip flop rises, d type flip flop is triggered, its signal output part exports the enable signal identical with signal input part level, enable signal is latched simultaneously, until again there is rising signals in control signal, then the state of d type flip flop Resurvey input signal makes response, namely, in the utility model, conducting and the closedown of follow-up switch element is controlled by the output state controlling d type flip flop.In specific implementation process, the model of d type flip flop of the present utility model is 74AHC1G79, and respective signal input end (in d type flip flop D port) and the control signal end (in d type flip flop CP port) respectively of PHY_POWER_ENH and the D_control signal shown in figure, GND is earth terminal, and VCC is power end.Especially, the concrete form of the utility model to trigger is not construed as limiting, as passed through to use JK flip-flop, rest-set flip-flop, T trigger etc. combinationally use or by other forms of with door, not gate, or mutually combinationally using between Sheffer stroke gate, as long as it can realize the purpose of this utility model, be all included in the utility model.
The truth table of table 1:D trigger
Particularly, in the utility model, switch element comprises: the first transistor Q1 and transistor seconds Q2, and wherein, the grid of the first transistor Q1 is connected with the output terminal of state latch unit, source ground, and drain electrode is connected with the grid of transistor seconds Q2; The source electrode of transistor seconds Q2 is connected with power supply unit, and drain electrode is connected with power supply unit.Further, as shown in Figure 3, the first transistor Q1 is nmos pass transistor; Transistor seconds Q2 is PMOS transistor, and particularly, the model of nmos pass transistor is 2N7002, the model of PMOS is P5103EMG, and in the utility model, is not construed as limiting the model of transistor, as long as it can realize the purpose of this utility model, be all included in content of the present utility model.
As a complete embodiment, the trigger U1 in state latch unit is a d type flip flop, and the first transistor Q1 in switch element is a nmos pass transistor, and transistor seconds Q2 is a PMOS transistor, as shown in Figure 4, makes following description to its workflow:
CPU (central processing unit) successively exported input signal before power down and control signal (first exports input signal and keeps level, export control signal subsequently) to state latch unit, and the rising edge of control signal inputs d type flip flop when input signal is high level, after then d type flip flop is triggered, export high level (enable signal), and keep high level output always.
The grid of the first transistor Q1 (NMOS tube) now in switch element is high level input, and the pressure reduction between grid and source electrode is greater than the forward voltage of the first transistor Q1, thus the first transistor Q1 conducting, its low level output that drains; Namely the grid low level of the transistor seconds Q2 be connected of draining with the first transistor Q1 inputs, pressure reduction now between the grid of transistor seconds Q2 and source electrode reaches the turn-on condition of transistor seconds Q2, and then transistor seconds Q2 conducting, be follow-up power supply unit (network chip) power supply.
Similar, when the rising edge of control signal inputs d type flip flop when pulse is low level, then after d type flip flop is triggered, output low level, and keep low level output always; The grid of the first transistor Q1 (NMOS tube) now in switch element is low level input, thus the first transistor Q1 not conducting, its drain electrode is high level; Namely the grid high level of the transistor seconds Q2 be connected of draining with the first transistor Q1 inputs, thus now transistor seconds Q2 not conducting, and drain electrode does not almost export, and namely be that follow-up power supply unit (network chip) is powered.
Further, switch element also comprises a RC delay circuit, as shown in Figure 5, comprising: the first divider resistance R3, the second divider resistance R4, and the second electric capacity C2; Wherein, first divider resistance R3 and the second electric capacity C2 is connected in parallel, its first end be connected in parallel is connected with the source electrode of power supply unit and transistor seconds Q2 respectively, and its second end connected is connected with the first end of the second divider resistance R4 and the grid of transistor seconds Q2 respectively; Second end of the second divider resistance R4 is connected with the drain electrode of the first transistor Q1.
In actual applications, power supply unit can be equivalent to resistance and Capacitance parallel connection, now, if the transistor seconds Q2 opening speed in switch element is too fast, electric capacity of equal value then in power supply unit can charging cause a larger peak current to occur between the drain electrode and source electrode of Q2 rapidly, even may burn out Q2, if electric current is larger, even burn out external transformer and power input interface.Therefore, in the utility model, before transistor seconds Q2, devise a RC delay circuit, reduced the conducting speed of transistor seconds Q2 by the resistance controlling the first divider resistance R3 and the second divider resistance R4, and then reduce the peak value of peak current.In actual applications, concrete restriction is not done to the selection of the first divider resistance R3 and the second divider resistance R4 resistance, as long as choosing of its resistance can ensure the complete conducting of transistor seconds Q2, as R3>10*R4.Particularly, in the utility model, enough slow for ensureing that transistor seconds Q2 opens, the resistance of the first divider resistance R3 is 1.0M, and the resistance of the second divider resistance R4 is 20K; The capacity of the second electric capacity C2 is 0.22U.When reality uses, in switch element, after electric signal exports from the first transistor Q1, before input transistor seconds Q2, grid electric signal first through above-mentioned RC delay circuit, to reach the effect of protection transistor seconds Q2 and whole power-supplying circuit.
Further, as shown in Figure 6, the 3rd electric capacity C3 in switch element, is also comprised, the 4th electric capacity C4, and the 5th electric capacity C5, wherein, the first end of the 3rd electric capacity C3 is connected with power supply unit, the second end ground connection, particularly, it is a filter capacitor, and the capacity at its two ends is 0.1U.4th electric capacity C4 and the 5th electric capacity C5 is connected in parallel, and the first end of its parallel connection is connected with the drain electrode of transistor seconds, the second end ground connection.The capacity of the 4th electric capacity C4 is 0.1U, and the capacity of the 5th electric capacity C5 is 10U.
As a specific embodiment, as shown in Figure 7, switch element comprises: third transistor Q3, transistor seconds Q2, and the second resistance R2, wherein, the first end of the second resistance R2 is connected with the output terminal of state latch unit, second end is connected with the grid of third transistor Q3, and the source electrode of third transistor Q3 is connected with power supply unit, and drain electrode is connected with the grid of transistor seconds Q2; The source electrode of transistor seconds Q2 is connected with power supply unit, and drain electrode is connected with power supply unit.Particularly, third transistor Q3 and transistor seconds Q2 is PMOS transistor, and its model is P5103EMG.Further, also comprise a RC delay circuit in switch element, comprising: the first divider resistance R3, the second divider resistance R4, and the second electric capacity C2; Wherein, first divider resistance R3 and the second electric capacity C2 is connected in parallel, its first end be connected in parallel is connected with the source electrode of power supply unit and transistor seconds Q2 respectively, and its second end connected is connected with the first end of the second divider resistance R4 and the grid of transistor seconds Q2 respectively; The second end ground connection of the second divider resistance R4.The workflow of the present embodiment and switch element comprise the first transistor Q1 and transistor seconds Q2 is similar, is a PMOS unlike third transistor Q3, namely when its grid is low level input (d type flip flop output low level), and just conducting; The effect of the RC circuit in switch element also with describe similar above, do not repeat at this.Particularly, in the present embodiment, the resistance of the second resistance is 1K, and the resistance of the first divider resistance is 1.0M, and the resistance of the second divider resistance R4 is 20K; The capacity of the second electric capacity C2 is 0.22U.
Further, in switch element, also comprise the 3rd electric capacity C3, the 4th electric capacity C4, and the 5th electric capacity C5, wherein, the first end of the 3rd electric capacity C3 is connected with power supply unit, the second end ground connection, and particularly, it is a filter capacitor, and the capacity at its two ends is 0.1U.4th electric capacity C4 and the 5th electric capacity C5 is connected in parallel, and the first end of its parallel connection is connected with the drain electrode of transistor seconds, the second end ground connection.The capacity of the 4th electric capacity C4 is 0.1U, and the capacity of the 5th electric capacity C5 is 10U.
Be described in detail the specific embodiment of utility model above, but the utility model is not restricted to specific embodiment described above, it is just as example.To those skilled in the art, any equivalent modifications that this system is carried out and substituting also all among category of the present utility model.Therefore, equalization conversion done under the spirit and scope not departing from utility model and amendment, all should be encompassed in scope of the present utility model.
Claims (10)
1. a power-supplying circuit, be connected with CPU (central processing unit) and power supply unit respectively, it is characterized in that, comprise: a state latch unit, one switch element and a power supply unit, the input end of described state latch unit is connected with the output terminal of described CPU (central processing unit), and the output terminal of described state latch unit is connected with the input end of described switch element, and the output terminal of described switch element is connected with described power supply unit; Described power supply unit is connected with described state latch unit and described switch element respectively, for described state latch unit and described switch element are powered;
Described CPU (central processing unit) is outputed signal is sent to described state latch unit, output signal described in described state latch cell response, the enable signal simultaneously exported latches, and whether the described enable signal judgement that described switch element receives according to it is that described power supply unit is powered.
2. power-supplying circuit as claimed in claim 1, it is characterized in that, described state latch unit comprises: a trigger, first resistance, and first electric capacity, and the output signal of described CPU (central processing unit) comprises control signal and input signal, wherein, the signal input part of described trigger is connected with described central control unit respectively with control signal end, receives the described input signal of described central control unit transmission and described control signal; Signal output part is connected with the first end of described first resistance, and power end is connected with described power supply unit, earth terminal ground connection; Second end of described first resistance is connected with described power supply unit, and the first end ground connection of described first electric capacity, the second end is connected with described power supply unit.
3. power-supplying circuit as claimed in claim 2, it is characterized in that: described trigger is d type flip flop, when the control signal of the end of control signal described in d type flip flop input rises, described d type flip flop is triggered, its signal output part exports the enable signal identical with signal input part level, described enable signal is latched simultaneously and keep export, until described control signal again there is rising signals, then described in described d type flip flop Resurvey, the state of input signal makes response.
4. power-supplying circuit as claimed in claim 1, it is characterized in that, described switch element comprises: the first transistor and transistor seconds, wherein, the grid of described the first transistor is connected with the output terminal of described state latch unit, source ground, and drain electrode is connected with the grid of described transistor seconds; The source electrode of described transistor seconds is connected with described power supply unit, and drain electrode is connected with described power supply unit.
5. power-supplying circuit as claimed in claim 4, it is characterized in that: described the first transistor is a nmos pass transistor, described transistor seconds is a PMOS transistor.
6. power-supplying circuit as claimed in claim 4, it is characterized in that, described switch element also comprises a RC delay circuit, comprising: the first divider resistance, the second divider resistance, and the second electric capacity; Wherein, described first divider resistance is connected with described second Capacitance parallel connection, its first end be connected in parallel is connected with the source electrode of described power supply unit and described transistor seconds respectively, and its second end connected is connected with the first end of described second divider resistance and the grid of described transistor seconds respectively; Second end of described second divider resistance is connected with the drain electrode of described the first transistor.
7. power-supplying circuit as claimed in claim 1, it is characterized in that, described switch element comprises: transistor seconds, third transistor, and the second resistance, wherein, the first end of described second resistance is connected with described power supply unit, second end is connected with the source electrode of described third transistor, and the grid of described third transistor is connected with the output terminal of described state latch unit, and drain electrode is connected with the grid of described transistor seconds; The source electrode of described transistor seconds is connected with described power supply unit, and drain electrode is connected with described power supply unit.
8. power-supplying circuit as claimed in claim 7, is characterized in that: described transistor seconds and described third transistor are PMOS transistor.
9. power-supplying circuit as claimed in claim 7, it is characterized in that, described switch element also comprises a RC delay circuit, comprising: the first divider resistance, the second divider resistance, and the second electric capacity; Wherein, described first divider resistance is connected with described second Capacitance parallel connection, its first end be connected in parallel is connected with the source electrode of described power supply unit and described transistor seconds respectively, and its second end connected is connected with the first end of described second divider resistance and the grid of described transistor seconds respectively; Second end ground connection of described second divider resistance.
10. power-supplying circuit as described in as arbitrary in claim 4-9, is characterized in that: also comprise the 3rd electric capacity in described switch element, the 4th electric capacity, and the 5th electric capacity, wherein,
The first end of described 3rd electric capacity is connected with described power supply unit, the second end ground connection;
Described 4th electric capacity is connected with described 5th Capacitance parallel connection, and the first end of its parallel connection is connected with the drain electrode of described transistor seconds, the second end ground connection.
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| CN107145207B (en) * | 2017-05-06 | 2020-04-07 | 湖南融和微电子有限公司 | Wake-up circuit in standby state mode |
| CN107797641A (en) * | 2017-10-19 | 2018-03-13 | 广东乐心医疗电子股份有限公司 | Power supply control method and control circuit for processor and electronic equipment |
| CN109932970A (en) * | 2019-03-22 | 2019-06-25 | 成都开图医疗系统科技有限公司 | A kind of Medical Devices emergency stop self-locking device |
| CN111668900A (en) * | 2020-06-16 | 2020-09-15 | 上海深湾能源科技有限公司 | Battery management system and control method |
| CN113296444A (en) * | 2021-06-02 | 2021-08-24 | 深圳木芯科技有限公司 | Switch control circuit and electronic equipment |
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