CN204463019U - A power supply control circuit - Google Patents

Abstract

The utility model relates to electronic circuit field, particularly relate to a kind of power-supplying circuit, comprise: a state latch unit, one switch element and a power supply unit, the input end of state latch unit is connected with the output terminal of CPU (central processing unit), the output terminal of state latch unit is connected with the input end of switch element, and the output terminal of switch element is connected with power supply unit; Power supply unit is connected with state latch unit and switch element respectively, for state latch unit and switch element are powered; CPU (central processing unit) is outputed signal is sent to state latch unit, and state latch cell response outputs signal, and the enable signal simultaneously exported latches, and whether the enable signal judgement that switch element receives according to it is that power supply unit is powered.Whole power-supplying circuit only only used simple and reliable logical circuit, with the break-make of simple structure by gauge tap unit, achieves when after CPU (central processing unit) power-off, the function still can powered for follow-up power supply unit.

Description

A power supply control circuit

technical field

The utility model relates to the field of electronic circuits, in particular to a control circuit capable of supplying power to a network chip after the system is powered off.

Background technique

With the popularity of computers and networks, people are increasingly inseparable from computers and networks. Although notebook computers can be easily carried and used, and the development of the Internet makes it possible for people to get the resources they need with the help of the Internet everywhere, but People are not satisfied with this. Due to the storage and call of resources, in order to improve work efficiency, people often not only want to use the computers around them at any time, but also want to use computers that are not around them at any time, such as computers at home or in the office. , the computer's remote network wake-up and remote control have gradually received attention.

Electronic products with network functions commonly used in the market, in order to achieve the purpose of remote control, after the CPU (Central Processing Unit, central processing unit) of the electronic product is turned off, the product needs to be woken up and controlled through an available network. In order to achieve this goal, it is necessary for the product to be able to determine whether to supply power to some chips in the network according to the control instructions before the CPU is powered off when the CPU is not powered on.

In existing products, after the CPU is powered off, SCM programming is generally used to control whether to supply power to the network part, but its cost is relatively high, and it needs to cooperate with it through a complex hardware structure.

Utility model content

In view of the above problems, the utility model provides a power supply control circuit, which only uses a simple logic circuit to replace the traditional single-chip microcomputer to control the power supply, and has a simple structure and effectively reduces the cost.

The utility model provides a power supply control circuit, which mainly includes:

A kind of power supply control circuit, is connected with central processing unit and power supply unit respectively, comprises: a state latch unit, a switch unit and a power supply unit, the input end of described state latch unit and the output end of described central processing unit connected, the output end of the state latch unit is connected to the input end of the switch unit, and the output end of the switch unit is connected to the power supply unit; the power supply unit is respectively connected to the state latch unit and the The switch unit is connected to supply power to the state latch unit and the switch unit;

The central processing unit sends its output signal to the state latch unit, and the state latch unit responds to the output signal and simultaneously latches the enable signal output by it, and the switch unit receives the The enabling signal determines whether to supply power to the power supply unit.

In this embodiment, the output state of the power supply control circuit is controlled to the state currently required by the user through the state latch unit, that is, when the power supply unit needs to be woken up to work, the state latch unit and the switch unit cooperate to output a high level, When it is not necessary to supply power to the power supply unit, the switch unit is disconnected through the state latch unit. In the utility model, the design structure of the entire power supply control circuit is simple and easy to implement in practical applications.

Preferably, the state latch unit includes: a flip-flop, a first resistor, and a first capacitor, and the output signal of the central processing unit includes a control signal and an input signal, wherein the signal input terminal of the flip-flop and the control signal end are respectively connected with the central processing unit, and receive the input signal and the control signal sent by the central processing unit; the signal output end is connected with the first end of the first resistor, and the power end is connected with the The power supply unit is connected, and the ground terminal is grounded; the second terminal of the first resistor is connected to the power supply unit, the first terminal of the first capacitor is grounded, and the second terminal is connected to the power supply unit.

In this embodiment, the central processing unit controls the state latch unit through the control signal and the input signal, triggers the state latch unit through the control signal, and performs an enabling operation on it, that is, only when the control signal satisfies a certain condition, The state latch unit responds to the incoming input signal. The combined use of the two signals realizes state switching according to user requirements, increasing the flexibility of the power supply control circuit.

Preferably, the flip-flop is a D flip-flop. When the control signal input to the control signal terminal in the D flip-flop rises, the D flip-flop is triggered, and its signal output terminal outputs the same level as the signal input terminal. enable signal, and at the same time latch and keep outputting the enable signal until the rising signal of the control signal appears again, then the D flip-flop re-acquires the state of the input signal to respond.

As shown in Figure 2-7, D, CP and Q shown in the figure respectively correspond to the signal input terminal, control signal terminal and signal output terminal in the utility model. It can be seen from Figure 2 that only when the control signal is on the rising edge, the output signal will collect the state of the input signal to make a corresponding response, and the output will not collect the input again for output until the next rising edge of the control signal arrives. In this way, before the central processing unit is turned off, the D flip-flop will maintain the required output by outputting the input signal (first) and the control signal (later) with sequential timing, and then the central processing unit is turned off again, so that the D flip-flop to maintain the output signal at the desired level. In this way, the working state of the electronic product is latched when no control chip is working, so as to ensure the normal operation of the product when the system is shut down.

Preferably, the switch unit includes: a first transistor and a second transistor, wherein the gate of the first transistor is connected to the output terminal of the state latch unit, the source is grounded, and the drain is connected to the second transistor. The gate of the transistor is connected; the source of the second transistor is connected to the power supply unit, and the drain is connected to the power supply unit.

Preferably, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor

Preferably, the switch unit further includes an RC delay circuit, including: a first voltage dividing resistor, a second voltage dividing resistor, and a second capacitor; wherein, the first voltage dividing resistor is connected in parallel with the second capacitor The first end connected in parallel is respectively connected to the source of the power supply unit and the second transistor, and the second end is connected to the first end of the second voltage dividing resistor and the second transistor respectively. The gate of the transistor is connected; the second terminal of the second voltage dividing resistor is connected with the drain of the first transistor.

Preferably, the switch unit includes: a second transistor, a third transistor, and a second resistor, wherein the first end of the second resistor is connected to the power supply unit, and the second end is connected to the third transistor. The source is connected, the gate of the third transistor is connected to the output terminal of the state latch unit, and the drain is connected to the gate of the second transistor; the source of the second transistor is connected to the power supply unit connected, and the drain is connected to the power supply unit.

Preferably, both the second transistor and the third transistor are PMOS transistors.

Preferably, the switch unit further includes an RC delay circuit, including: a first voltage dividing resistor, a second voltage dividing resistor, and a second capacitor; wherein, the first voltage dividing resistor is connected in parallel with the second capacitor connection, the first end of the parallel connection is respectively connected to the source of the power supply unit and the second transistor, and the second end of the connection is respectively connected to the first end of the second voltage dividing resistor and the second The gate of the transistor is connected; the second terminal of the second voltage dividing resistor is grounded.

Preferably, the switch unit further includes a third capacitor, a fourth capacitor, and a fifth capacitor, wherein,

A first end of the third capacitor is connected to the power supply unit, and a second end of the capacitor is grounded.

The fourth capacitor and the fifth capacitor are connected in parallel, and the first end of the parallel connection is connected to the drain of the second transistor, and the second end is grounded.

In summary, the power supply control circuit provided by the utility model can bring at least one of the following beneficial effects:

1. In the utility model, through the mutual cooperation of the trigger in the state latch unit and the transistor in the switch unit, the switch unit is effectively turned on and off, that is, when it is necessary to supply power to the subsequent power supply unit, the control switch The unit is turned on, and when it is not necessary to supply power to the subsequent power supply unit, the control switch unit is turned off. The design of the entire circuit only uses a simple but highly reliable logic circuit to realize the function of supplying power to the subsequent power supply unit after the central processing unit is powered off;

2. In this utility model, a simple logic circuit is used instead of a conventional single-chip microcomputer, which not only reduces hardware costs, but also reduces the workload of software engineers and reduces the probability of product errors;

3. In the utility model, the designed power supply control circuit is widely used, and it can be transplanted to most electronic products with wake-up on network, and has strong versatility; and it does not need to be designed and tested separately for different products, greatly reducing design and The time cost of testing.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the utility model is described in further detail:

Fig. 1 is the structural block diagram schematic diagram of power supply control circuit in the utility model;

Fig. 2 is the circuit schematic diagram of state latch unit in the utility model;

Fig. 3 is the circuit diagram of a kind of embodiment in the switch unit in the utility model;

Fig. 4 is a circuit diagram of an embodiment of the power supply control circuit in the utility model;

Fig. 5 adds the power supply control circuit diagram of RC delay circuit in the utility model;

Fig. 6 is the circuit diagram of the complete embodiment of power supply control circuit in the utility model;

Fig. 7 is a circuit diagram of another embodiment of the power supply control circuit in the utility model.

Detailed ways

In order to illustrate the embodiments of the utility model or the technical solutions in the prior art more clearly, the utility model will be specifically described below in conjunction with the accompanying drawings and embodiments. The drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

As a specific embodiment, as shown in Figure 1, the power supply control circuit provided by the utility model is respectively connected to the central processing unit and the power supply unit, and the power supply control circuit mainly includes: a state latch unit, a switch unit and a power supply unit , the input end of the state latch unit is connected with the output end of the central processing unit, the output end of the state latch unit is connected with the input end of the switch unit, and the output end of the switch unit is connected with the power supply unit; the power supply unit is respectively connected with the state latch unit It is connected with the switch unit and supplies power to the state latch unit and the switch unit. In practical applications, the central processing unit sends the output signal to the state latch unit, and the state latch unit responds to the output signal of the central processing unit, and at the same time latches the signal output by it, and the switch unit receives the enable The signal determines whether to supply power to the power supply unit.

The switch unit generally includes two forms. One is to use the output signal of the trigger to directly control the enable pin of the voltage conversion chip. If the enable signal is disabled, the power chip will not work as a whole and the power consumption of the overall product will be reduced. In another case, some voltage conversion chips need to work under all conditions, such as powering the real-time clock of the product. In this case, the output of the flip-flop must control a switch unit, and the switch unit is turned on. The power supply unit supplies power; the switch unit closes and only supplies power to the real-time clock. In the utility model, the above-mentioned power supply unit is provided by a 3.3V voltage conversion chip, which has power in any state, as shown in Figure 2-7, in the figure V_S_3V3 is the power supply unit, which is not only the switch unit The power supply for each device and the state latch unit at the same time; the power supply unit is the network chip that needs power supply, that is, the PHY_3V3 in Figure 3-7; the central processing unit is the CPU (Central Processing Unit) in the computer. In particular, the utility model does not limit the voltage conversion chip included in the power supply unit, as long as it can supply power to the power supply control circuit in the utility model, it is included in the content of the utility model.

Further, the output signal of the central processing unit specifically includes a control signal and an input signal, and the control signal and the input signal are sent to the state latch unit. In order to enable the state latch unit to latch its output state, in the utility model, a control signal is used to effectively control its output state.

As a specific embodiment, as shown in FIG. 2, the state latch unit includes: a flip-flop, a first resistor R1, and a first capacitor C1, and the output signal of the central processing unit includes a control signal and an input signal, wherein the trigger The signal input end and the control signal end of the device are connected with the central processing unit respectively, and receive the input signal and the control signal sent by the central processing unit; the signal output end is connected with the first end of the first resistor R1, the power end is connected with the power supply unit, and grounded The terminal is grounded; the second terminal of the first resistor R1 is connected to the power supply unit, the first terminal of the first capacitor C1 is grounded, and the second terminal is connected to the power supply unit. Specifically, when the control signal output by the central processing unit reaches the trigger condition of the flip-flop, the flip-flop makes a corresponding output response according to the received input signal, and at the same time performs state latching according to the current enable output signal until The arrival of the next trigger condition that satisfies the trigger. In the specific implementation process, in the present invention, the resistance value of the first resistor R1 is 1K, and the capacity value of both ends of the first capacitor C1 is 0.1U.

Further, in the present utility model, flip-flop U1 is a D flip-flop, as shown in Figure 2 and Table 1, wherein, Table 1 is the truth table of the D flip-flop, specifically, when the control signal in the D flip-flop When the control signal input at the terminal rises, the D flip-flop is triggered, and its signal output terminal outputs an enable signal with the same level as the signal input terminal, and at the same time, the enable signal is latched until the control signal rises again, then the D trigger The flip-flop re-acquires the state of the input signal to respond, that is, in the present invention, by controlling the output state of the D flip-flop to control the turn-on and turn-off of the subsequent switch unit. In the specific implementation process, the model of the D flip-flop of the present utility model is 74AHC1G79, and the PHY_POWER_ENH and D_control signals shown in the figure correspond to the signal input terminal (the D port in the D flip-flop) and the control signal end (in the D flip-flop) respectively. CP port), GND is the ground terminal, and VCC is the power supply terminal. In particular, the present invention does not limit the specific form of the flip-flop. For example, JK flip-flop, RS flip-flop, T flip-flop, etc. can also be used in combination or through other forms of AND gate, NOT gate, or NAND gate The mutual combination use among them, as long as it can realize the purpose of the utility model, all include in the utility model.

Table 1: Truth Table for D Flip-Flops

Specifically, in the present utility model, the switch unit includes: a first transistor Q1 and a second transistor Q2, wherein the gate of the first transistor Q1 is connected to the output end of the state latch unit, the source is grounded, and the drain is connected to the second transistor Q2. The gate of the second transistor Q2 is connected; the source of the second transistor Q2 is connected to the power supply unit, and the drain is connected to the power supply unit. Furthermore, as shown in Figure 3, the first transistor Q1 is an NMOS transistor; the second transistor Q2 is a PMOS transistor, specifically, the model of the NMOS transistor is 2N7002, and the model of the PMOS transistor is P5103EMG, and in the present invention, the The model of the transistor is not limited, as long as it can realize the purpose of the utility model, it is included in the content of the utility model.

As a complete embodiment, the flip-flop U1 in the state latch unit is a D flip-flop, the first transistor Q1 in the switch unit is an NMOS transistor, and the second transistor Q2 is a PMOS transistor, as shown in FIG. 4 , Describe its workflow as follows:

The central processing unit outputs the input signal and the control signal (first output the input signal and maintain the level, then output the control signal) to the state latch unit before power-off, and the rising edge of the control signal is at a high level when the input signal Input a D flip-flop, then after the D flip-flop is triggered, it outputs a high level (enable signal), and keeps the high level output.

At this time, the gate of the first transistor Q1 (NMOS transistor) in the switch unit is a high-level input, and the voltage difference between the gate and the source is greater than the conduction voltage of the first transistor Q1, so the first transistor Q1 conducts The drain is low-level output; that is, the gate low-level input of the second transistor Q2 connected to the drain of the first transistor Q1, at this time, the voltage difference between the gate and source of the second transistor Q2 reaches The conduction condition of the second transistor Q2, and then the conduction of the second transistor Q2, supplies power for the subsequent power supply unit (network chip).

Similarly, when the rising edge of the control signal is input to the D flip-flop when the pulse is at low level, the D flip-flop will output low level after being triggered, and keep the low level output; at this time, the first switch unit in the switch unit The gate of a transistor Q1 (NMOS transistor) is a low-level input, so that the first transistor Q1 is not turned on, and its drain is at a high level; that is, the gate of the second transistor Q2 connected to the drain of the first transistor Q1 High-level input, so the second transistor Q2 is not turned on at this time, and the drain has almost no output, that is, it does not supply power to the subsequent power supply unit (network chip).

Further, the switch unit also includes an RC delay circuit, as shown in Figure 5, including: a first voltage dividing resistor R3, a second voltage dividing resistor R4, and a second capacitor C2; wherein, the first voltage dividing resistor R3 and The second capacitor C2 is connected in parallel, the first end of the parallel connection is respectively connected with the power supply unit and the source of the second transistor Q2, and the second end of the connection is respectively connected with the first end of the second voltage dividing resistor R4 and the second transistor The gate of Q2 is connected; the second terminal of the second voltage dividing resistor R4 is connected with the drain of the first transistor Q1.

In practical applications, the power supply unit can be equivalently connected in parallel with a resistor and a capacitor. At this time, if the second transistor Q2 in the switch unit is turned on too quickly, the equivalent capacitance in the power supply unit will be charged rapidly, resulting in a large spike The current appears between the drain and source of Q2, and it may even burn out Q2. If the current is larger, it may even burn out the external transformer and power input interface. Therefore, in the utility model, an RC delay circuit is designed before the second transistor Q2, and the conduction speed of the second transistor Q2 is reduced by controlling the resistance values of the first voltage dividing resistor R3 and the second voltage dividing resistor R4 , thereby reducing the peak value of the peak current. In practical applications, there are no specific restrictions on the selection of the resistance values of the first voltage dividing resistor R3 and the second voltage dividing resistor R4, as long as the selection of the resistance values can ensure that the second transistor Q2 is completely turned on, such as R3>10* R4. Specifically, in the utility model, in order to ensure that the second transistor Q2 is opened slowly enough, the resistance value of the first voltage dividing resistor R3 is 1.0M, and the resistance value of the second voltage dividing resistor R4 is 20K; the capacity of the second capacitor C2 It is 0.22U. In actual use, in the switch unit, after the electrical signal is output from the first transistor Q1 and before it is input to the second transistor Q2, the gate electrical signal first passes through the above-mentioned RC delay circuit to protect the second transistor Q2 and the entire The role of the power supply control circuit.

Further, as shown in FIG. 6, the switch unit further includes a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5, wherein the first terminal of the third capacitor C3 is connected to the power supply unit, and the second terminal is grounded. Specifically, it is a filter capacitor with a capacity of 0.1U at both ends. The fourth capacitor C4 and the fifth capacitor C5 are connected in parallel, and the first end of the parallel connection is connected to the drain of the second transistor, and the second end is grounded. The capacity of the fourth capacitor C4 is 0.1U, and the capacity of the fifth capacitor C5 is 10U.

As a specific embodiment, as shown in FIG. 7, the switch unit includes: a third transistor Q3, a second transistor Q2, and a second resistor R2, wherein the first terminal of the second resistor R2 is connected to the output terminal of the state latch unit connected, the second end is connected to the gate of the third transistor Q3, the source of the third transistor Q3 is connected to the power supply unit, and the drain is connected to the gate of the second transistor Q2; the source of the second transistor Q2 is connected to the power supply unit , the drain is connected to the power supply unit. Specifically, both the third transistor Q3 and the second transistor Q2 are PMOS transistors, and their model is P5103EMG. Further, the switch unit also includes an RC delay circuit, including: a first voltage dividing resistor R3, a second voltage dividing resistor R4, and a second capacitor C2; wherein, the first voltage dividing resistor R3 is connected in parallel with the second capacitor C2 connected, the first end of the parallel connection is respectively connected to the power supply unit and the source of the second transistor Q2, and the second end of the connection is respectively connected to the first end of the second voltage dividing resistor R4 and the gate of the second transistor Q2 ; The second terminal of the second voltage dividing resistor R4 is grounded. The working process of this embodiment is similar to that of the switch unit including the first transistor Q1 and the second transistor Q2, the difference is that the third transistor Q3 is a PMOS transistor, that is, when its gate is a low-level input (the D flip-flop outputs a low power It is only turned on when it is flat); the function of the RC circuit in the switch unit is also similar to the previous description, and will not be repeated here. Specifically, in this embodiment, the resistance value of the second resistor is 1K, the resistance value of the first voltage dividing resistor is 1.0M, the resistance value of the second voltage dividing resistor R4 is 20K; the capacity of the second capacitor C2 is 0.22 U.

Further, the switch unit also includes a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5, wherein the first terminal of the third capacitor C3 is connected to the power supply unit, and the second terminal is grounded, specifically, it is a Filter capacitor, and the capacity of both ends is 0.1U. The fourth capacitor C4 and the fifth capacitor C5 are connected in parallel, and the first end of the parallel connection is connected to the drain of the second transistor, and the second end is grounded. The capacity of the fourth capacitor C4 is 0.1U, and the capacity of the fifth capacitor C5 is 10U.

The specific embodiments of the utility model have been described in detail above, but the utility model is not limited to the specific embodiments described above, which are only examples. For those skilled in the art, any equivalent modifications and substitutions to the system are also within the scope of the present utility model. Therefore, all equivalent transformations and modifications made without departing from the spirit and scope of the utility model shall fall within the scope of the utility model.

Claims (10)

1. A power supply control circuit, which is respectively connected with a central processing unit and a power supply unit, is characterized in that, comprising: a state latch unit, a switch unit and a power supply unit, the input terminal of the state latch unit is connected to the The output terminal of the central processing unit is connected, the output terminal of the state latch unit is connected with the input terminal of the switch unit, and the output terminal of the switch unit is connected with the power supply unit; the power supply unit is respectively connected with the state The latch unit is connected to the switch unit to supply power to the state latch unit and the switch unit; The central processing unit sends its output signal to the state latch unit, and the state latch unit responds to the output signal and simultaneously latches the enable signal output by it, and the switch unit receives the The enabling signal determines whether to supply power to the power supply unit. 2. The power supply control circuit according to claim 1, wherein the state latch unit includes: a flip-flop, a first resistor, and a first capacitor, and the output signal of the central processing unit includes a control signal and input signal, wherein, the signal input terminal and the control signal terminal of the trigger are respectively connected to the central control unit, and receive the input signal and the control signal sent by the central control unit; the signal output terminal is connected to the The first terminal of the first resistor is connected, the power supply terminal is connected to the power supply unit, and the ground terminal is grounded; the second terminal of the first resistor is connected to the power supply unit, the first terminal of the first capacitor is grounded, and the second terminal of the first resistor is connected to the power supply unit. The two terminals are connected with the power supply unit. 3. The power supply control circuit according to claim 2, characterized in that: the flip-flop is a D flip-flop, and when the control signal input from the control signal terminal in the D flip-flop rises, the D flip-flop is triggered, Its signal output terminal outputs an enable signal with the same level as the signal input terminal, and simultaneously latches the enable signal and keeps output until the rising signal of the control signal appears again, then the D flip-flop collects all respond to the state of the input signal. 4. The power supply control circuit according to claim 1, wherein the switch unit comprises: a first transistor and a second transistor, wherein the gate of the first transistor is connected to the output terminal of the state latch unit connected, the source is grounded, and the drain is connected to the gate of the second transistor; the source of the second transistor is connected to the power supply unit, and the drain is connected to the power supply unit. 5. The power supply control circuit according to claim 4, wherein the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. 6. The power supply control circuit according to claim 4, wherein the switch unit further comprises an RC delay circuit, comprising: a first voltage dividing resistor, a second voltage dividing resistor, and a second capacitor; wherein, the The first voltage dividing resistor is connected in parallel with the second capacitor, the first ends connected in parallel are respectively connected to the source of the power supply unit and the second transistor, and the second ends connected to the second capacitor are respectively connected to the first The first end of the two voltage dividing resistors is connected to the gate of the second transistor; the second end of the second voltage dividing resistor is connected to the drain of the first transistor. 7. The power supply control circuit according to claim 1, wherein the switch unit comprises: a second transistor, a third transistor, and a second resistor, wherein the first end of the second resistor is connected to the power supply The unit is connected, the second end is connected to the source of the third transistor, the gate of the third transistor is connected to the output end of the state latch unit, and the drain is connected to the gate of the second transistor; The source of the second transistor is connected to the power supply unit, and the drain is connected to the power supply unit. 8. The power supply control circuit according to claim 7, wherein the second transistor and the third transistor are both PMOS transistors. 9. The power supply control circuit according to claim 7, wherein the switch unit further comprises an RC delay circuit, comprising: a first voltage dividing resistor, a second voltage dividing resistor, and a second capacitor; wherein, the The first voltage dividing resistor is connected in parallel with the second capacitor, the first ends connected in parallel are respectively connected to the source of the power supply unit and the second transistor, and the second ends connected to the second capacitor are respectively connected to the first The first end of the two voltage dividing resistors is connected to the gate of the second transistor; the second end of the second voltage dividing resistor is grounded. 10. The power supply control circuit according to any one of claims 4-9, wherein the switch unit further includes a third capacitor, a fourth capacitor, and a fifth capacitor, wherein, The first end of the third capacitor is connected to the power supply unit, and the second end is grounded; The fourth capacitor and the fifth capacitor are connected in parallel, and the first end of the parallel connection is connected to the drain of the second transistor, and the second end is grounded.