CN107145207B - Wake-up circuit in standby state mode - Google Patents
Wake-up circuit in standby state mode Download PDFInfo
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- CN107145207B CN107145207B CN201710314740.6A CN201710314740A CN107145207B CN 107145207 B CN107145207 B CN 107145207B CN 201710314740 A CN201710314740 A CN 201710314740A CN 107145207 B CN107145207 B CN 107145207B
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- gate
- resistor
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- standby state
- chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
Abstract
The invention discloses a wake-up circuit in a standby state mode, which comprises a voltage detection point, and a first branch circuit, a second branch circuit and a third branch circuit which are connected with the voltage detection point, wherein the first branch circuit comprises a first NOT gate, a first D trigger and a first NOT gate which are sequentially connected, the second branch circuit comprises an OR gate, a second D trigger and a third NOT gate which are sequentially connected, and the third branch circuit comprises a resistor and an NMOS switching tube which are sequentially connected. The invention realizes the awakening of the standby state and simultaneously reduces the power consumption in the standby state to the maximum extent.
Description
Technical Field
The invention belongs to a wake-up circuit, and particularly relates to a wake-up circuit in a standby state mode.
Background
In the wake-up circuit in the existing standby mode, when the chip is in the standby state, part of the circuits can be turned off in order to save power consumption, and when the chip exits the standby state, the turned-off part of the circuits normally works. A comparator is generally used to determine whether to wake up the standby state, and the implementation method is shown in fig. 1. In the figure, CC is a voltage to be detected, reference voltage VREF is a reference voltage of the comparator, bias current IB is a working current of the comparator, the enable signal EN is used to switch the comparator, and whether to wake up the standby state is determined according to the level of the output level wake of the comparator. The existing wake-up circuit has the problem of high power in a standby state. The reason is analyzed: firstly, in a standby state, the comparator works and has power consumption; secondly, in a standby state, in order to enable the comparator to work, the bandgap circuit does not work when the reference voltage VREF is obtained, and the bias circuit needs to work when the bias current IB is obtained.
Disclosure of Invention
The invention aims to provide a wake-up circuit in a standby state mode, which can reduce standby power.
The technical scheme adopted for realizing the purpose of the invention is as follows:
the wake-up circuit in the standby state mode comprises a voltage detection point, and a first branch, a second branch and a third branch which are connected with the voltage detection point, wherein the first branch comprises a first NOT gate, a first D trigger and a first NOT gate which are sequentially connected, the second branch comprises an OR gate, a second D trigger and a third NOT gate which are sequentially connected, and the third branch comprises a resistor and an NMOS switch tube which are sequentially connected.
The voltage detection point is added, and the input end of the first NAND gate, the input end of the OR gate and the third branch which are added and connected correspondingly are also included.
The invention has the advantages of
Compared with the prior wake-up circuit in the standby state, the wake-up circuit in the standby state has the following differences:
1. the circuit of the invention only generates power consumption when waking up the standby state, is very small and can be ignored. In the conventional wake-up circuit, the comparator itself operating in the standby state has power consumption.
2. The circuit of the invention does not need other circuit support in the standby state. The traditional wake-up circuit needs a band gap circuit and a bias current circuit to support the comparator to work in a standby state, so that the power consumption of the band gap circuit and the bias current circuit in the standby state is increased.
This has the effect that the power consumption in the standby state is small. The standby state wake-up circuit realizes the wake-up of the standby state and simultaneously reduces the power consumption in the standby state to the maximum extent.
The technical scheme of the invention is further explained by combining the attached drawings.
Drawings
Fig. 1 is a diagram of a conventional standby state wake-up circuit.
Fig. 2 is a circuit diagram of the present invention.
Fig. 3 is a single input standby state wake-up circuit diagram of the present invention.
Fig. 4 is a circuit connection diagram for two modes of operation incorporating the circuit of the present invention.
FIG. 5 is a diagram of a wake-up circuit for a standby state with a middle CC voltage after wake-up according to the present invention.
FIG. 6 is a circuit diagram of two operating modes with an intermediate CC voltage after wake-up according to the present invention.
Detailed Description
Referring to fig. 2, the wake-up circuit in standby mode of the present invention includes voltage detection points CC1 and CC2, D flip-flops I20 and I17, nand gate I0, or gate I3, not gates I1 and I2, NMOS switch tubes M0 and M1, and resistors R0 — R5; the detection point CC1 is connected with the parallel ends of resistors R0, R3 and R4, the detection point CC2 is connected with the parallel ends of resistors R1, R2 and R5, the other ends of the resistors R0, R3 and R4 are respectively connected with the input end IN1 of a NAND gate I0, the input end IN2 of an OR gate I3 and the drain end of an NMOS switch tube M0, the other ends of the resistors R1, R2 and R5 are respectively connected with the input end IN2 of a NAND gate I0, the input end IN1 of an OR gate I3 and the drain end of an NMOS switch tube M1, and the gates of the NMOS switch tubes M0 and M1 are connected with the same control signal RD _ EN; the enable signal EN is respectively connected with the input ends IN of the NOT gates I1 and I2 and the input ends SET of the D flip-flops I20 and I17; the input end D of the D flip-flop I20 is connected with the output end of the NAND gate I0, and the input end CLK is connected with the output end of the NOT gate I1; the input end D of the D flip-flop I17 is connected with the output end of the OR gate I3, and the input end CLK is connected with the output end of the NOT gate I2; the output terminals Q of the D flip-flops I20 and I17 respectively output wake-up 1 and wake-up 2 as wake-up signals.
The two voltage detecting points CC1 and CC2 have the same performance, when the two CHIPs CHIP1 and CHIP 2 in the standby state are connected through their respective detecting points CC1, as shown in fig. 4, their operation modes are set to be different, and it is assumed that at this time, the CHIP1 operates in the mode one and the CHIP 2 operates in the mode two, which determine whether the NMOS switch is turned on, and the NMOS switches M0 and M1 on the CHIP1 operating in the mode one are not conductive, i.e., M0 and M1 are always turned off, and meanwhile, the voltage at the detecting points CC1 and CC2 is high in the standby state of the CHIP1 in this mode; when the CHIP 2 operating in the mode two is in the standby state, the detection point CC1 is not charged, the CC2 is not charged, and the NMOS switch transistor M2 or M3 is turned on after the CHIP 2 is awakened in the standby state, that is, the NMOS switch transistor M2 or M3 is turned on after the CHIP 2 is awakened.
The CHIP1 is waken by wake-up 1 in the standby state when operating in the mode one, and the CHIP 2 is waken by wake-up signal output wake-up 2 in the standby state when operating in the mode two.
In the standby state, CHIP 2 is connected to probing point CC1 of CHIP1 through probing point CC1 (see fig. 4). For CHIP 2, detection point CC1 before connection is not charged, detection point CC1 after connection is high, then wake-up signal output wake 2 is high, CHIP 2 is woken up, and exits from standby state, and control signal RD _ EN goes from low to high, that is, NMOS switch M2 is turned on after CHIP 2 is woken up, resistor R10 is turned on, detection point CC1 goes from high to low, EN goes from low to high, and lock-up signal output wake-up 2 signal. When the level at detection point CC1 changes from high to low, the WAKEUP1 signal for the wake-up signal output of CHIP1 changes to high, and wakes up and exits the standby mode, and EN changes from low to high, and the WAKEUP1 signal is output as the lock wake-up signal. In this way, the CHIPs CHIP1 and CHIP 2 in the first and second modes in the standby state are both brought into abutment and then awakened.
In use, if the voltage at the detection point CC is at an intermediate value between the high and low levels after the standby state is awakened, the inputs of the nand gate and the or gate connected to the detection point CC will have intermediate values, which will cause current leakage, so that after the awakening, the power of the nand gate I0 and the or gate I3 inputted from the detection point CC in fig. 2 needs to be turned off, as shown in fig. 5. IN fig. 5, a detection point CC1 is connected to the parallel ends of resistors R0, R3 and R4, a detection point CC2 is connected to the parallel ends of resistors R1, R2 and R5, the other ends of resistors R0, R3 and R4 are respectively connected to the input end IN1 of a nand gate I0, the input end IN2 of an or gate I3 and the drain of an NMOS switch tube M0, the other ends of resistors R1, R2 and R5 are respectively connected to the input end IN2 of a nand gate I0, the input end IN1 of an or gate I3 and the drain of an NMOS switch tube M1, and the gates of NMOS switch tubes M0 and M1 are connected to the same control signal RD _ EN; the enable signal EN is respectively connected with the input ends IN of the NOT gates I1, I2 and I6, one input end IN1 of the OR gate I4, the gates of the PMOS tubes M2 and M3 and the input ends SET of the D flip-flops I20 and I17; the output end of the NAND gate I0 is connected with one input end IN2 of the OR gate I4, and the power supply end of the NAND gate I0 is connected with the drain end of the PMOS tube M2; the output end of the OR gate I3 is connected with an input end IN2 of the AND gate I5, and the power supply end of the OR gate I3 is connected with the drain end of the PMOS tube M3; the output end of the NOT gate I6 is connected with the other input end IN1 of the AND gate I5; the input end D of the D flip-flop I20 is connected with the output end of the OR gate I4, and the input end CLK is connected with the output end of the NOT gate I1; the input end D of the D flip-flop I17 is connected with the output end of the I5, and the input end CLK of the D flip-flop I17 is connected with the output end of the NOT gate I2; the output terminals Q of the D flip-flops I20 and I17 respectively output wake-up 1 and wake-up 2 as wake-up signals.
When used in a charging CHIP, CHIPs CHIP1 and CHIP 2 operating in two modes, dfp (downstream Facing port) and ufp (upstream Facing port), are connected to each other through a probing point CC1, as shown in fig. 6. At this time, the CHIP1 works in the DFP mode, the CHIP 2 works in the UFP mode, the NMOS switching tubes M0 and M1 of the CHIP1 working in the DFP mode are not turned on, that is, M0 and M1 are always turned off, and meanwhile, the voltages of the detection points CC1 and CC2 of the CHIP1 are high in the standby state; the detection points CC1 and CC2 of the CHIP 2 operating in the UFP mode are not charged in the standby state, and the NMOS switching tubes M6 and M7 are turned on after the standby state of the CHIP 2 is woken up, that is, M6 and M7 are turned on after the standby state is woken up.
The CHIP1 operating in the DFP mode wakes up by the wake-up signal output wake 1 in the standby state, and the CHIP 2 operating in the UFP mode wakes up by the wake-up signal output wake 2 in the standby state.
In the standby state, the UFP mode CHIP 2 is connected to the DFP mode CHIP1 through the probing point CC1 as shown in fig. 6. For CHIP 2, detection point CC1 before connection is not charged, detection point CC1 after connection is high, then wake-up signal output wake 2 after connection is high, CHIP 2 is woken up, and exits from standby mode, and control signal RD _ EN goes from low to high, that is, NMOS switch M6 turns on after CHIP 2 is woken up, resistor R15 is turned on, detection point CC1 goes from high to low, enable signal EN goes from low to high, and lock-up signal output wake-up 2 signal. When the detection point CC1 changes from high to low, the WAKEUP1 signal of the DFP mode CHIP1 goes high, the CHIP1 wakes up, the standby mode exits, the enable signal EN changes from low to high, and the WAKEUP1 signal is output as the lock-on wake-up signal. Thus, the CHIP1 and the CHIP 2 in the standby state are both waked up after being brought into contact with each other.
After waking up, the enable signal EN of the DFP operation mode CHIP1 and the UFP operation mode CHIP 2 in fig. 6 changes from the low level in the standby state to the high level after waking up, and powers off the nand gates I0 and I7 and the or gates I3 and I10, which have the probing point CC as an input, so that when they operate, the probing point CC voltage does not leak current to I0, I7, I3, and I10. The AND gates I5 and I12 and the OR gates I4 and I11 in FIG. 6 are also used to ensure that the D input of the D flip-flop is prevented from generating a leakage current due to an intermediate value.
The invention can also set one or more than two detection points with the same performance according to the requirement, and only needs to connect the added detection points to the input ends with the same number respectively added by the NAND gate I0 and the OR gate I3, and to add the NMOS switch tubes with the same number and the resistors on the switch tubes, and to connect the added detection points to the added resistors.
If the detection point is a detection point CC, it is shown in fig. 3. A detection point CC is connected with the parallel ends of resistors R1, R2 and R5, the other ends of the resistors R1, R2 and R5 are respectively connected with an input end IN of a NOT gate I5 and a drain end of a switch tube M1 of an input end D, NMOS of a D flip-flop I17, a grid electrode of the NMOS switch tube M1 is connected with a control signal RD _ EN, and an enable signal EN is respectively connected with the input ends IN of the NOT gates I1 and I2 and the input ends SET of the D flip-flops I20 and I17; the input end D of the D flip-flop I20 is connected with the output end of the NOT gate I5, and the input end CLK thereof is connected with the output end of the NOT gate I1; the input end CLK of the D flip-flop I17 is connected with the output end of the NOT gate I2; the output terminals Q of the D flip-flops I20 and I17 are used as wake-up signals to output WAKEUP1 and WAKEUP 2.
Claims (1)
1. A wake-up circuit in a standby state mode is characterized by comprising a first chip and a second chip which are connected with each other, wherein the first chip and the second chip respectively comprise a first voltage detection point, a second voltage detection point, a first D trigger, a second D trigger, a NAND gate, an OR gate, a first NOT gate, a second NOT gate, a first NMOS switching tube, a second NMOS switching tube and a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a; the first detection point is connected with the parallel ends of the first resistor, the fourth resistor and the fifth resistor, the second detection point is connected with the parallel ends of the second resistor, the third resistor and the sixth resistor, the other ends of the first resistor, the fourth resistor and the fifth resistor are respectively connected with the input end of the NAND gate, the input end of the OR gate and the drain end of the first NMOS switch tube, the other ends of the second resistor, the third resistor and the sixth resistor are respectively connected with the input end of the NAND gate, the input end of the OR gate and the drain end of the second NMOS switch tube, and the grids of the first NMOS switch tube and the second NMOS switch tube are connected with the same control signal; the enabling signals are respectively connected with the input ends of the first NOT gate and the second NOT gate and the set input ends of the first D trigger and the second D trigger; the D input end of the first D trigger is connected with the output end of the NAND gate, and the Clk input end of the first D trigger is connected with the output end of the first NAND gate; the D input end of the second D trigger is connected with the output end of the OR gate, and the Clk input end of the second D trigger is connected with the output end of the second NOT gate; q output ends of the first D trigger and the second D trigger are respectively used as wake-up signals to be output; the working modes of the first chip and the second chip are different, and the first detection point voltage and the second detection point voltage of the first chip are different from the first detection point voltage and the second detection point voltage of the second chip under different modes.
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| CN201710314740.6A CN107145207B (en) | 2017-05-06 | 2017-05-06 | Wake-up circuit in standby state mode |
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| CN201710314740.6A CN107145207B (en) | 2017-05-06 | 2017-05-06 | Wake-up circuit in standby state mode |
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| CN107145207A CN107145207A (en) | 2017-09-08 |
| CN107145207B true CN107145207B (en) | 2020-04-07 |
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| CN107145207A (en) | 2017-09-08 |
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