CN106294244A - A kind of USB Type C interface circuit - Google Patents

A kind of USB Type C interface circuit Download PDF

Info

Publication number
CN106294244A
CN106294244A CN201610657211.1A CN201610657211A CN106294244A CN 106294244 A CN106294244 A CN 106294244A CN 201610657211 A CN201610657211 A CN 201610657211A CN 106294244 A CN106294244 A CN 106294244A
Authority
CN
China
Prior art keywords
level
nodal point
equipment
signal
point voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610657211.1A
Other languages
Chinese (zh)
Other versions
CN106294244B (en
Inventor
刘靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Huinengtai Semiconductor Technology Co Ltd
Original Assignee
Shenzhen Huinengtai Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Huinengtai Semiconductor Technology Co Ltd filed Critical Shenzhen Huinengtai Semiconductor Technology Co Ltd
Priority to CN201610657211.1A priority Critical patent/CN106294244B/en
Publication of CN106294244A publication Critical patent/CN106294244A/en
Application granted granted Critical
Publication of CN106294244B publication Critical patent/CN106294244B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

The present embodiments relate to USB interface technical field, particularly relate to a kind of USB Type C interface circuit.Wherein, this USB Type C interface circuit is used for detecting external equipment, including the first signal end and secondary signal end, also includes: controller；First current source circuit, itself and controller connect；Second current source circuit, itself and controller connect；Logic circuit, itself and controller connect；Comparison module, its input and logic circuit connect, and outfan and controller connect.Use the present invention, on the one hand, this USB Type C interface circuit can be according to the type of external equipment, with external equipment successful handshake, i.e. identify UFP equipment or DFP equipment or DRP equipment, on the other hand, external equipment can connect the first signal end or secondary signal end the most in conversion, this USBType C interface circuit can timely respond in this conversion, and therefore, this USB Type C interface circuit identifies the direction of insertion of external equipment.

Description

A kind of USB Type-C interface circuit
Technical field
The present embodiments relate to USB interface technical field, particularly relate to a kind of USB Type-C interface circuit.
Background technology
Along with popularizing of USB Type-C interface, the most equipment that gets up needs to support USB Type-C agreement.According to The regulation of Type-C standard agreement, Type-C interface has 24 interfaces of positive anti-communism, wherein 12, front, reverse side 12.Fig. 1 is The schematic diagram of each pin definitions of USB Type-C socket under Type-C standard agreement.As it is shown in figure 1, USB Type-C socket Including the first signal end CC1 and secondary signal end CC2.
According to Type-C agreement, supporting that the mode of operation of Type-C protocol devices can be generally divided into three kinds, the first is UFP pattern (Upstream Facing Port, uplink port), is from machine, from machine from main frame power taking.The second is DFP mould Formula (Downstream Facing Port, downlink port), is main frame, and main frame provides power supply to from machine.The third is DRP mould Formula (Dual RolePort, bidirectional port).DRP pattern can be operated in DFP pattern can also be operated in UFP pattern.Work as DRP Equipment is connected to UFP equipment, and DRP equipment translates into DFP equipment, and when DRP equipment is connected to DFP equipment, DRP equipment just converts For UFP equipment.When two DRP equipment link together, when any one party is operated in DFP pattern, the opposing party translates into UFP equipment.When any one party is operated in UFP pattern, the opposing party translates into DFP equipment.
Fig. 2 is the principle schematic that under Type-C standard agreement, DFP equipment communicates with UFP equipment.As in figure 2 it is shown, for For DFP equipment, the first signal end CC1 and secondary signal end CC2 there is upper resistance Rp connect direct voltage source, or connect Connect and draw current source, Fig. 2 to be illustrated that direct voltage source.For UFP equipment, in the first signal end CC1 and secondary signal Pull down resistor Rd is had on end CC2.When being not connected with, for DFP equipment, CC1 and CC2 is all drawn high to high level by inside, For UFP equipment, CC1 and CC2 is all pulled low to low level by inside.When DFP equipment is connected with UFP equipment, for DFP For equipment, CC1 or CC2 can detect that level is pulled low, and now explanation equipment has connected, and equipment is according to the electricity of CC1 or CC2 The low situation of horizontal drawing, judges the direction of insertion equipment with this.For UFP equipment, CC1 or CC2 pin can detect level quilt Drawing high, equipment draws high situation according to the level of CC1 or CC2, judges the direction of insertion equipment with this.Such as the CC1 of DFP equipment When linking the CC2 of UFP equipment, now the level of the CC1 of DFP equipment is pulled low, and the level of the CC2 of UPF equipment is driven high, right For DFP equipment, the equipment now inserted is connected to front, and for UFP equipment, the equipment now inserted is connected to instead Face.For DRP equipment, it is periodically switching between DFP and UFP pattern, when being connected to DFP equipment, can automatically cut Shake hands successfully with UFP pattern.When running into UFP equipment, can automatically shake hands successfully with DFP pattern.Communication after having switched Process is consistent with the communication process of DFP with UFP recited above.
Inventor, during realizing the present invention, finds that correlation technique there is problems in that correlation technique can only identify UPF equipment, DFP equipment, the one in DRP equipment, and fail to identify the direction of insertion equipment, thus fail to fully meet The demand of Type-C agreement.
Summary of the invention
The embodiment of the present invention is mainly solving the technical problems that provide a kind of USB Type-C interface circuit, and its solution is existing Technology also exists the technical problem of the direction of insertion that can not identify external equipment and external equipment.
For solving above-mentioned technical problem, the present invention provides techniques below scheme:
In first aspect, the embodiment of the present invention provides a kind of USB Type-C interface circuit, is used for detecting external equipment, bag Including the first signal end and secondary signal end, described USB Type-C interface circuit includes: controller, believes for output timing pulse Number；First current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described first Number end connect primary nodal point output primary nodal point voltage；Second current source circuit, itself and described controller connect, for basis Described time series pulse signals, at the secondary nodal point output secondary nodal point voltage connected with described secondary signal end；Logic circuit, its Connect with described primary nodal point, described secondary nodal point and described controller respectively, for according to described time series pulse signals, institute State primary nodal point voltage and described secondary nodal point voltage, export logic control signal；Comparison module, its input and described patrol Collecting circuit to connect, outfan and described controller connect, and for according to described logic control signal, access described primary nodal point electricity Pressure or described secondary nodal point voltage.
Alternatively, when described first signal end and described secondary signal end all do not access external equipment, described first segment The sequential of point voltage is all identical with described time series pulse signals with the sequential of described secondary nodal point voltage；Or, when described first Signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described primary nodal point voltage by High level saltus step becomes low level, and described secondary nodal point voltage keeps high level；Or, set when described first signal end accesses DFP Standby or DRP equipment, and when described time series pulse signals is low level, described primary nodal point voltage is by low transition Cheng Gao electricity Flat, described secondary nodal point voltage keeps low level；Or, when described secondary signal terminates into UFP equipment or DRP equipment, and When described time series pulse signals is high level, described secondary nodal point voltage is become low level, described primary nodal point by high level saltus step Voltage keeps high level；Or, when described secondary signal terminates into DFP equipment or DRP equipment, and described time series pulse signals During for low level, described secondary nodal point voltage is become high level by low transition, and described primary nodal point voltage keeps low level.
Alternatively, described logic control signal includes the first logic control signal and the second logic control signal；When described First signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described logic circuit is defeated Going out described first logic control signal, described comparison module, according to described first logic control signal, accesses described primary nodal point Voltage；Or, when described first signal end accesses DFP equipment or DRP equipment, and described time series pulse signals is low level Time, described logic circuit export described first logic control signal, described comparison module according to described first logic control signal, Access described primary nodal point voltage；Or, when described secondary signal terminates into UFP equipment or DRP equipment, and serial vein time described Rushing signal when being high level, described logic circuit exports the second logic control signal, and described comparison module is patrolled according to described second Collect control signal, access described secondary nodal point voltage；Or, when described secondary signal terminates into DFP equipment or DRP equipment, and And described time series pulse signals is when being low level, described logic circuit exports described second logic control signal, described compares mould Tuber, according to described second logic control signal, accesses described secondary nodal point voltage.
Alternatively, described comparison module includes: the first single-pole double-throw switch (SPDT), including the first switch input terminal, second switch Input, the first output switching terminal and the first switch control terminal, described first switch input terminal accesses described primary nodal point electricity Pressure, described second switch input accesses described secondary nodal point voltage, and described first switch control terminal accesses described logic control Signal；First comparator, its first inverting input and described first output switching terminal connect, and the first in-phase input end accesses the One Type-C normal voltage, first compares outfan exports the first level to described controller；Second comparator, it is second anti-phase Input and described first output switching terminal connect, and the second in-phase input end accesses the 2nd Type-C normal voltage, and second compares Outfan exports second electrical level to described controller；When described first level is the height persistently exported in the range of holding time Level, described time series pulse signals is maintained high level by the most described controller；When described second electrical level is at the model held time Enclosing the interior high level persistently exported, described time series pulse signals is maintained high level by the most described controller；3rd comparator, it is years old Three in-phase input ends and described first output switching terminal connect, and the 3rd inverting input accesses the 3rd Type-C normal voltage, the Three compare outfan exports the 3rd level to described controller；4th comparator, its 4th in-phase input end and described first is opened Pass outfan connects, and the 4th inverting input accesses the 4th Type-C normal voltage, and the 4th compares outfan to described controller Export the 4th level；5th comparator, its 5th in-phase input end and described first output switching terminal connect, the 5th anti-phase input Terminating into the 5th Type-C normal voltage, the 5th compares outfan exports the 5th level to described controller；When described 3rd electricity Putting down the high level for persistently exporting in the range of holding time, described time series pulse signals is maintained low electricity by the most described controller Flat；When described 4th level is the high level persistently exported in the range of holding time, and described 3rd level is in dimension Holding the low level persistently exported in the range of the time, described time series pulse signals is maintained low level by the most described controller；Work as institute Stating the 5th level is the high level persistently exported in the range of holding time, and described 4th level is to hold time In the range of the low level that persistently exports, described time series pulse signals is maintained low level by the most described controller.
Alternatively, described comparison module includes: the first single-pole double-throw switch (SPDT), including the first switch input terminal, second switch Input, the first output switching terminal and first control end, and described first switch input terminal accesses described primary nodal point voltage, institute Stating second switch input and access described secondary nodal point voltage, described first switch control terminal accesses described logic control signal； First comparator, its first in-phase input end and described first output switching terminal connect, and the first inverting input accesses first Type-C normal voltage, described first comparator according to a described Type-C normal voltage and described primary nodal point voltage or According to a described Type-C normal voltage and described secondary nodal point voltage, compare outfan from first and export to described controller First level signal；Second comparator, its second inverting input and described first output switching terminal connect, the second homophase input Terminating into the 2nd Type-C normal voltage, described second comparator is according to described 2nd Type-C normal voltage and described first segment Point voltage or according to described 2nd Type-C normal voltage and described secondary nodal point voltage, compares outfan to described from second Controller output second electrical level signal；When external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 1.23V, when described 2nd Type-C normal voltage is 0.66V, described first level signal is for hold in the range of holding time The high level of continuous output, described time series pulse signals is maintained low level by the most described controller, or, described second electrical level signal The high level persistently exported in the range of holding time, described time series pulse signals is maintained low level by the most described controller； Or, when external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 0.66V, described 2nd Type- When C normal voltage is 0.2V, described first level signal is at the interior high level persistently exported of holding time, the most described controller Described time series pulse signals is maintained low level, or, described first level signal is defeated for continuing in the range of holding time The low level gone out, and described second electrical level signal is the high level persistently exported in the range of holding time, the most described control Described time series pulse signals is maintained low level by device processed；Or, when external equipment is UFP equipment or DRP equipment, described first Type-C normal voltage is 1.6V, and when described 2nd Type-C normal voltage is 2.6V, described first level signal is to maintain The high level persistently exported in the range of time, described time series pulse signals is maintained high level by the most described controller, or, institute Stating the first level signal is the low level persistently exported in the range of holding time, and described second electrical level signal is when maintaining In persistently export high level, the most described controller by described time series pulse signals maintain high level.
In second aspect, the embodiment of the present invention provides a kind of USB Type-C interface circuit, is used for detecting external equipment, bag Including the first signal end and secondary signal end, described USB Type-C interface circuit includes: controller, believes for output timing pulse Number；First current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described first Number end connect primary nodal point output primary nodal point voltage；Second current source circuit, itself and described controller connect, for basis Described time series pulse signals, at the secondary nodal point output secondary nodal point voltage connected with described secondary signal end；Logic circuit, its Connect with described primary nodal point, described secondary nodal point and described controller respectively, for according to described primary nodal point voltage and Described secondary nodal point voltage, exports the first level signal, and described controller, according to described first level signal, exports second electrical level Signal；Comparison module, its input and described logic circuit connect, and outfan and described controller connect, for according to described Second electrical level signal, accesses described primary nodal point voltage or described secondary nodal point voltage.
Alternatively, when described first signal end and described secondary signal end all do not access external equipment, described first segment The sequential of point voltage is all identical with described time series pulse signals with the sequential of described secondary nodal point voltage；Or, when described first Signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described primary nodal point voltage by High level saltus step becomes low level, and described secondary nodal point voltage keeps high level；Or, set when described first signal end accesses DFP Standby or DRP equipment, and when described time series pulse signals is low level, described primary nodal point voltage is by low transition Cheng Gao electricity Flat, described secondary nodal point voltage keeps low level；Or, when described secondary signal terminates into UFP equipment or DRP equipment, and When described time series pulse signals is high level, described secondary nodal point voltage is become low level, described primary nodal point by high level saltus step Voltage keeps high level；Or, when described secondary signal terminates into DFP equipment or DRP equipment, and described time series pulse signals During for low level, described secondary nodal point voltage is become high level by low transition, and described primary nodal point voltage keeps low level.
Alternatively, when described first signal end accesses UFP equipment or DRP equipment, and described time series pulse signals is high During level, the first level signal of described logic circuit output is low level signal, so that the second electricity of described controller output Ordinary mail number is high level, and described comparison module is accessed primary nodal point voltage；Or, when described first signal end accesses DFP equipment or DRP equipment, and when described time series pulse signals is low level, the first level letter of described logic circuit output Number it is high level signal, so that the second electrical level signal of described controller output is high level, and described comparison module is connect Enter primary nodal point voltage；Or, when described secondary signal terminates into UFP equipment or DRP equipment, and described time series pulse signals During for high level, the first level signal of described logic circuit output is high level signal, so that the of the output of described controller Two level signals are low level, and described comparison module is accessed secondary nodal point voltage；Or, when described secondary signal terminates Enter DFP equipment or DRP equipment, and when described time series pulse signals is low level, the first level of described logic circuit output Signal is low level signal, so that the second electrical level signal of described controller output is low level, and by described comparison module Access secondary nodal point voltage.
Alternatively, described comparison module includes: the first single-pole double-throw switch (SPDT), including the first switch input terminal, second switch Input, the first output switching terminal and the first switch control terminal, described first switch input terminal accesses described primary nodal point electricity Pressure, described second switch input accesses described secondary nodal point voltage, and described first switch control terminal accesses described second electrical level Signal；First comparator, its first inverting input and described first output switching terminal connect, and the first in-phase input end accesses the One Type-C normal voltage, first compares outfan exports the 3rd level to described controller；Second comparator, it is second anti-phase Input and described first output switching terminal connect, and the second in-phase input end accesses the 2nd Type-C normal voltage, and second compares Outfan exports the 4th level to described controller；When described 3rd level is the height persistently exported in the range of holding time Level, described time series pulse signals is maintained high level by the most described controller；When described 4th level is at the model held time Enclosing the interior high level persistently exported, described time series pulse signals is maintained high level by the most described controller；3rd comparator, it is years old Three in-phase input ends and described first output switching terminal connect, and the 3rd inverting input accesses the 3rd Type-C normal voltage, the Three compare outfan exports the 5th level to described controller；4th comparator, its 4th in-phase input end and described first is opened Pass outfan connects, and the 4th inverting input accesses the 4th Type-C normal voltage, and the 4th compares outfan to described controller Export the 6th level；5th comparator, its 5th in-phase input end and described first output switching terminal connect, the 5th anti-phase input Terminating into the 5th Type-C normal voltage, the 5th compares outfan exports the 7th level to described controller；When described 5th electricity Putting down the high level for persistently exporting in the range of holding time, described time series pulse signals is maintained low electricity by the most described controller Flat；When described 6th level is the high level persistently exported in the range of holding time, and described 5th level is in dimension Holding the low level persistently exported in the range of the time, described time series pulse signals is maintained low level by the most described controller；Work as institute Stating the 7th level is the high level persistently exported in the range of holding time, and described 6th level is to hold time In the range of the low level that persistently exports, described time series pulse signals is maintained low level by the most described controller.
Alternatively, described comparison module includes: the first single-pole double-throw switch (SPDT), including the first switch input terminal, second switch Input, the first output switching terminal and the first switch control terminal, described first switch input terminal accesses described primary nodal point electricity Pressure, described second switch input accesses described secondary nodal point voltage, and described first switch control terminal accesses described second electrical level Signal；First comparator, its first in-phase input end and described first output switching terminal connect, and the first inverting input accesses the One Type-C normal voltage, described first comparator according to a described Type-C normal voltage and described primary nodal point voltage or Person, according to a described Type-C normal voltage and described secondary nodal point voltage, compares outfan from first defeated to described controller Go out three level signal；Second comparator, its second inverting input and described first output switching terminal connect, and the second homophase is defeated Entering to terminate into the 2nd Type-C normal voltage, described second comparator is according to described 2nd Type-C normal voltage and described first Node voltage or according to described 2nd Type-C normal voltage and described secondary nodal point voltage, compares outfan to institute from second State controller output the 4th level signal；When external equipment is DFP equipment or DRP equipment, a described Type-C normal voltage For 1.23V, when described 2nd Type-C normal voltage is 0.66V, described three level signal is in the range of holding time The high level persistently exported, described time series pulse signals is maintained low level by the most described controller, or, described 3rd level letter Number in the range of holding time output low level and described 4th level signal in the range of holding time continue The high level of output, described time series pulse signals is maintained low level by the most described controller；Or, when external equipment is that DFP sets Standby or DRP equipment, a described Type-C normal voltage is 0.66V, when described 2nd Type-C normal voltage is 0.2V, described Three level signal is at the interior high level persistently exported of holding time, and described time series pulse signals is maintained by the most described controller Low level, or, described three level signal is the low level persistently exported in the range of holding time, and the described 4th The high level that level signal persistently exports in the range of holding time, described time series pulse signals is maintained by the most described controller Low level；Or, when external equipment is UFP equipment or DRP equipment, and a described Type-C normal voltage is 1.6V, described When two Type-C normal voltages are 2.6V, the high level that described three level signal persistently exports in the range of holding time, Described time series pulse signals is maintained high level by the most described controller, or, described three level signal is to hold time In the range of the low level that persistently exports, described 4th level signal for hold time the interior high level that persistently exports, the most described control Described time series pulse signals is maintained high level by device processed.
In each embodiment of the present invention, when external equipment is UFP equipment or DFP equipment or DRP equipment, and access During one signal end, the first current source circuit primary nodal point export primary nodal point voltage, logic circuit according to time series pulse signals, Primary nodal point voltage and secondary nodal point voltage, export logic control signal, and comparison module accesses according to this logic control signal Primary nodal point voltage, comparison module from outfan to controller outputs level signals；When external equipment is UFP equipment or DFP sets Standby or DRP equipment, and when accessing secondary signal end, the second current source circuit exports secondary nodal point voltage at secondary nodal point, patrols Collect circuit according to time series pulse signals, primary nodal point voltage and secondary nodal point voltage, output logic control signal, comparison module According to this logic control signal access secondary nodal point voltage, comparison module from outfan to controller outputs level signals.At this During, on the one hand, this USB Type-C interface circuit can be according to the type of external equipment, and external equipment successful handshake, I.e. identifying UFP equipment or DFP equipment or DRP equipment, on the other hand, external equipment can connect the first signal the most in conversion End or secondary signal end, this USB Type-C interface circuit can timely respond in this conversion, and therefore, this USB Type-C connects Mouth circuit identifies the direction of insertion of external equipment.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of each pin definitions of USB Type-C socket under Type-C standard agreement；
Fig. 2 is the principle schematic that under Type-C standard agreement, DFP equipment communicates with UFP equipment；
Fig. 3 is the theory diagram of a kind of USB Type-C interface circuit that the embodiment of the present invention provides；
Fig. 4 is the structural representation of a kind of USB Type-C interface circuit that the embodiment of the present invention provides；
Fig. 4 a is the sequential chart that the USB Type-C interface circuit shown in Fig. 4 inserts UPF equipment；
Fig. 4 b is the sequential chart that the USB Type-C interface circuit shown in Fig. 4 inserts DPF equipment；
Fig. 5 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides；
Fig. 6 is the theory diagram of a kind of USB Type-C interface circuit that another embodiment of the present invention provides；
Fig. 7 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides；
Fig. 8 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, not For limiting the present invention.
Fig. 3 is the theory diagram of a kind of USB Type-C interface circuit that the embodiment of the present invention provides.As it is shown on figure 3, the One current source circuit 301 is connected with the first signal end CC1 and controller 302 respectively.Controller 302 output timing pulse signal SW, wherein, this time series pulse signals SW is the typical cycle that Type-C agreement specifies, concrete, and this time series pulse signals SW is The square wave of 75 milliseconds.Second current source circuit 303 is connected with secondary signal end CC2 and controller 302 respectively.First current source electricity Road 301 and the second current source circuit 303 receive the time series pulse signals SW that controller 302 sends, and the first current source simultaneously Circuit 301 is according to this time series pulse signals SW, at the primary nodal point 10A output primary nodal point electricity connected with the first signal end CC1 Pressure, the second current source circuit 303 is according to time series pulse signals SW, in the secondary nodal point 10B output connected with secondary signal end CC2 Secondary nodal point voltage.
In the present embodiment, when the first signal end CC1 and secondary signal end CC2 does not all access external equipment, first segment The sequential of point voltage is all identical with time series pulse signals SW with the sequential of secondary nodal point voltage, and the i.e. first current source circuit 301 exists When being not connected with external equipment, identical with the sequential of time series pulse signals at the primary nodal point voltage of primary nodal point 10A output, this skill Art field personnel it should be understood that no matter designer is according to which kind of the first current source circuit 301 of Type-C Protocol Design, if its When not connecing external equipment, the voltage of output is identical with time series pulse signals, the first current source circuit 301 after any replacement Should fall under the scope of the present invention.
In the present embodiment, the second current source circuit 303 and the first current source circuit 301 are symmetric circuit, its structure and Operation principle, with described in the first current source circuit 301, is not discussed in detail here.
In certain embodiments, Fig. 4 is that the structure of a kind of USB Type-C interface circuit that the embodiment of the present invention provides is shown It is intended to.As shown in Figure 4, the first current source circuit 301 includes first current source I the 1, second single-pole double-throw switch (SPDT) S2 and first Pull down resistor R1, the second single-pole double-throw switch (SPDT) S2 include the 3rd switch input terminal S21, the 4th switch input terminal S22, second switch Outfan S23 and second switch control end S24, the 3rd switch input terminal S21 and connect the first current source I1, the 4th switch input End S22 connects the first pull down resistor R1, second switch outfan S23 and connects the first signal end CC1, and second switch controls end S24 Connect with controller 302.When the first signal end CC1 does not connects external equipment, definition second switch controls end S24 and accesses high level Time series pulse signals SW time, connect the first current source I1, when accessing low level time series pulse signals SW, connect first drop-down Resistance R1.Certainly, designer controls end S24 access time series pulse signals SW according to job requirements self-defining second switch herein Implication.Clearly as the first signal end CC1 does not accesses external equipment, the therefore sequential of primary nodal point voltage and time sequential pulse Signal SW is identical, such as, when time series pulse signals SW is high level, primary nodal point voltage is high level, time series pulse signals When SW is low level, primary nodal point voltage is low level.Herein, primary nodal point 10A can be equal to second switch outfan S23, Or the first signal end CC1 can also be equal to.In design the first current source circuit 301, designer can also be to the present embodiment The first shown current source circuit 301 converts.In certain embodiments, first current source circuit 301 is according to being configured Current source, in conjunction with Type-C agreement, can export the primary nodal point voltage of different magnitude of voltage, such as, when the first current source circuit 301 current sources configured are 330uA, then primary nodal point voltage is 1.68V.When the electricity that the first current source circuit 301 is configured Stream source is 180uA, then primary nodal point voltage is 0.918V, and the current source configured when the first current source circuit 301 is 80uA, then Primary nodal point voltage is 0.408V.Wherein, current source herein is to design according to Type-C agreement, and, designer is permissible According to Type-C agreement, design the first current source circuit 301 of multiple conversion, to realize exporting not according to time series pulse signals SW Purpose with the primary nodal point voltage of magnitude of voltage.
As shown in Figure 4, the second current source circuit 303 includes the second current source I2, the 3rd single-pole double-throw switch (SPDT) S3 and Two pull down resistor R2, the 3rd single-pole double-throw switch (SPDT) S3 include the 5th switch input terminal S31, the 6th switch input terminal S32, second open Closing outfan S33 and the 3rd switch control terminal S34, the 5th switch input terminal S31 and connect the second current source I2, the 6th switch is defeated Enter to hold S32 to connect the second pull down resistor R2, second switch outfan S33 and connect secondary signal end CC2, the 3rd switch control terminal S34 and controller 302 connect.When secondary signal end CC2 does not connects external equipment, definition the 3rd switch control terminal S34 accesses height During the time series pulse signals SW of level, connect the second current source I2, when accessing low level time series pulse signals SW, connect second Pull down resistor R2.
In the present embodiment, when the first signal end CC1 accesses UFP equipment or DRP equipment, and time series pulse signals SW is During high level, incorporated by reference to Fig. 2, due to the effect of the pull down resistor Rd1 of UFP equipment or DRP equipment, by the first signal end CC1 Primary nodal point voltage pull-down, therefore, primary nodal point voltage is become low level by high level saltus step, due to secondary signal end CC2 not Accessing external equipment, therefore, secondary nodal point voltage keeps high level.Herein, UFP equipment or DRP are accessed as the first signal end CC1 Equipment, and when time series pulse signals SW is low level, USB Type-C interface will not be with external equipment successful connection.
In certain embodiments, refer again to Fig. 2 and Fig. 4, when the first signal end CC1 accesses UFP equipment or DRP equipment, And when time series pulse signals SW is high level, the second single-pole double-throw switch (SPDT) S2 connects the first current source I1, due to UFP equipment or The effect of the pull down resistor Rd1 of person's DRP equipment, by the primary nodal point voltage pull-down of the first signal end CC1, therefore, primary nodal point Voltage is become low level by high level saltus step.Owing to secondary signal end CC2 does not accesses external equipment, and the 3rd single-pole double-throw switch (SPDT) S3 connects the second current source I2, and therefore, secondary nodal point voltage keeps high level.
In the present embodiment, when the first signal end CC1 accesses DFP equipment or DRP equipment, and time series pulse signals SW is During low level, please in conjunction with Fig. 2, due to DFU equipment or the voltage source of DRP equipment or the effect of current source, relatively, its Can be with the voltage of lifting primary nodal point 10A, therefore primary nodal point voltage is become high level by low transition.Due to secondary signal end CC2 does not accesses external equipment, and therefore, secondary nodal point voltage keeps low level.Herein, DFP equipment is accessed as the first signal end CC1 Or DRP equipment, and when time series pulse signals SW is high level, USB Type-C interface will not be with external equipment successful connection. Certainly, the present embodiment is merely given as connecting a kind of connection during external equipment about time series pulse signals and USB Type-C interface System, designer can be according to job requirements, the content instructed and guided in conjunction with the present invention, the various implementation of self-defining, at this also It is not limited to the present embodiment.
In some embodiments, refer again to Fig. 2 and Fig. 4, when the first signal end CC1 accesses DFP equipment or DRP equipment, and And time series pulse signals SW is when being low level, the second single-pole double-throw switch (SPDT) S2 connects the first current source I1, due to DFP equipment or The voltage source of DRP equipment or the effect of current source, by the primary nodal point voltage lifting of the first signal end CC1, therefore, first segment Point voltage is become high level by low transition.Owing to secondary signal end CC2 does not accesses external equipment, and the 3rd single-pole double throw is opened Closing S3 and connect the second pull down resistor R2, therefore, secondary nodal point voltage keeps low level.
In the present embodiment, based on above-mentioned reason, when secondary signal end CC2 accesses UFP equipment or DRP equipment, and And time series pulse signals SW is when being high level, secondary nodal point voltage is become low level by high level saltus step, and primary nodal point voltage keeps High level.When secondary signal end CC2 accesses DFP equipment or DRP equipment, and when time series pulse signals SW is low level, second Node voltage is become high level by low transition, and primary nodal point voltage keeps low level.
In the present embodiment, logic circuit 304 is respectively with primary nodal point 10A, secondary nodal point 10B and controller 302 even Connect, according to time series pulse signals SW, primary nodal point voltage and secondary nodal point voltage, export logic control signal.USB Type- When C interface circuit connects external equipment, this logic circuit 304 can be by time series pulse signals SW, primary nodal point voltage and the Two node voltages carry out logical operations, finally give logic control signal, and wherein, this logic control signal compares mould for control Block 305, makes comparison module 305 have access to primary nodal point voltage or secondary nodal point voltage, wherein, and comparison module 305 defeated Entering end and logic circuit 304 connects, outfan and controller 302 connect.In this process, on the one hand, this USB Type-C connects Mouthful circuit can be according to the type of external equipment, and external equipment successful handshake i.e. identifies UFP equipment or DFP equipment or DRP Equipment, on the other hand, external equipment can connect the first signal end or secondary signal end the most in conversion, this USB Type-C Interface circuit can timely respond in this conversion, and therefore, this USB Type-C interface circuit identifies the insertion side of external equipment To.
In certain embodiments, this logic control signal includes the first logic control signal and the second logic control signal. When the first signal end CC1 accesses UFP equipment or DRP equipment, and when time series pulse signals SW is high level, logic circuit exports First logic control signal, comparison module, according to the first logic control signal, accesses primary nodal point voltage.
When the first signal end CC1 accesses DFP equipment or DRP equipment, and when time series pulse signals SW is low level, logic Circuit exports the first logic control signal, and comparison module, according to the first logic control signal, accesses primary nodal point voltage.
Therefore, when external equipment accesses the first signal end CC1, the first current source circuit 301 is in primary nodal point 10A output the One node voltage, no matter which kind of type this external equipment is, the first logic control signal that logic circuit 304 produces all ensures this Primary nodal point voltage accesses comparison module 305, and is produced the most defeated by comparison module 305 according to the primary nodal point voltage accessed Go out to controller 302.
In like manner can obtain, when secondary signal end CC2 accesses UFP equipment or DRP equipment, and time series pulse signals SW is high electricity At ordinary times, logic circuit 304 exports the second logic control signal, and comparison module 305, according to the second logic control signal, accesses second Node voltage.
When secondary signal terminates into DFP equipment or DRP equipment, and when time series pulse signals SW is low level, logic electricity Road 304 exports the second logic control signal, and comparison module 305, according to the second logic control signal, accesses secondary nodal point voltage.
Therefore, when external equipment accesses secondary signal end CC2, the second current source circuit 303 is in secondary nodal point 10B output the Two node voltages, no matter which kind of type this external equipment is, the second logic control signal that logic circuit 304 produces all ensures this Secondary nodal point voltage accesses comparison module 305, and is produced the most defeated by comparison module 305 according to the secondary nodal point voltage accessed Go out to controller 302.
In the present embodiment, logic circuit 304 can be made up of multiple logical devices, such as, with or gate logic device, non- Gate device and etc. device composition, logic circuit 304 can also is that logic chip and other there is the circuit of logical operations, No matter use the logic circuit of which kind of logical device composition, or logic chip and etc., instructed and guided according to the present embodiment Content, as long as the logic control signal of output is capable of the object of the invention.
Refer again to Fig. 4, logic circuit 304 includes the 6th comparator 3041 and NOR gate circuit 3042, the 6th comparator 6th inverting input of 3041 accesses secondary nodal point 10B, and the 6th in-phase input end accesses primary nodal point 10A, and the 6th is the most defeated Going out to hold OUT6 to access the first XOR input of NOR gate circuit 3042, the second XOR input accesses time series pulse signals SW, XOR outfan DIR and comparison module 305 connect.
When the first signal end CC1 access UFP equipment or DRP equipment, when time series pulse signals SW is high level, now, Primary nodal point voltage is less than secondary nodal point voltage, and therefore, the 6th output level comparing outfan OUT6 is low level, and XOR is defeated The output level going out to hold DIR is high level, and therefore comparison module 305 is according to the logic control signal of this high level, accesses first Node voltage.
When the first signal end CC1 accesses DFP equipment or DRP equipment, when time series pulse signals SW is low level, in like manner may be used , the 6th output level comparing outfan OUT6 is high level, and the output level of XOR outfan DIR is high level, therefore Comparison module 305, according to the logic control signal of this high level, accesses primary nodal point voltage.
When secondary signal end CC2 access UFP equipment or DRP equipment, when time series pulse signals SW is high level, now, Secondary nodal point voltage is less than primary nodal point voltage, and therefore, the 6th output level comparing outfan OUT6 is high level, and XOR is defeated The output level going out to hold DIR is low level, and therefore comparison module 305 is according to this low level logic control signal, accesses second Node voltage.
When secondary signal end CC2 accesses DFP equipment or DRP equipment, when time series pulse signals SW is low level, in like manner may be used , the 6th output level comparing outfan OUT6 is low level, and the output level of XOR outfan DIR is low level, therefore Comparison module 305, according to this low level logic control signal, accesses secondary nodal point voltage.
Refer again to Fig. 4, comparison module 305 includes the first single-pole double-throw switch (SPDT) S1, the first comparator U1, the second comparator U2, the 3rd comparator U3, the 4th comparator U4 and the 5th comparator U5.First single-pole double-throw switch (SPDT) S1 includes that the first switch is defeated Enter to hold S11, second switch input S12, the first output switching terminal S13 and the first switch control terminal S14, the first switch input End S11 accesses primary nodal point voltage, and second switch input S12 accesses secondary nodal point voltage, and the first switch control terminal S14 accesses Logic control signal.
First inverting input of the first comparator U1 and the first output switching terminal S13 connect, and the first in-phase input end connects Entering Type-C normal voltage V1, first compares outfan exports the first level to controller 302.Herein, a Type-C Normal voltage V1 is the voltage threshold of the charging current of DFP equipment 3A, and the occurrence of Type-C normal voltage V1 is 2.6V.
Second inverting input of the second comparator U2 and the first output switching terminal S13 connect, and the second in-phase input end connects Entering the 2nd Type-C normal voltage V2, second compares outfan exports second electrical level to controller 302.Herein, the 2nd Type-C Normal voltage V2 is the voltage threshold of the charging current of DFP equipment acquiescence, and the occurrence of the 2nd Type-C normal voltage V2 is 1.6V。
In the present embodiment, the current source that the first current source circuit 301 or the second current source circuit 303 are configured is 330 μ A, the first signal end CC1 or secondary signal end CC2 access UFP equipment or during DRP equipment, primary nodal point voltage now or Secondary nodal point voltage is 1.68V (330 μ A*5.1K), and wherein, 5.1K is the first pull down resistor or the resistance of the second pull down resistor. When the first level is at the t that holds timeCCDEBOUNCEIn the range of the high level that persistently exports, then equipment successful connection, therefore, control Time series pulse signals SW is maintained high level output by device 302 processed.
When the current source configured is 80 μ A or 180 μ A, when second electrical level is at the t that holds timeCCDEBOUNCEModel Enclosing the interior high level persistently exported, then equipment successful connection, time series pulse signals SW is maintained high level output by controller 302. Herein, hold time tCCDEBOUNCEIt is the time threshold being successfully connected between the equipment that specifies of Type-C agreement, holds time tCCDEBOUNCEGenerally 150ms.
Controller 302 knows to export how many electric currents by analyzing the level of the first comparator U1 output, therefore, and this The USB Type-C interface circuit that embodiment provides has and identifies corresponding broadcast current ability.
3rd in-phase input end of the 3rd comparator U3 and the first output switching terminal connect, and the 3rd inverting input accesses the Three Type-C normal voltages V3, the 3rd compares outfan exports the 3rd level to controller 302.Herein, the 3rd Type-C standard Voltage V3 is the UFP equipment Inspection voltage threshold to 3A charging current, and the occurrence of the 3rd Type-C normal voltage V3 is 1.23V。
4th in-phase input end of the 4th comparator U4 and the first output switching terminal connect, and the 4th inverting input accesses the Four Type-C normal voltages V4, the 4th compares outfan exports the 4th level to described controller.Herein, the 4th Type-C standard Voltage V4 is the UFP equipment Inspection voltage threshold to 1.5A charging current, and the occurrence of the 4th Type-C normal voltage V4 is 0.66V。
5th in-phase input end of the 5th comparator U5 and the first output switching terminal connect, and the 5th inverting input accesses the Five Type-C normal voltages V5, the 5th compares outfan exports the 5th level to controller.Herein, the 5th Type-C normal voltage V5 is the UFP equipment Inspection voltage threshold to 0.5A charging current, and the occurrence of the 5th Type-C normal voltage V5 is 0.2V.
In the present embodiment, the first signal end CC1 or secondary signal end CC2 accesses DFP equipment or DRP equipment, and And the current source of DFP equipment or DRP equipment is when being configured to 330 μ A, primary nodal point voltage or secondary nodal point voltage now are 1.68V (330 μ A*5.1K), wherein, the resistance that 5.1K is configured according to Type-C agreement by DFP equipment or DRP equipment.When 3rd level is at the t that holds timeCCDEBOUNCEIn the range of the high level that persistently exports, then equipment successful connection, DFP equipment or The electric current that person's DRP equipment can export is 3A, and time series pulse signals SW is maintained low level by controller 302.
When the current source of DFP equipment or DRP equipment is configured to 180 μ A, the 4th level is for hold time tCCDEBOUNCEIn the range of the high level that persistently exports, and the 3rd level is at the t that holds timeCCDEBOUNCEIn the range of continue The low level of output, then equipment successful connection, the electric current that DFP equipment or DRP equipment can export is 1.5A, controller 302 Time series pulse signals SW is maintained low level.
When the current source of DFP equipment or DRP equipment is configured to 80 μ A, the 5th level is at the t that holds timeCCDEBOUNCE In the range of the high level that persistently exports, and the 4th level is at the t that holds timeCCDEBOUNCEIn the range of persistently export low The electric current that level, then equipment successful connection, DFP equipment or DRP equipment can export is 0.5A, controller 302 by time serial vein Rush signal SW and maintain low level.
Controller 302 is by the level of analysis the 3rd comparator U3 or the 4th comparator U4 or the 5th comparator U5 output Know and can get how much current from DFP equipment or DRP equipment, therefore, the USB Type-C interface that the present embodiment provides Circuit has and identifies corresponding broadcast current ability.
Below with the first signal end CC1 access UPF equipment as example, the present embodiment USB Type-C interface electricity is discussed in detail The operation principle on road.
Fig. 4 a is the sequential chart that the USB Type-C interface circuit shown in Fig. 4 inserts UPF equipment.Incorporated by reference to Fig. 4 and Fig. 4 a, Before t1, the first signal end CC1 of USB Type-C interface circuit not yet accesses UPF equipment, due to the first signal end CC1 and Always, therefore, when SW is high level, CC1 and CC2 is high electricity for the sequential of secondary signal end CC2 and time series pulse signals SW Flat, when SW is low level, CC1 and CC2 is low level.If the level that the level of CC1 is higher than CC2, before t1, OUT6 Signal be high level (if the level of CC1 is less than the level of CC2, then before t1, the signal of OUT6 is low level). DIR signal is the XOR gate output of OUT6 signal and SW, and therefore, before t1, the signal of DIR is contrary with the signal logic of SW, When SW is high level, DIR is low level, and when SW signal is low level, DIR signal is high level.Before t1, work as DIR During for high level, CC signal links CC1, owing to now CC1 is low level, and therefore output signal OUT1 and of the first comparator Two comparator OUT2 are output as low level, and when DIR signal is low level, CC signal links CC2, are now high due to CC2 Level, therefore output signal OUT1 and the second comparator OUT2 of the first comparator is output as high level.
In the t1 moment, it is assumed that inserting UPF equipment at the first signal end CC1, now SW is high level, and the first current source flows through The pull down resistor of UFP equipment, drags down the level of the first signal end CC1, now connects due to CC line and the first signal end CC1, I.e. primary nodal point voltage accesses comparison module, and the level of CC is pulled low, therefore output signal OUT1 and second of the first comparator The output of comparator OUT2 jumps to low level from high level, and equipment successful connection is described, now SW signal level no longer becomes Change, continue to keep high level.Secondary signal end CC2, owing to not having equipment to insert, continues to keep high level.The now level of CC2 Higher than CC1, therefore OUT6 signal step-down.DIR signal be OUT6 signal be the XOR output of SW signal, now saltus step be high electric Flat.
The most again with the first signal end CC1 access DPF equipment as example, the present embodiment USB Type-C interface is discussed in detail The operation principle of circuit.
Fig. 4 b is the sequential chart that the USB Type-C interface circuit shown in Fig. 4 inserts DPF equipment.Incorporated by reference to Fig. 4 and Fig. 4 b, Before t1, not having equipment to insert, CC1 and CC2 is controlled by SW signal, and sequential is consistent with SW, when SW is high level, and CC1 Being all high level with CC2, when SW is low level, CC1 and CC2 is low level.If the level that the level of CC1 is higher than CC2, So before t1, the signal of OUT6 be high level (if the level of CC1 is less than the level of CC2, then before t1, OUT6 Signal be low level).DIR signal is the XOR gate output of OUT6 signal and SW, so before t1, the signal of DIR and SW Signal logic contrary, when SW is high level, DIR is low level, and when SW signal is low level, DIR signal is high level. Before t1, when DIR is high level, CC signal links CC1, owing to now CC1 is low level, so the 3rd comparator output OUT3, the 4th comparator output OUT4 and the 5th comparator output OUT5 be low level.When DIR signal is low electricity At ordinary times, CC signal links CC2, is now high level due to CC2, so OUT3, the output of OUT4, OUT5 is high level.
In the t1 moment, it is assumed that have DFP equipment to insert at CC1 port, now SW is low level, and CC1 port passes through Rd1 resistance Ground connection, owing to there being DFP equipment to insert, therefore the current source of DFP equipment will flow through the resistance of Rd1, is lifted by the level of CC1 port Height, this level raised and the 3rd comparator, the reference voltage of the 4th comparator and the 5th comparator compares, when OUT3's Level is high and continues tCCDEBOUNCETime, equipment successful connection is described, and identifies the broadcast current ability of DFP equipment For 3A.When the level of OUT4 is high and continues tCCDEBOUNCETime, equipment successful connection is described, and identifies DFP equipment Broadcast current ability be 1.5A.When the level of OUT5 is high and continues tCCDEBOUNCETime, equipment successful connection is described, and And the broadcast current ability identifying DFP equipment is 0.5A.Equipment successful connection, now SW signal level no longer changes, Continue to keep low level.The port of CC2, owing to not having equipment to insert, continues to low level.Now the level of CC1 is higher than CC2, So OUT6 signal is high.DIR signal be OUT6 signal be SW signal XOR output, now saltus step is high level.
In like manner can obtain, operation principle during secondary signal end CC2 access UFP or DFP equipment is same as above, does not goes to live in the household of one's in-laws on getting married at this State.
In the present embodiment, on the one hand, this USB Type-C interface circuit can be according to the type of external equipment and external Equipment successful handshake, i.e. identifies UFP equipment or DFP equipment or DRP equipment, and on the other hand, external equipment can arbitrarily convert Ground connects the first signal end or secondary signal end, and this USB Type-C interface circuit can timely respond in this conversion, therefore, This USB Type-C interface circuit identifies the direction of insertion of external equipment.
Fig. 5 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides.Such as Fig. 5 institute Showing, the difference of the present embodiment and above-described embodiment is, the comparison module 50 of the present embodiment includes the first single-pole double-throw switch (SPDT) S1, the first comparator 501 and the second comparator 502.
First single-pole double-throw switch (SPDT) S1 includes that the first switch input terminal S11, second switch input S12, the first switch are defeated Go out to hold S13 and first to control end S14, the first switch input terminal S11 and access primary nodal point voltage, second switch input S12 Accessing secondary nodal point voltage, the first switch control terminal S14 accesses logic control signal.
First in-phase input end of the first comparator 501 and the first output switching terminal S13 connect, the first anti-phase input termination Enter Type-C normal voltage V1, the first comparator 501 according to Type-C normal voltage V1 and primary nodal point voltage or Person, according to Type-C normal voltage V1 and secondary nodal point voltage, compares outfan from first and exports the first level to controller Signal.
Second inverting input of the second comparator 502 and the first output switching terminal S13 connect, and the second in-phase input end connects Enter the 2nd Type-C normal voltage V2, the second comparator 502 according to the 2nd Type-C normal voltage and primary nodal point voltage or According to the 2nd Type-C normal voltage and secondary nodal point voltage, compare outfan to controller output second electrical level letter from second Number.
When external equipment is DFP equipment or DRP equipment, and a Type-C normal voltage is 1.23V, the 2nd Type-C standard When voltage is 0.66V, the first level signal is at the t that holds timeCCDEBOUNCEIn the range of the high level that persistently exports, then equipment The electric current that successful connection, DFP equipment or DRP equipment can export is 3A, and time series pulse signals is maintained low level by controller, Or, the first level signal is at the t that holds timeCCDEBOUNCEIn the range of output low level, second electrical level signal maintain time Between tCCDEBOUNCEIn the range of the high level that persistently exports, then equipment successful connection, DFP equipment or DRP equipment can export Electric current be 1.5A, time series pulse signals is maintained low level by controller.
When external equipment is DFP equipment or DRP equipment, and a Type-C normal voltage is 0.66V, the 2nd Type-C standard When voltage is 0.2V, the first level signal is at the t that holds timeCCDEBOUNCEThe high level the most persistently exported, then equipment connects into Merit, time series pulse signals is maintained low level by controller, or, the first level signal is at the t that holds timeCCDEBOUNCEScope The low level the most persistently exported, and second electrical level signal is at the t that holds timeCCDEBOUNCEIn the range of the high electricity that persistently exports Flat, then equipment successful connection, the electric current that DFP equipment or DRP equipment can export is 0.5A, and controller is by time series pulse signals Maintain low level.
When external equipment is UFP equipment or DRP equipment, and a Type-C normal voltage is 1.6V, the 2nd Type-C standard When voltage is 2.6V, the first level signal is at the t that holds timeCCDEBOUNCEIn the range of the high level that persistently exports, the second electricity Ordinary mail number is for hold time the interior high level that persistently exports, then equipment successful connection, time series pulse signals is maintained height by controller Level, and illustrate that electric current broadcast-capable now is 1.5A or 0.5AA, or, the first level signal is for hold time tCCDEBOUNCEIn the range of the low level that persistently exports, second electrical level signal is at the t that holds timeCCDEBOUNCEIn the range of continue the most defeated Going out high level, then equipment successful connection, time series pulse signals is maintained high level by controller, and electric current broadcast now is described Ability is 3AA.If the first level signal is low, second electrical level signal is also low, then explanation does not has equipment to insert, and connects not become Merit.
The USB Type-C interface circuit that the present embodiment provides can not only identify type and the insertion side of external equipment To, and also can interpolate that out corresponding broadcast current ability.
Fig. 6 is the theory diagram of a kind of USB Type-C interface circuit that another embodiment of the present invention provides.Such as Fig. 6 institute Showing, the difference of the present embodiment and first embodiment is: the logic control signal of logic circuit output is not directly to control to compare Module accesses primary nodal point voltage or secondary nodal point voltage, but logic circuit produces the first level signal, and controller Receive this first level signal, and export second electrical level signal according to this first level signal, in order to control comparison module and connect Enter primary nodal point voltage or secondary nodal point voltage.
Concrete, the first current source circuit 601 is connected with the first signal end CC1 and controller 602 respectively.Controller 602 Output timing pulse signal SW, wherein, this time series pulse signals SW is the typical cycle that Type-C agreement specifies, concrete, should Time series pulse signals SW is the square wave of 75 milliseconds.Second current source circuit 603 respectively with secondary signal end CC2 and controller 602 Connect.First current source circuit 601 and the second current source circuit 603 receive the time series pulse signals that controller 602 sends simultaneously SW, and the first current source circuit 601 is according to this time series pulse signals SW, at the primary nodal point connected with the first signal end CC1 10A exports primary nodal point voltage, and the second current source circuit 603, according to time series pulse signals SW, is connecting with secondary signal end CC2 Secondary nodal point 10B export secondary nodal point voltage.
When the first signal end CC1 and secondary signal end CC2 does not all access external equipment, the sequential of primary nodal point voltage and The sequential of secondary nodal point voltage is all identical with time series pulse signals.When the first signal end CC1 accesses UFP equipment or DRP equipment, and And time series pulse signals is when being high level, primary nodal point voltage is become low level by high level saltus step, and secondary nodal point voltage keeps height Level.When the first signal end CC1 accesses DFP equipment or DRP equipment, and when time series pulse signals is low level, primary nodal point Voltage is become high level by low transition, and secondary nodal point voltage keeps low level.When secondary signal end CC2 access UFP equipment or DRP equipment, and when time series pulse signals is high level, secondary nodal point voltage is become low level, primary nodal point by high level saltus step Voltage keeps high level.When secondary signal end CC2 accesses DFP equipment or DRP equipment, and time series pulse signals is low level Time, secondary nodal point voltage is become high level by low transition, and primary nodal point voltage keeps low level.
Logic circuit 604 connects with primary nodal point, secondary nodal point and controller 602 respectively, for according to primary nodal point Voltage and secondary nodal point voltage, export the first level signal, and controller 602 is according to the first level signal, output second electrical level letter Number.
Input and the logic circuit 604 of comparison module 605 connect, and outfan and controller 602 connect, for according to the Two level signals, access primary nodal point voltage or secondary nodal point voltage.In this process, on the one hand, this USB Type-C connects Mouthful circuit can be according to the type of external equipment, and external equipment successful handshake i.e. identifies UFP equipment or DFP equipment or DRP Equipment, on the other hand, external equipment can connect the first signal end or secondary signal end the most in conversion, this USB Type-C Interface circuit can timely respond in this conversion, and therefore, this USB Type-C interface circuit identifies the insertion side of external equipment To.
When the first signal end CC1 accesses UFP equipment or DRP equipment, and when time series pulse signals SW is high level, logic First level signal of circuit 604 output is low level signal, so that the second electrical level signal of controller 602 output is high electricity Flat, and comparison module 605 is accessed primary nodal point voltage.
When the first signal end CC1 accesses DFP equipment or DRP equipment, and when time series pulse signals SW is low level, logic First level signal of circuit 604 output is high level signal, so that the second electrical level signal of controller 602 output is high electricity Flat, and comparison module 605 is accessed primary nodal point voltage.
When secondary signal end CC2 accesses UFP equipment or DRP equipment, and when time series pulse signals SW is high level, logic First level signal of circuit 604 output is high level signal, so that the second electrical level signal of controller 602 output is low electricity Flat, and comparison module 605 is accessed secondary nodal point voltage.
When secondary signal end CC2 accesses DFP equipment or DRP equipment, and when time series pulse signals SW is low level, logic First level signal of circuit 604 output is low level signal, so that the second electrical level signal of controller 602 output is low electricity Flat, and comparison module 605 is accessed secondary nodal point voltage.
Fig. 7 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides.Such as Fig. 7 institute Show, comparison module 605 include the first single-pole double-throw switch (SPDT) S1, the first comparator U1, the second comparator U2, the 3rd comparator U3, 4th comparator U4 and the 5th comparator U5.
First single-pole double-throw switch (SPDT) S1 include the first switch input terminal, second switch input, the first output switching terminal with And first switch control terminal, the first switch input terminal accesses primary nodal point voltage, and described second switch input accesses second section Point voltage, the first switch control terminal accesses second electrical level signal.
First inverting input of the first comparator U1 and the first output switching terminal connect, and the first in-phase input end accesses the One Type-C normal voltage, first compares outfan exports the 3rd level to controller 602.
Second inverting input and described first output switching terminal of the second comparator U2 connect, and the second in-phase input end connects Entering the 2nd Type-C normal voltage, second compares outfan exports the 4th level to controller 602.
When the 3rd level is the high level persistently exported in the range of holding time, then controller 602 is by time sequential pulse Signal maintains high level；When the 4th level is the high level persistently exported in the range of holding time, then controller 602 by time Sequence pulse signal maintains high level.
3rd in-phase input end of the 3rd comparator U3 and the first output switching terminal connect, and the 3rd inverting input accesses the Three Type-C normal voltages, the 3rd compares outfan exports the 5th level to controller 602.
4th in-phase input end of the 4th comparator U4 and the first output switching terminal connect, and the 4th inverting input accesses the Four Type-C normal voltages, the 4th compares outfan exports the 6th level to controller 602.
5th in-phase input end of the 5th comparator U5 and the first output switching terminal connect, and the 5th inverting input accesses the Five Type-C normal voltages, the 5th compares outfan exports the 7th level to controller 602.
When the 5th level is the high level persistently exported in the range of holding time, then controller 602 is by time sequential pulse Signal maintains low level.When the 6th level is the high level persistently exported in the range of holding time, and the 5th level is The low level persistently exported in the range of holding time, then time series pulse signals is maintained low level by controller 602；When the 7th Level is the high level persistently exported in the range of holding time, and the 6th level is for continuing in the range of holding time The low level of output, then time series pulse signals is maintained low level by controller 602.
In the present embodiment, on the one hand, this USB Type-C interface circuit can be according to the type of external equipment and external Equipment successful handshake, i.e. identifies UFP equipment or DFP equipment or DRP equipment, and on the other hand, external equipment can arbitrarily convert Ground connects the first signal end or secondary signal end, and this USB Type-C interface circuit can timely respond in this conversion, therefore, This USB Type-C interface circuit identifies the direction of insertion of external equipment.
Fig. 8 is the structural representation of a kind of USB Type-C interface circuit that another embodiment of the present invention provides.Such as Fig. 8 institute Showing, the difference of the present embodiment and above-described embodiment is, the present embodiment comparison module 80 include the first single-pole double-throw switch (SPDT) S1, First comparator 801 and the second comparator 802.
In the present embodiment, the first single-pole double-throw switch (SPDT) S1 include the first switch input terminal, second switch input, first Output switching terminal and the first switch control terminal, the first switch input terminal accesses primary nodal point voltage, second switch input termination Entering secondary nodal point voltage, the first switch control terminal accesses second electrical level signal.
In the present embodiment, the first in-phase input end of the first comparator 801 and the first output switching terminal connect, and first is anti- Phase input accesses a Type-C normal voltage, and the first comparator is according to a Type-C normal voltage and primary nodal point voltage Or according to a Type-C normal voltage and secondary nodal point voltage, compare outfan from first and export the 3rd level to controller Signal.
Second inverting input of the second comparator 802 and the first output switching terminal connect, and the second in-phase input end accesses 2nd Type-C normal voltage, the second comparator is according to the 2nd Type-C normal voltage and primary nodal point voltage or according to second Type-C normal voltage and secondary nodal point voltage, compare outfan from second and export the 4th level signal to controller.
When external equipment is DFP equipment or DRP equipment, and a Type-C normal voltage is 1.23V, the 2nd Type-C standard When voltage is 0.66V, three level signal is the high level persistently exported in the range of holding time, then controller is by sequential Pulse signal maintain low level, or, three level signal be in the range of holding time output low level and the 4th electricity Ordinary mail number is the high level persistently exported in the range of holding time, then described time series pulse signals is maintained low electricity by controller Flat.
When external equipment is DFP equipment or DRP equipment, and a Type-C normal voltage is 0.66V, the 2nd Type-C standard When voltage is 0.2V, three level signal is at the interior high level persistently exported of holding time, then controller is by serial vein time described Rush signal and maintain low level, or, three level signal is the low level persistently exported in the range of holding time, and the The high level that four level signals persistently export in the range of holding time, then time series pulse signals is maintained low electricity by controller Flat.
When external equipment is UFP equipment or DRP equipment, and a described Type-C normal voltage is 1.6V, described second When Type-C normal voltage is 2.6V, the high level that described three level signal persistently exports in the range of holding time, then Described time series pulse signals is maintained high level by described controller, or, described three level signal is at the model held time Enclose the interior low level persistently exported, described 4th level signal for hold time the interior high level that persistently exports, the most described control Described time series pulse signals is maintained high level by device.
In the present embodiment, on the one hand, this USB Type-C interface circuit can be according to the type of external equipment and external Equipment successful handshake, i.e. identifies UFP equipment or DFP equipment or DRP equipment, and on the other hand, external equipment can arbitrarily convert Ground connects the first signal end or secondary signal end, and this USB Type-C interface circuit can timely respond in this conversion, therefore, This USB Type-C interface circuit identifies the direction of insertion of external equipment.
In various embodiments, controller can be general processor, digital signal processor (DSP), special integrated electricity Road (ASIC), field programmable gate array (FPGA) or other PLD, discrete gate or transistor logic, discrete Nextport hardware component NextPort or any combination of these parts.Further, controller herein can be any conventional processors, micro-process Device, microcontroller or state machine.Processor can also be implemented as the combination of calculating equipment, such as, DSP and the group of microprocessor Conjunction, multi-microprocessor, one or more microprocessor combine DSP core or other this configuration any.
The foregoing is only embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization is originally Equivalent structure or equivalence flow process that description of the invention and accompanying drawing content are made convert, or are directly or indirectly used in what other were correlated with Technical field, is the most in like manner included in the scope of patent protection of the present invention.

Claims (10)

1. a USB Type-C interface circuit, is used for detecting external equipment, and including the first signal end and secondary signal end, it is special Levy and be, including:
Controller, for output timing pulse signal；
First current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described first Number end connect primary nodal point output primary nodal point voltage；
Second current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described second Number end connect secondary nodal point output secondary nodal point voltage；
Logic circuit, it connects with described primary nodal point, described secondary nodal point and described controller respectively, for according to described Time series pulse signals, described primary nodal point voltage and described secondary nodal point voltage, export logic control signal；
Comparison module, its input and described logic circuit connect, and outfan and described controller connect, for patrolling described in basis Collect control signal, access described primary nodal point voltage or described secondary nodal point voltage.
USB Type-C interface circuit the most according to claim 1, it is characterised in that
When described first signal end and described secondary signal end all do not access external equipment, the sequential of described primary nodal point voltage All identical with described time series pulse signals with the sequential of described secondary nodal point voltage；Or,
When described first signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Primary nodal point voltage is become low level by high level saltus step, and described secondary nodal point voltage keeps high level；Or,
When described first signal end accesses DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Primary nodal point voltage is become high level by low transition, and described secondary nodal point voltage keeps low level；Or,
When described secondary signal terminates into UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Secondary nodal point voltage is become low level by high level saltus step, and described primary nodal point voltage keeps high level；Or,
When described secondary signal terminates into DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Secondary nodal point voltage is become high level by low transition, and described primary nodal point voltage keeps low level.
USB Type-C interface circuit the most according to claim 2, it is characterised in that described logic control signal includes One logic control signal and the second logic control signal；
When described first signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Logic circuit exports described first logic control signal, and described comparison module, according to described first logic control signal, accesses institute State primary nodal point voltage；Or,
When described first signal end accesses DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Logic circuit exports described first logic control signal, and described comparison module, according to described first logic control signal, accesses institute State primary nodal point voltage；Or,
When described secondary signal terminates into UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Logic circuit exports the second logic control signal, and described comparison module, according to described second logic control signal, accesses described Two node voltages；Or,
When described secondary signal terminates into DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Logic circuit exports described second logic control signal, and described comparison module, according to described second logic control signal, accesses institute State secondary nodal point voltage.
USB Type-C interface circuit the most according to claim 3, it is characterised in that described comparison module includes:
First single-pole double-throw switch (SPDT), including the first switch input terminal, second switch input, the first output switching terminal and first Switch control terminal, described first switch input terminal accesses described primary nodal point voltage, and described second switch input accesses described Secondary nodal point voltage, described first switch control terminal accesses described logic control signal；
First comparator, its first inverting input and described first output switching terminal connect, and the first in-phase input end accesses the One Type-C normal voltage, first compares outfan exports the first level to described controller；
Second comparator, its second inverting input and described first output switching terminal connect, and the second in-phase input end accesses the Two Type-C normal voltages, second compares outfan exports second electrical level to described controller；When described first level is in dimension Holding the high level persistently exported in the range of the time, described time series pulse signals is maintained high level by the most described controller；Work as institute Stating second electrical level is the high level persistently exported in the range of holding time, and the most described controller is by described time series pulse signals Maintain high level；
3rd comparator, its 3rd in-phase input end and described first output switching terminal connect, and the 3rd inverting input accesses the Three Type-C normal voltages, the 3rd compares outfan exports the 3rd level to described controller；
4th comparator, its 4th in-phase input end and described first output switching terminal connect, and the 4th inverting input accesses the Four Type-C normal voltages, the 4th compares outfan exports the 4th level to described controller；
5th comparator, its 5th in-phase input end and described first output switching terminal connect, and the 5th inverting input accesses the Five Type-C normal voltages, the 5th compares outfan exports the 5th level to described controller；When described 3rd level is in dimension Holding the high level persistently exported in the range of the time, described time series pulse signals is maintained low level by the most described controller；Work as institute Stating the 4th level is the high level persistently exported in the range of holding time, and described 3rd level is to hold time In the range of the low level that persistently exports, described time series pulse signals is maintained low level by the most described controller；When described 5th electricity Put down the high level for persistently exporting in the range of holding time, and described 4th level is for hold in the range of holding time The low level of continuous output, described time series pulse signals is maintained low level by the most described controller.
USB Type-C interface circuit the most according to claim 3, it is characterised in that described comparison module includes:
First single-pole double-throw switch (SPDT), including the first switch input terminal, second switch input, the first output switching terminal and first Controlling end, described first switch input terminal accesses described primary nodal point voltage, and described second switch input accesses described second Node voltage, described first switch control terminal accesses described logic control signal；
First comparator, its first in-phase input end and described first output switching terminal connect, and the first inverting input accesses the One Type-C normal voltage, described first comparator according to a described Type-C normal voltage and described primary nodal point voltage or Person, according to a described Type-C normal voltage and described secondary nodal point voltage, compares outfan from first defeated to described controller Go out the first level signal；
Second comparator, its second inverting input and described first output switching terminal connect, and the second in-phase input end accesses the Two Type-C normal voltages, described second comparator according to described 2nd Type-C normal voltage and described primary nodal point voltage or Person, according to described 2nd Type-C normal voltage and described secondary nodal point voltage, compares outfan from second defeated to described controller Go out second electrical level signal；
When external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 1.23V, described 2nd Type-C When normal voltage is 0.66V, described first level signal is the high level persistently exported in the range of holding time, then described Described time series pulse signals is maintained low level by controller, or, described first level signal is in the range of holding time Output low level and second electrical level signal is the high level persistently exported in the range of holding time, the most described controller will Described time series pulse signals maintains low level；Or,
When external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 0.66V, described 2nd Type-C When normal voltage is 0.2V, described first level signal is at the interior high level persistently exported of holding time, the most described controller Described time series pulse signals is maintained low level, or, described first level signal is defeated for continuing in the range of holding time The low level gone out, and described second electrical level signal is the high level persistently exported in the range of holding time, the most described control Described time series pulse signals is maintained low level by device processed；Or,
When external equipment is UFP equipment or DRP equipment, and a described Type-C normal voltage is 1.6V, described 2nd Type-C When normal voltage is 2.6V, described first level signal is the high level persistently exported in the range of holding time, then described Described time series pulse signals is maintained high level by controller, or, described first level signal is in the range of holding time The low level persistently exported, described second electrical level signal is for hold time the interior high level that persistently exports, and the most described controller will Described time series pulse signals maintains high level.
6. a USB Type-C interface circuit, is used for detecting external equipment, and including the first signal end and secondary signal end, it is special Levy and be, including:
Controller, for output timing pulse signal；
First current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described first Number end connect primary nodal point output primary nodal point voltage；
Second current source circuit, itself and described controller connect, for according to described time series pulse signals, believing with described second Number end connect secondary nodal point output secondary nodal point voltage；
Logic circuit, it connects with described primary nodal point, described secondary nodal point and described controller respectively, for according to described Primary nodal point voltage and described secondary nodal point voltage, export the first level signal, and described controller is according to described first level letter Number, export second electrical level signal；
Comparison module, its input and described logic circuit connect, and outfan and described controller connect, for according to described the Two level signals, access described primary nodal point voltage or described secondary nodal point voltage.
USB Type-C interface circuit the most according to claim 6, it is characterised in that
When described first signal end and described secondary signal end all do not access external equipment, the sequential of described primary nodal point voltage All identical with described time series pulse signals with the sequential of described secondary nodal point voltage；Or,
When described first signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Primary nodal point voltage is become low level by high level saltus step, and described secondary nodal point voltage keeps high level；Or,
When described first signal end accesses DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Primary nodal point voltage is become high level by low transition, and described secondary nodal point voltage keeps low level；Or,
When described secondary signal terminates into UFP equipment or DRP equipment, and when described time series pulse signals is high level, described Secondary nodal point voltage is become low level by high level saltus step, and described primary nodal point voltage keeps high level；Or,
When described secondary signal terminates into DFP equipment or DRP equipment, and when described time series pulse signals is low level, described Secondary nodal point voltage is become high level by low transition, and described primary nodal point voltage keeps low level.
USB Type-C interface circuit the most according to claim 7, it is characterised in that
When described first signal end accesses UFP equipment or DRP equipment, and when described time series pulse signals is high level, described First level signal of logic circuit output is low level signal, so that the second electrical level signal of described controller output is high electricity Flat, and described comparison module is accessed primary nodal point voltage；Or,
When described first signal end accesses DFP equipment or DRP equipment, and when described time series pulse signals is low level, described First level signal of logic circuit output is high level signal, so that the second electrical level signal of described controller output is high electricity Flat, and described comparison module is accessed primary nodal point voltage；Or,
When described secondary signal terminates into UFP equipment or DRP equipment, and when described time series pulse signals is high level, described First level signal of logic circuit output is high level signal, so that the second electrical level signal of described controller output is low electricity Flat, and described comparison module is accessed secondary nodal point voltage；Or,
When described secondary signal terminates into DFP equipment or DRP equipment, and when described time series pulse signals is low level, described First level signal of logic circuit output is low level signal, so that the second electrical level signal of described controller output is low electricity Flat, and described comparison module is accessed secondary nodal point voltage.
USB Type-C interface circuit the most according to claim 8, it is characterised in that described comparison module includes:
First single-pole double-throw switch (SPDT), including the first switch input terminal, second switch input, the first output switching terminal and first Switch control terminal, described first switch input terminal accesses described primary nodal point voltage, and described second switch input accesses described Secondary nodal point voltage, described first switch control terminal accesses described second electrical level signal；
First comparator, its first inverting input and described first output switching terminal connect, and the first in-phase input end accesses the One Type-C normal voltage, first compares outfan exports the 3rd level to described controller；
Second comparator, its second inverting input and described first output switching terminal connect, and the second in-phase input end accesses the Two Type-C normal voltages, second compares outfan exports the 4th level to described controller；When described 3rd level is in dimension Holding the high level persistently exported in the range of the time, described time series pulse signals is maintained high level by the most described controller；Work as institute Stating the 4th level is the high level persistently exported in the range of holding time, and the most described controller is by described time series pulse signals Maintain high level；
3rd comparator, its 3rd in-phase input end and described first output switching terminal connect, and the 3rd inverting input accesses the Three Type-C normal voltages, the 3rd compares outfan exports the 5th level to described controller；
4th comparator, its 4th in-phase input end and described first output switching terminal connect, and the 4th inverting input accesses the Four Type-C normal voltages, the 4th compares outfan exports the 6th level to described controller；
5th comparator, its 5th in-phase input end and described first output switching terminal connect, and the 5th inverting input accesses the Five Type-C normal voltages, the 5th compares outfan exports the 7th level to described controller；When described 5th level is in dimension Holding the high level persistently exported in the range of the time, described time series pulse signals is maintained low level by the most described controller；Work as institute Stating the 6th level is the high level persistently exported in the range of holding time, and described 5th level is to hold time In the range of the low level that persistently exports, described time series pulse signals is maintained low level by the most described controller；When described 7th electricity Put down the high level for persistently exporting in the range of holding time, and described 6th level is for hold in the range of holding time The low level of continuous output, described time series pulse signals is maintained low level by the most described controller.
USB Type-C interface circuit the most according to claim 8, it is characterised in that described comparison module includes:
First single-pole double-throw switch (SPDT), including the first switch input terminal, second switch input, the first output switching terminal and first Switch control terminal, described first switch input terminal accesses described primary nodal point voltage, and described second switch input accesses described Secondary nodal point voltage, described first switch control terminal accesses described second electrical level signal；
First comparator, its first in-phase input end and described first output switching terminal connect, and the first inverting input accesses the One Type-C normal voltage, described first comparator according to a described Type-C normal voltage and described primary nodal point voltage or Person, according to a described Type-C normal voltage and described secondary nodal point voltage, compares outfan from first defeated to described controller Go out three level signal；
Second comparator, its second inverting input and described first output switching terminal connect, and the second in-phase input end accesses the Two Type-C normal voltages, described second comparator according to described 2nd Type-C normal voltage and described primary nodal point voltage or Person, according to described 2nd Type-C normal voltage and described secondary nodal point voltage, compares outfan from second defeated to described controller Go out the 4th level signal；
When external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 1.23V, described 2nd Type-C When normal voltage is 0.66V, described three level signal is the high level persistently exported in the range of holding time, then described Described time series pulse signals is maintained low level by controller, or, described three level signal is in the range of holding time Output low level and described 4th level signal is the high level persistently exported in the range of holding time, the most described control Described time series pulse signals is maintained low level by device；Or,
When external equipment is DFP equipment or DRP equipment, and a described Type-C normal voltage is 0.66V, described 2nd Type-C When normal voltage is 0.2V, described three level signal is at the interior high level persistently exported of holding time, the most described controller Described time series pulse signals is maintained low level, or, described three level signal is defeated for continuing in the range of holding time The low level gone out, and the high level that described 4th level signal persistently exports in the range of holding time, the most described control Described time series pulse signals is maintained low level by device；Or,
When external equipment is UFP equipment or DRP equipment, and a described Type-C normal voltage is 1.6V, described 2nd Type-C When normal voltage is 2.6V, the high level that described three level signal persistently exports in the range of holding time, the most described control Described time series pulse signals is maintained high level by device processed, or, described three level signal is for hold in the range of holding time The low level of continuous output, described 4th level signal is for hold time the interior high level that persistently exports, and the most described controller is by institute State time series pulse signals and maintain high level.
CN201610657211.1A 2016-08-11 2016-08-11 USB Type-C interface circuit Active CN106294244B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610657211.1A CN106294244B (en) 2016-08-11 2016-08-11 USB Type-C interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610657211.1A CN106294244B (en) 2016-08-11 2016-08-11 USB Type-C interface circuit

Publications (2)

Publication Number Publication Date
CN106294244A true CN106294244A (en) 2017-01-04
CN106294244B CN106294244B (en) 2023-08-11

Family

ID=57669860

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610657211.1A Active CN106294244B (en) 2016-08-11 2016-08-11 USB Type-C interface circuit

Country Status (1)

Country Link
CN (1) CN106294244B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107145207A (en) * 2017-05-06 2017-09-08 湖南融和微电子有限公司 A kind of wake-up circuit under holding state pattern
CN107480084A (en) * 2017-07-26 2017-12-15 深圳天珑无线科技有限公司 Type C mobile terminals charge and data transmission method, device and storage medium
CN108415865A (en) * 2018-02-02 2018-08-17 广东欧珀移动通信有限公司 Interface circuit and electronic device
CN109889658A (en) * 2019-01-25 2019-06-14 努比亚技术有限公司 Accessory and mobile terminal for mobile terminal
CN110413553A (en) * 2018-04-27 2019-11-05 太普动力新能源(常熟)股份有限公司 The universal sequence bus unit of variable voltage
CN110502382A (en) * 2019-08-26 2019-11-26 Oppo（重庆）智能科技有限公司 TYPE-C interface test method, device, storage medium and electronic equipment
CN110716525A (en) * 2018-07-11 2020-01-21 深圳市海美思信息技术有限公司 Method and circuit for detecting signal state of CC terminal of USB-C interface
CN111240453A (en) * 2018-11-29 2020-06-05 瑞萨电子株式会社 Controller, control method, and control program
CN111881072A (en) * 2020-07-30 2020-11-03 武汉精立电子技术有限公司 High-speed USB TYPE-C interface device supporting bidirectional transmission and graphic signal generator
WO2021036772A1 (en) * 2019-08-28 2021-03-04 上海爻火微电子有限公司 Type c interface single-pole double-throw switch circuit, analog switch chip and electronic device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090198841A1 (en) * 2008-02-06 2009-08-06 Matsushita Electric Industrial Co., Ltd. Interface detecting circuit and interface detecting method
CN103106167A (en) * 2013-01-22 2013-05-15 矽力杰半导体技术(杭州)有限公司 Universal Serial Bus (USB) equipment and control method thereof
CN105045738A (en) * 2014-03-24 2015-11-11 诺基亚技术有限公司 Method and device for connecting USB type-c devices
CN105630724A (en) * 2016-01-27 2016-06-01 深圳慧能泰半导体科技有限公司 USB Type-C system control circuit
US9400546B1 (en) * 2015-06-19 2016-07-26 Cypress Semiconductor Corporation Low-power implementation of Type-C connector subsystem
US20160217103A1 (en) * 2015-01-27 2016-07-28 Samsung Electronics Co., Ltd. Method and apparatus for full duplex transmission between electronic devices
CN206162503U (en) * 2016-08-11 2017-05-10 深圳慧能泰半导体科技有限公司 USBType C interface circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090198841A1 (en) * 2008-02-06 2009-08-06 Matsushita Electric Industrial Co., Ltd. Interface detecting circuit and interface detecting method
CN103106167A (en) * 2013-01-22 2013-05-15 矽力杰半导体技术(杭州)有限公司 Universal Serial Bus (USB) equipment and control method thereof
CN105045738A (en) * 2014-03-24 2015-11-11 诺基亚技术有限公司 Method and device for connecting USB type-c devices
US20160217103A1 (en) * 2015-01-27 2016-07-28 Samsung Electronics Co., Ltd. Method and apparatus for full duplex transmission between electronic devices
US9400546B1 (en) * 2015-06-19 2016-07-26 Cypress Semiconductor Corporation Low-power implementation of Type-C connector subsystem
CN105630724A (en) * 2016-01-27 2016-06-01 深圳慧能泰半导体科技有限公司 USB Type-C system control circuit
CN206162503U (en) * 2016-08-11 2017-05-10 深圳慧能泰半导体科技有限公司 USBType C interface circuit

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107145207A (en) * 2017-05-06 2017-09-08 湖南融和微电子有限公司 A kind of wake-up circuit under holding state pattern
CN107145207B (en) * 2017-05-06 2020-04-07 湖南融和微电子有限公司 Wake-up circuit in standby state mode
CN107480084A (en) * 2017-07-26 2017-12-15 深圳天珑无线科技有限公司 Type C mobile terminals charge and data transmission method, device and storage medium
CN108415865A (en) * 2018-02-02 2018-08-17 广东欧珀移动通信有限公司 Interface circuit and electronic device
CN110413553A (en) * 2018-04-27 2019-11-05 太普动力新能源(常熟)股份有限公司 The universal sequence bus unit of variable voltage
CN110413553B (en) * 2018-04-27 2023-05-12 太普动力新能源(常熟)股份有限公司 Universal serial bus device with variable voltage
CN110716525A (en) * 2018-07-11 2020-01-21 深圳市海美思信息技术有限公司 Method and circuit for detecting signal state of CC terminal of USB-C interface
CN111240453A (en) * 2018-11-29 2020-06-05 瑞萨电子株式会社 Controller, control method, and control program
CN109889658A (en) * 2019-01-25 2019-06-14 努比亚技术有限公司 Accessory and mobile terminal for mobile terminal
CN110502382B (en) * 2019-08-26 2023-04-07 Oppo（重庆）智能科技有限公司 TYPE-C interface testing method and device, storage medium and electronic equipment
CN110502382A (en) * 2019-08-26 2019-11-26 Oppo（重庆）智能科技有限公司 TYPE-C interface test method, device, storage medium and electronic equipment
WO2021036772A1 (en) * 2019-08-28 2021-03-04 上海爻火微电子有限公司 Type c interface single-pole double-throw switch circuit, analog switch chip and electronic device
US11451224B2 (en) 2019-08-28 2022-09-20 Shanghai Yaohuo Microelectronics Co., Ltd. Single-pole double-throw switch circuit with type-c interface, analog switch chip, and electronic device
CN111881072A (en) * 2020-07-30 2020-11-03 武汉精立电子技术有限公司 High-speed USB TYPE-C interface device supporting bidirectional transmission and graphic signal generator
CN111881072B (en) * 2020-07-30 2021-11-23 武汉精立电子技术有限公司 High-speed USB TYPE-C interface device supporting bidirectional transmission and graphic signal generator

Also Published As

Publication number Publication date
CN106294244B (en) 2023-08-11

Similar Documents

Publication Publication Date Title
CN106294244A (en) A kind of USB Type C interface circuit
CN206162503U (en) USBType C interface circuit
CN204929366U (en) DALI interface circuit
CN103929854B (en) A kind of LED drive device and LED light adjusting controller thereof
CN106300314A (en) The high voltage protective system and method for Type C interface chip CC pin
CN107682961A (en) A kind of LED fishing lamps power supply output switching circuit
CN106300637B (en) Chip power supply circuit, chip, print cartridge
CN202121292U (en) Power failure protective circuit and power supply circuit
CN106028521B (en) A kind of control method of light adjusting circuit
CN203775490U (en) LED color temperature adjusting circuit and LED lighting device
CN101640415A (en) Power supply current equalizing system and current equalizing control method thereof
CN109890115A (en) A kind of intelligent lighting control system and its flash control circuit
CN104980383B (en) Local oscillator leakage of transmitter reduces system
CN102857719A (en) Power supply control system and power supply control method
CN208369198U (en) A kind of load protection circuit and motor
CN106873509A (en) A kind of carrier rocket power supply far controls regulating circuit and method
CN206020648U (en) A kind of three-phase and four-line electric energy meter with fault self-checking function
CN206756912U (en) Voltage detecting circuit and circuit board
CN2894147Y (en) Standby regulating switching circuit for TV power supply
CN104571091B (en) The controller failure detecting system of intelligent transducer
CN101163170B (en) Feed condition and ring current testing apparatus
CN209283208U (en) A kind of isolation communicating circuit for leading aobvious plate
CN107818066A (en) Data communication system
CN207503216U (en) MBUS communication switching circuits
CN108055139B (en) Method for reducing power consumption of communication equipment port in idle state

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant