CN106294244B - USB Type-C interface circuit - Google Patents

USB Type-C interface circuit Download PDF

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Publication number
CN106294244B
CN106294244B CN201610657211.1A CN201610657211A CN106294244B CN 106294244 B CN106294244 B CN 106294244B CN 201610657211 A CN201610657211 A CN 201610657211A CN 106294244 B CN106294244 B CN 106294244B
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signal
level
node voltage
controller
high level
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CN106294244A (en
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刘靖
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Hynetek Semiconductor Co ltd
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Hynetek Semiconductor Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the invention relates to the technical field of USB interfaces, in particular to a USB Type-C interface circuit. The USB Type-C interface circuit is used for detecting external equipment and comprises a first signal end and a second signal end, and further comprises: a controller; a first current source circuit connected to the controller; a second current source circuit connected to the controller; a logic circuit connected to the controller; and the input end of the comparison module is connected with the logic circuit, and the output end of the comparison module is connected with the controller. According to the invention, on one hand, the USB Type-C interface circuit can successfully handshake with the external device according to the Type of the external device, namely, the UFP device, the DFP device or the DRP device is identified, and on the other hand, the external device can be connected with the first signal end or the second signal end in a random conversion manner, and the USB Type-C interface circuit can respond to the conversion in time, so that the USB Type-C interface circuit identifies the inserting direction of the external device.

Description

USB Type-C interface circuit
Technical Field
The embodiment of the invention relates to the technical field of USB interfaces, in particular to a USB Type-C interface circuit.
Background
With the popularity of the USB Type-C interface, more devices are required to support the USB Type-C protocol. The Type-C interface has 24 interfaces in total, 12 on the front and 12 on the back, according to the specification of the Type-C standard protocol. FIG. 1 is a schematic diagram of the various pin definitions of an USB Type-C receptacle under the Type-C standard protocol. As shown in fig. 1, the USB Type-C receptacle includes a first signal terminal CC1 and a second signal terminal CC2.
According to the Type-C protocol, the operation modes of the devices supporting the Type-C protocol can be generally divided into three modes, wherein the first mode is UFP mode (Upstream Facing Port, uplink port), namely, the slave, and the slave takes power from the host. The second is DFP mode (Downstream Facing Port, downstream port), i.e., the master, which provides power to the slaves. The third is DRP mode (Dual roller port, bi-directional port). The DRP mode may operate in DFP mode or UFP mode. When the DRP device is connected to the UFP device, the DRP device is converted into a DFP device, and when the DRP device is connected to the DFP device, the DRP device is converted into a UFP device. When two DRP devices are connected together, when either one of them operates in DFP mode, the other is converted into UFP device. When either party is operating in UFP mode, the other party is converted to a DFP device.
Fig. 2 is a schematic diagram of the communication between a DFP device and a UFP device under the Type-C standard protocol. As shown in fig. 2, for the DFP apparatus, the upper resistor Rp is connected to the dc voltage source or to the pull-up current source at the first signal terminal CC1 and the second signal terminal CC2, and fig. 2 shows the dc voltage source. For UFP devices there is a pull-down resistor Rd on the first signal terminal CC1 and the second signal terminal CC 2. When not connected, CC1 and CC2 are both pulled internally high for DFP devices and CC1 and CC2 are both pulled internally low for UFP devices. When the DFP device and the UFP device are connected, the CC1 or CC2 detects that the level is pulled down for the DFP device, which indicates that the device is connected, and the device determines the direction of inserting the device according to the level pull down condition of the CC1 or CC 2. For UFP devices, the CC1 or CC2 pin detects that the level is pulled high, and the device determines the direction of inserting the device according to the level pull-up condition of CC1 or CC 2. For example, when CC1 of the DFP device is connected to CC2 of the UFP device, the level of CC1 of the DFP device is pulled low and the level of CC2 of the UPF device is pulled high, for the DFP device, the device inserted at the time is connected to the front side, and for the UFP device, the device inserted at the time is connected to the back side. For a DRP device, it periodically switches between DFP and UFP modes, and when connected to the DFP device, automatically switches to the UFP mode for successful handshake. When a UFP device is encountered, the handshake is automatically successful in DFP mode. The communication procedure after the handover is completed corresponds to the communication procedure of DFP and UFP described above.
In the process of implementing the present invention, the inventors found that the related art has the following problems: the related art can only identify one of the UPF device, the DFP device, and the DRP device, and fails to identify the direction of the add-in device, and thus fails to fully satisfy the requirements of the Type-C protocol.
Disclosure of Invention
The technical problem that the external equipment and the inserting direction of the external equipment cannot be identified in the prior art is solved.
In order to solve the technical problems, the invention provides the following technical scheme:
in a first aspect, an embodiment of the present invention provides an USB Type-C interface circuit, configured to detect an external device, including a first signal end and a second signal end, where the USB Type-C interface circuit includes: a controller for outputting a timing pulse signal; the first current source circuit is connected with the controller and is used for outputting a first node voltage at a first node connected with the first signal end according to the time sequence pulse signal; the second current source circuit is connected with the controller and is used for outputting a second node voltage at a second node connected with the second signal end according to the time sequence pulse signal; the logic circuit is respectively connected with the first node, the second node and the controller and is used for outputting logic control signals according to the time sequence pulse signals, the first node voltage and the second node voltage; and the input end of the comparison module is connected with the logic circuit, and the output end of the comparison module is connected with the controller and is used for accessing the first node voltage or the second node voltage according to the logic control signal.
Optionally, when the first signal end and the second signal end are not connected to an external device, the time sequence of the first node voltage and the time sequence of the second node voltage are the same as the time sequence pulse signal; or when the first signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the first node voltage jumps from the high level to the low level, and the second node voltage keeps at the high level; or when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the first node voltage jumps from the low level to the high level, and the second node voltage is kept at the low level; or when the second signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the second node voltage jumps from the high level to the low level, and the first node voltage keeps at the high level; or when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is at a low level, the second node voltage jumps from the low level to the high level, and the first node voltage keeps at the low level.
Optionally, the logic control signals include a first logic control signal and a second logic control signal; when the first signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is in a high level, the logic circuit outputs the first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal; or when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the logic circuit outputs the first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal; or when the second signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the logic circuit outputs a second logic control signal, and the comparison module is connected to the second node voltage according to the second logic control signal; or when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is at a low level, the logic circuit outputs the second logic control signal, and the comparison module is connected to the second node voltage according to the second logic control signal.
Optionally, the comparing module includes: the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the logic control signal; the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end of the first comparator is connected with a first Type-C standard voltage, and the first comparison output end outputs a first level to the controller; the second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparison output end outputs a second level to the controller; when the first level is a high level continuously output in a maintaining time range, the controller maintains the time sequence pulse signal at the high level; when the second level is a high level continuously output in a maintaining time range, the controller maintains the time sequence pulse signal at the high level; the third non-inverting input end of the third comparator is connected with the first switch output end, the third inverting input end of the third comparator is connected with a third Type-C standard voltage, and the third comparison output end outputs a third level to the controller; the fourth non-inverting input end of the fourth comparator is connected with the first switch output end, the fourth inverting input end of the fourth comparator is connected with a fourth Type-C standard voltage, and the fourth comparison output end outputs a fourth level to the controller; the fifth non-inverting input end of the fifth comparator is connected with the first switch output end, the fifth inverting input end of the fifth comparator is connected with a fifth Type-C standard voltage, and the fifth comparison output end outputs a fifth level to the controller; when the third level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the fourth level is a high level continuously output in a range of a sustain time and the third level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the fifth level is a high level continuously output in a range of a sustain time and the fourth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level.
Optionally, the comparing module includes: the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the logic control signal; the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end is connected with a first Type-C standard voltage, and the first comparator outputs a first level signal to the controller from a first comparison output end according to the first Type-C standard voltage and the first node voltage or according to the first Type-C standard voltage and the second node voltage; the second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparator outputs a second level signal to the controller from a second comparison output end according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage; when the external device is DFP device or DRP device, the first Type-C standard voltage is 1.23V, and the second Type-C standard voltage is 0.66V, the first level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a low level, or the second level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a low level; or when the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, and the second Type-C standard voltage is 0.2V, the first level signal is a high level continuously output in a sustain time, the controller maintains the timing pulse signal at a low level, or the first level signal is a low level continuously output in a sustain time range, and the second level signal is a high level continuously output in a sustain time range, the controller maintains the timing pulse signal at a low level; or when the external device is a UFP device or a DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, where the first level signal is a high level continuously output in a maintaining time range, the controller maintains the timing pulse signal at a high level, or the first level signal is a low level continuously output in a maintaining time range, and the second level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a high level.
In a second aspect, an embodiment of the present invention provides an USB Type-C interface circuit, configured to detect an external device, including a first signal end and a second signal end, where the USB Type-C interface circuit includes: a controller for outputting a timing pulse signal; the first current source circuit is connected with the controller and is used for outputting a first node voltage at a first node connected with the first signal end according to the time sequence pulse signal; the second current source circuit is connected with the controller and is used for outputting a second node voltage at a second node connected with the second signal end according to the time sequence pulse signal; the logic circuit is respectively connected with the first node, the second node and the controller and is used for outputting a first level signal according to the first node voltage and the second node voltage, and the controller is used for outputting a second level signal according to the first level signal; and the input end of the comparison module is connected with the logic circuit, and the output end of the comparison module is connected with the controller and is used for accessing the first node voltage or the second node voltage according to the second level signal.
Optionally, when the first signal end and the second signal end are not connected to an external device, the time sequence of the first node voltage and the time sequence of the second node voltage are the same as the time sequence pulse signal; or when the first signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the first node voltage jumps from the high level to the low level, and the second node voltage keeps at the high level; or when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the first node voltage jumps from the low level to the high level, and the second node voltage is kept at the low level; or when the second signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the second node voltage jumps from the high level to the low level, and the first node voltage keeps at the high level; or when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is at a low level, the second node voltage jumps from the low level to the high level, and the first node voltage keeps at the low level.
Optionally, when the first signal end is connected to the UFP device or the DRP device and the timing pulse signal is at a high level, the first level signal output by the logic circuit is a low level signal, so that the second level signal output by the controller is at a high level, and the comparison module is connected to a first node voltage; or when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the first level signal output by the logic circuit is a high level signal, so that the second level signal output by the controller is at a high level, and the comparison module is connected to a first node voltage; or when the second signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is at a high level, the first level signal output by the logic circuit is a high level signal, so that the second level signal output by the controller is at a low level, and the comparison module is connected to a second node voltage; or when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is at a low level, the first level signal output by the logic circuit is a low level signal, so that the second level signal output by the controller is at a low level, and the comparison module is connected to a second node voltage.
Optionally, the comparing module includes: the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the second level signal; the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end of the first comparator is connected with a first Type-C standard voltage, and the first comparison output end outputs a third level to the controller; the second inverting input end of the second comparator is connected with the output end of the first switch, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparison output end outputs a fourth level to the controller; when the third level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a high level; when the fourth level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a high level; the third non-inverting input end of the third comparator is connected with the first switch output end, the third inverting input end of the third comparator is connected with a third Type-C standard voltage, and the third comparison output end outputs a fifth level to the controller; the fourth non-inverting input end of the fourth comparator is connected with the output end of the first switch, the fourth inverting input end of the fourth comparator is connected with a fourth Type-C standard voltage, and the fourth comparison output end outputs a sixth level to the controller; the fifth non-inverting input end of the fifth comparator is connected with the first switch output end, the fifth inverting input end of the fifth comparator is connected with a fifth Type-C standard voltage, and the fifth comparison output end outputs a seventh level to the controller; when the fifth level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the sixth level is a high level continuously output in a range of a sustain time and the fifth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the seventh level is a high level continuously output in a range of a sustain time and the sixth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level.
Optionally, the comparing module includes: the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the second level signal; the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end is connected with a first Type-C standard voltage, and the first comparator outputs a third level signal to the controller from the first comparing output end according to the first Type-C standard voltage and the first node voltage or according to the first Type-C standard voltage and the second node voltage; the second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparator outputs a fourth level signal to the controller from a second comparison output end according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage; when the external device is a DFP device or a DRP device, the first Type-C standard voltage is 1.23V, and the second Type-C standard voltage is 0.66V, the controller maintains the timing pulse signal at a low level when the third level signal is a high level continuously output in a range of a maintaining time, or maintains the timing pulse signal at a low level when the third level signal is a low level output in a range of a maintaining time and the fourth level signal is a high level continuously output in a range of a maintaining time, and maintains the timing pulse signal at a low level; or when the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, the second Type-C standard voltage is 0.2V, the third level signal is a high level continuously output in a sustain time, the controller maintains the timing pulse signal at a low level, or the third level signal is a low level continuously output in a sustain time range, and the fourth level signal is a high level continuously output in a sustain time range, the controller maintains the timing pulse signal at a low level; or when the external device is a UFP device or a DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, where the third level signal is a high level continuously output in a maintaining time range, the controller maintains the timing pulse signal at a high level, or the third level signal is a low level continuously output in a maintaining time range, and the fourth level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a high level.
In each embodiment of the invention, when the external device is UFP device, DFP device or DRP device and is connected to the first signal terminal, the first current source circuit outputs a first node voltage at the first node, the logic circuit outputs a logic control signal according to the time sequence pulse signal, the first node voltage and the second node voltage, the comparison module is connected to the first node voltage according to the logic control signal, and the comparison module outputs a level signal from the output terminal to the controller; when the external device is UFP device, DFP device or DRP device and is connected to the second signal end, the second current source circuit outputs a second node voltage at the second node, the logic circuit outputs a logic control signal according to the time sequence pulse signal, the first node voltage and the second node voltage, the comparison module is connected to the second node voltage according to the logic control signal, and the comparison module outputs a level signal from the output end to the controller. In the process, on one hand, the USB Type-C interface circuit can successfully handshake with external equipment according to the Type of the external equipment, namely, the UFP equipment, the DFP equipment or the DRP equipment is identified, and on the other hand, the external equipment can be connected with the first signal end or the second signal end in a random conversion manner, and the USB Type-C interface circuit can respond to the conversion in time, so that the USB Type-C interface circuit identifies the inserting direction of the external equipment.
Drawings
FIG. 1 is a schematic diagram of the various pin definitions of an USB Type-C receptacle under the Type-C standard protocol;
fig. 2 is a schematic diagram of communication between a DFP device and a UFP device under a Type-C standard protocol;
FIG. 3 is a schematic block diagram of a USB Type-C interface circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a USB Type-C interface circuit according to an embodiment of the present invention;
FIG. 4a is a timing diagram of the insertion of the USB Type-C interface circuit of FIG. 4 into a UPF device;
FIG. 4b is a timing diagram of the insertion of the USB Type-C interface circuit of FIG. 4 into a DPF device;
FIG. 5 is a schematic diagram of a USB Type-C interface circuit according to another embodiment of the present invention;
FIG. 6 is a schematic block diagram of a USB Type-C interface circuit according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of a USB Type-C interface circuit according to another embodiment of the present invention;
fig. 8 is a schematic diagram of a USB Type-C interface circuit according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Fig. 3 is a schematic block diagram of an USB Type-C interface circuit according to an embodiment of the present invention. As shown in fig. 3, the first current source circuit 301 is connected to the first signal terminal CC1 and the controller 302, respectively. The controller 302 outputs a timing pulse signal SW, wherein the timing pulse signal SW is a typical period specified by the Type-C protocol, and specifically, the timing pulse signal SW is a square wave of 75 ms. The second current source circuit 303 is connected to the second signal terminal CC2 and the controller 302, respectively. The first current source circuit 301 and the second current source circuit 303 simultaneously receive the timing pulse signal SW sent by the controller 302, and the first current source circuit 301 outputs a first node voltage at the first node 10A connected to the first signal terminal CC1 according to the timing pulse signal SW, and the second current source circuit 303 outputs a second node voltage at the second node 10B connected to the second signal terminal CC2 according to the timing pulse signal SW.
In this embodiment, when neither the first signal terminal CC1 nor the second signal terminal CC2 is connected to the external device, the timing of the first node voltage and the timing of the second node voltage are the same as the timing pulse signal SW, i.e. the first current source circuit 301 outputs the same first node voltage and the timing pulse signal at the first node 10A when the external device is not connected, it should be understood by those skilled in the art that no matter what first current source circuit 301 is designed by the designer according to the Type-C protocol, as long as the voltage output is the same as the timing pulse signal when the external device is not connected, any replaced first current source circuit 301 should fall within the protection scope of the present invention.
In this embodiment, the second current source circuit 303 and the first current source circuit 301 are symmetrical circuits, and the structure and the working principle are the same as those of the first current source circuit 301, and need not be described here.
In some embodiments, fig. 4 is a schematic structural diagram of an USB Type-C interface circuit according to an embodiment of the present invention. As shown in fig. 4, the first current source circuit 301 includes a first current source I1, a second single-pole double-throw switch S2, and a first pull-down resistor R1, the second single-pole double-throw switch S2 includes a third switch input terminal S21, a fourth switch input terminal S22, a second switch output terminal S23, and a second switch control terminal S24, the third switch input terminal S21 is connected to the first current source I1, the fourth switch input terminal S22 is connected to the first pull-down resistor R1, the second switch output terminal S23 is connected to the first signal terminal CC1, and the second switch control terminal S24 is connected to the controller 302. When the first signal terminal CC1 is not connected to an external device, the first current source I1 is turned on when the second switch control terminal S24 is defined to be connected to the high-level timing pulse signal SW, and the first pull-down resistor R1 is turned on when the second switch control terminal is defined to be connected to the low-level timing pulse signal SW. Of course, the designer defines the meaning of the second switch control terminal S24 accessing the timing pulse signal SW according to the operation requirement. Obviously, since the first signal terminal CC1 is not connected to the external device, the timing of the first node voltage is the same as the timing pulse signal SW, for example, when the timing pulse signal SW is at a high level, the first node voltage is at a high level, and when the timing pulse signal SW is at a low level, the first node voltage is at a low level. Here, the first node 10A may be equivalent to the second switch output terminal S23, or may also be equivalent to the first signal terminal CC1. In designing the first current source circuit 301, the designer can also perform conversion on the first current source circuit 301 shown in the present embodiment. In some embodiments, the first current source circuit 301 may output the first node voltage of different voltage values according to the configured current source in combination with the Type-C protocol, for example, when the configured current source of the first current source circuit 301 is 330uA, the first node voltage is 1.68V. When the current source configured by the first current source circuit 301 is 180uA, the first node voltage is 0.918V, and when the current source configured by the first current source circuit 301 is 80uA, the first node voltage is 0.408V. The current source is designed according to the Type-C protocol, and the designer may design the first current source circuit 301 with multiple transforms according to the Type-C protocol, so as to achieve the purpose of outputting the first node voltages with different voltage values according to the timing pulse signal SW.
As shown in fig. 4, the second current source circuit 303 includes a second current source I2, a third single-pole double-throw switch S3, and a second pull-down resistor R2, the third single-pole double-throw switch S3 includes a fifth switch input terminal S31, a sixth switch input terminal S32, a second switch output terminal S33, and a third switch control terminal S34, the fifth switch input terminal S31 is connected to the second current source I2, the sixth switch input terminal S32 is connected to the second pull-down resistor R2, the second switch output terminal S33 is connected to the second signal terminal CC2, and the third switch control terminal S34 is connected to the controller 302. When the second signal terminal CC2 is not connected to an external device, the third switch control terminal S34 is defined to switch on the second current source I2 when the high-level timing pulse signal SW is connected to the low-level timing pulse signal SW, and to switch on the second pull-down resistor R2.
In this embodiment, when the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, please combine fig. 2, because the pull-down resistor Rd1 of the UFP device or the DRP device pulls down the first node voltage of the first signal terminal CC1, the first node voltage jumps from a high level to a low level, and because the second signal terminal CC2 is not connected to the external device, the second node voltage remains at a high level. Here, when the first signal terminal CC1 accesses the UFP device or the DRP device and the timing pulse signal SW is at a low level, the USB Type-C interface is not successfully connected to the external device.
In some embodiments, please refer to fig. 2 and fig. 4 again, when the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the second single-pole double-throw switch S2 turns on the first current source I1, and the first node voltage of the first signal terminal CC1 is pulled down due to the pull-down resistor Rd1 of the UFP device or the DRP device, so that the first node voltage jumps from the high level to the low level. Since the second signal terminal CC2 is not connected to an external device, and the third single pole double throw switch S3 turns on the second current source I2, the second node voltage remains high.
In this embodiment, when the first signal terminal CC1 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, referring to fig. 2 again, due to the voltage source or the current source of the DFU device or the DRP device, it can raise the voltage of the first node 10A relatively, so that the voltage of the first node jumps from a low level to a high level. Since the second signal terminal CC2 is not connected to an external device, the voltage of the second node is kept low. Here, when the first signal terminal CC1 accesses the DFP device or the DRP device and the timing pulse signal SW is at a high level, the USB Type-C interface is not successfully connected to the external device. Of course, this embodiment only provides a connection between the timing pulse signal and the USB Type-C interface when the external device is connected, and the designer can define various implementation manners according to the operation requirements and in combination with the content trained by the present invention, which is not limited to this embodiment.
In some embodiments, please refer to fig. 2 and fig. 4 again, when the first signal terminal CC1 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the second single pole double throw switch S2 turns on the first current source I1, and the voltage of the first node of the first signal terminal CC1 is raised due to the voltage source or the current source of the DFP device or the DRP device, so that the first node voltage jumps from a low level to a high level. Since the second signal terminal CC2 is not connected to an external device, and the third single pole double throw switch S3 turns on the second pull-down resistor R2, the second node voltage remains low.
In the present embodiment, for the same reason as described above, when the second signal terminal CC2 is connected to the UFP device or the DRP device and the timing pulse signal SW is at the high level, the second node voltage jumps from the high level to the low level, and the first node voltage remains at the high level. When the second signal terminal CC2 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the second node voltage jumps from the low level to the high level, and the first node voltage remains at the low level.
In the present embodiment, the logic circuit 304 is connected to the first node 10A, the second node 10B, and the controller 302, respectively, and outputs a logic control signal according to the timing pulse signal SW, the first node voltage, and the second node voltage. When the USB Type-C interface circuit is connected to an external device, the logic circuit 304 may perform a logic operation on the timing pulse signal SW, the first node voltage, and the second node voltage, to finally obtain a logic control signal, where the logic control signal is used to control the comparison module 305, so that the comparison module 305 may access the first node voltage or the second node voltage, where an input end of the comparison module 305 is connected to the logic circuit 304, and an output end is connected to the controller 302. In the process, on one hand, the USB Type-C interface circuit can successfully handshake with external equipment according to the Type of the external equipment, namely, the UFP equipment, the DFP equipment or the DRP equipment is identified, and on the other hand, the external equipment can be connected with the first signal end or the second signal end in a random conversion manner, and the USB Type-C interface circuit can respond to the conversion in time, so that the USB Type-C interface circuit identifies the inserting direction of the external equipment.
In some embodiments, the logic control signals include a first logic control signal and a second logic control signal. When the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the logic circuit outputs a first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal.
When the first signal end CC1 is connected to the DFP device or the DRP device and the time sequence pulse signal SW is at a low level, the logic circuit outputs a first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal.
Therefore, when the external device is connected to the first signal terminal CC1, the first current source circuit 301 outputs a first node voltage at the first node 10A, and the first logic control signal generated by the logic circuit 304 ensures that the first node voltage is connected to the comparison module 305 no matter what type of the external device is, and the comparison module 305 generates a certain output to the controller 302 according to the connected first node voltage.
Similarly, when the second signal terminal CC2 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the logic circuit 304 outputs a second logic control signal, and the comparison module 305 is connected to the second node voltage according to the second logic control signal.
When the second signal terminal is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the logic circuit 304 outputs a second logic control signal, and the comparison module 305 is connected to the second node voltage according to the second logic control signal.
Therefore, when the external device is connected to the second signal terminal CC2, the second current source circuit 303 outputs a second node voltage at the second node 10B, and the second logic control signal generated by the logic circuit 304 ensures that the second node voltage is connected to the comparison module 305 no matter what type of the external device is, and the comparison module 305 generates a certain output to the controller 302 according to the connected second node voltage.
In this embodiment, the logic circuit 304 may be composed of a plurality of logic devices, for example, an or gate logic device, an not gate device, and the like, and the logic circuit 304 may be a logic chip or other circuits having logic operations, and no matter what logic device is used, or a logic chip or the like, as long as the output logic control signal can achieve the object of the present invention according to the teaching of the present embodiment.
Referring to fig. 4 again, the logic circuit 304 includes a sixth comparator 3041 and an exclusive-or circuit 3042, a sixth inverting input terminal of the sixth comparator 3041 is connected to the second node 10B, a sixth non-inverting input terminal is connected to the first node 10A, a sixth comparing output terminal OUT6 is connected to a first exclusive-or input terminal of the exclusive-or circuit 3042, a second exclusive-or input terminal is connected to the timing pulse signal SW, and an exclusive-or output terminal DIR is connected to the comparing module 305.
When the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the first node voltage is lower than the second node voltage at this time, so that the output level of the sixth comparison output terminal OUT6 is at a low level, and the output level of the exclusive or output terminal DIR is at a high level, so that the comparison module 305 is connected to the first node voltage according to the logic control signal at the high level.
When the first signal terminal CC1 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the same applies, and the output level of the sixth comparison output terminal OUT6 is at a high level, and the output level of the exclusive or output terminal DIR is at a high level, so that the comparison module 305 is connected to the first node voltage according to the logic control signal at the high level.
When the second signal terminal CC2 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the second node voltage is lower than the first node voltage at this time, so that the output level of the sixth comparison output terminal OUT6 is at a high level, and the output level of the exclusive or output terminal DIR is at a low level, so that the comparison module 305 is connected to the second node voltage according to the logic control signal at the low level.
When the second signal terminal CC2 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the same applies, and the output level of the sixth comparison output terminal OUT6 is at a low level, and the output level of the exclusive or output terminal DIR is at a low level, so that the comparison module 305 is connected to the second node voltage according to the logic control signal at the low level.
Referring to fig. 4 again, the comparison module 305 includes a first single pole double throw switch S1, a first comparator U1, a second comparator U2, a third comparator U3, a fourth comparator U4 and a fifth comparator U5. The first single-pole double-throw switch S1 includes a first switch input end S11, a second switch input end S12, a first switch output end S13, and a first switch control end S14, where the first switch input end S11 is connected to a first node voltage, the second switch input end S12 is connected to a second node voltage, and the first switch control end S14 is connected to a logic control signal.
The first inverting input terminal of the first comparator U1 is connected to the first switch output terminal S13, the first inverting input terminal is connected to the first Type-C standard voltage V1, and the first comparison output terminal outputs the first level to the controller 302. Here, the first Type-C standard voltage V1 is a voltage threshold of the charging current of the DFP apparatus 3A, and a specific value of the first Type-C standard voltage V1 is 2.6V.
The second inverting input terminal of the second comparator U2 is connected to the first switch output terminal S13, the second non-inverting input terminal is connected to the second Type-C standard voltage V2, and the second comparison output terminal outputs the second level to the controller 302. Here, the second Type-C standard voltage V2 is a voltage threshold of a default charging current of the DFP apparatus, and a specific value of the second Type-C standard voltage V2 is 1.6V.
In the present embodiment, the first current source circuitWhen the current source configured by 301 or the second current source circuit 303 is 330 μa and the first signal terminal CC1 or the second signal terminal CC2 is connected to the UFP device or the DRP device, the first node voltage or the second node voltage at this time is 1.68V (330 μa×5.1k), where 5.1K is the resistance value of the first pull-down resistor or the second pull-down resistor. When the first level is at the maintaining time t CCDEBOUNCE The device connection is successful if the continuously output high level is within the range of (1), and thus, the controller 302 maintains the high level output of the timing pulse signal SW.
When the configured current source is 80 μA or 180 μA, the second level is maintained at the holding time t CCDEBOUNCE If the device connection is successful, the controller 302 maintains the timing pulse signal SW at the high level. Here, the sustain time t CCDEBOUNCE Is the time threshold of successful connection between devices specified by Type-C protocol, and the maintenance time t CCDEBOUNCE Typically 150ms.
The controller 302 knows how much current can be output by analyzing the level output by the first comparator U1, and therefore, the USB Type-C interface circuit provided in this embodiment has a capability of identifying a corresponding broadcast current.
The third non-inverting input terminal of the third comparator U3 is connected to the first switch output terminal, the third inverting input terminal is connected to the third Type-C standard voltage V3, and the third comparison output terminal outputs a third level to the controller 302. Here, the third Type-C standard voltage V3 is a voltage threshold where the UFP device detects a 3A charging current, and a specific value of the third Type-C standard voltage V3 is 1.23V.
The fourth non-inverting input end of the fourth comparator U4 is connected with the first switch output end, the fourth inverting input end is connected with a fourth Type-C standard voltage V4, and the fourth comparison output end outputs a fourth level to the controller. Here, the fourth Type-C standard voltage V4 is a voltage threshold where the UFP device detects a 1.5A charging current, and a specific value of the fourth Type-C standard voltage V4 is 0.66V.
The fifth non-inverting input end of the fifth comparator U5 is connected with the first switch output end, the fifth inverting input end is connected with a fifth Type-C standard voltage V5, and the fifth comparison output end outputs a fifth level to the controller. Here, the fifth Type-C standard voltage V5 is a voltage threshold where the UFP device detects a charging current of 0.5A, and a specific value of the fifth Type-C standard voltage V5 is 0.2V.
In this embodiment, when the first signal terminal CC1 or the second signal terminal CC2 is connected to the DFP device or the DRP device and the current source of the DFP device or the DRP device is configured to be 330 μa, the first node voltage or the second node voltage at this time is 1.68V (330 μa×5.1k), where 5.1K is a resistor configured by the DFP device or the DRP device according to the Type-C protocol. When the third level is at the maintaining time t CCDEBOUNCE If the device connection is successful, the DFP device or the DRP device may output a current of 3A, and the controller 302 maintains the timing pulse signal SW at a low level.
The fourth level is at the sustain time t when the current source of the DFP device or the DRP device is configured to 180 mua CCDEBOUNCE A high level continuously output in the range of (2), and a third level is a high level continuously output in the range of (2) for a sustain time t CCDEBOUNCE If the device connection is successful, the DFP device or the DRP device may output a current of 1.5A, and the controller 302 maintains the timing pulse signal SW at a low level.
The fifth level is at the sustain time t when the current source of the DFP apparatus or the DRP apparatus is configured to 80 mua CCDEBOUNCE A high level continuously output in the range of (2), and a fourth level is a high level continuously output in the range of (2) for a sustain time t CCDEBOUNCE If the device connection is successful, the DFP device or the DRP device may output a current of 0.5A, and the controller 302 maintains the timing pulse signal SW at a low level.
The controller 302 knows how much current can be obtained from the DFP device or the DRP device by analyzing the level output by the third comparator U3 or the fourth comparator U4 or the fifth comparator U5, and therefore, the USB Type-C interface circuit provided in this embodiment has the capability of identifying the corresponding broadcast current.
The working principle of the USB Type-C interface circuit of this embodiment will be described in detail below by taking an example that the first signal terminal CC1 is connected to the UPF device.
Fig. 4a is a timing diagram of the insertion of the USB Type-C interface circuit of fig. 4 into a UPF device. Referring to fig. 4 and fig. 4a, before t1, the first signal terminal CC1 of the USB Type-C interface circuit is not connected to the UPF device, and because the timing and the timing pulse signals SW of the first signal terminal CC1 and the second signal terminal CC2 are always the same, when SW is at a high level, both CC1 and CC2 are at a high level, and when SW is at a low level, both CC1 and CC2 are at a low level. If the level of CC1 is higher than the level of CC2, the signal of OUT6 is high before t1 (if the level of CC1 is lower than the level of CC2, the signal of OUT6 is low before t 1). The DIR signal is the OUT6 signal and the exclusive OR gate output of SW, so that before t1 the DIR signal is logically opposite to the SW signal, the DIR signal is low when SW is high and the DIR signal is high when SW is low. Before t1, the CC signal is connected to CC1 when the DIR signal is at a high level, and the output signals OUT1 and OUT2 of the first and second comparators are low because CC1 is at a low level at this time, and the CC signal is connected to CC2 when the DIR signal is at a low level, and the output signals OUT1 and OUT2 of the first and second comparators are high because CC2 is at a high level at this time.
At time t1, supposing that a UPF device is inserted into the first signal terminal CC1, SW is at a high level, the first current source flows through a pull-down resistor of the UFP device, and pulls the level of the first signal terminal CC1 low, at this time, since the CC line is connected with the first signal terminal CC1, that is, the first node voltage is connected to the comparison module, the level of the CC is pulled low, so that the output signals OUT1 and OUT2 of the first comparator jump from the high level to the low level, which indicates that the device connection is successful, at this time, the SW signal level is not changed any more, and the high level is kept continuously. The second signal terminal CC2 continues to remain high since no device is inserted. At this time, the level of CC2 is higher than CC1, and thus the OUT6 signal goes low. The DIR signal is the OUT6 signal and the exclusive or output of the SW signal transitions high.
The working principle of the USB Type-C interface circuit of this embodiment is described in detail below by taking the first signal terminal CC1 connected to the DPF device as an example.
FIG. 4b is a timing diagram of the insertion of the USB Type-C interface circuit of FIG. 4 into a DPF device. Referring to fig. 4 and 4b, before t1, CC1 and CC2 are controlled by SW signals with the same timing as SW, CC1 and CC2 are both high when SW is high, and CC1 and CC2 are both low when SW is low, without device insertion. If the level of CC1 is higher than the level of CC2, then the signal of OUT6 is high before t1 (if the level of CC1 is lower than the level of CC2, then the signal of OUT6 is low before t 1). The DIR signal is the OUT6 signal and the exclusive OR gate output of SW, so before t1, the DIR signal is logically opposite to the SW signal, DIR is low when SW is high, and DIR signal is high when SW is low. Before t1, when DIR is high, the CC signal is connected to CC1, and since CC1 is low at this time, OUT3 output by the third comparator, OUT4 output by the fourth comparator, and OUT5 output by the fifth comparator are all low. When the DIR signal is low, the CC signal is connected to CC2, and the outputs of OUT3, OUT4, OUT5 are all high since CC2 is high.
At time t1, assuming that a DFP device is inserted into the CC1 port, SW is low, the CC1 port is grounded through the Rd1 resistor, and since the DFP device is inserted, the current source of the DFP device will flow through the Rd1 resistor to raise the level of the CC1 port, the raised level is compared with the reference voltages of the third comparator, the fourth comparator and the fifth comparator, when the level of OUT3 is high and the time t is continued CCDEBOUNCE When it is stated that the device has been successfully connected, and the broadcast current capability of the DFP device is identified as 3A. When OUT4 is high and continues t CCDEBOUNCE When it is stated that the device has been successfully connected, and the broadcast current capability of the DFP device is identified as 1.5A. When OUT5 is high and continues t CCDEBOUNCE When it is stated that the device has been successfully connected, and the broadcast current capability of the DFP device is identified as 0.5A. The device connection is successful, at this point the SW signal level is no longer changing, and remains low. The port of CC2 continues to remain low since no device is inserted. At this time, the level of CC1 is higher than CC2, so the OUT6 signal is high. The DIR signal is the OUT6 signal and the exclusive or output of the SW signal transitions high.
The same applies to the operation principle of the second signal terminal CC2 when accessing the UFP or DFP device, which is not described herein.
In this embodiment, on the one hand, the USB Type-C interface circuit may successfully handshake with the external device according to the Type of the external device, that is, identify the UFP device or the DFP device or the DRP device, and on the other hand, the external device may be connected to the first signal end or the second signal end in a random transformation manner, and the USB Type-C interface circuit may respond to the transformation in time, so that the USB Type-C interface circuit identifies the insertion direction of the external device.
Fig. 5 is a schematic structural diagram of an USB Type-C interface circuit according to another embodiment of the present invention. As shown in fig. 5, the comparison module 50 of the present embodiment is different from the above embodiment in that it includes a first single pole double throw switch S1, a first comparator 501, and a second comparator 502.
The first single-pole double-throw switch S1 includes a first switch input end S11, a second switch input end S12, a first switch output end S13, and a first control end S14, where the first switch input end S11 is connected to a first node voltage, the second switch input end S12 is connected to a second node voltage, and the first switch control end S14 is connected to a logic control signal.
The first non-inverting input terminal of the first comparator 501 is connected to the first switch output terminal S13, the first inverting input terminal is connected to the first Type-C standard voltage V1, and the first comparator 501 outputs a first level signal from the first comparison output terminal to the controller according to the first Type-C standard voltage V1 and the first node voltage or according to the first Type-C standard voltage V1 and the second node voltage.
The second inverting input terminal of the second comparator 502 is connected to the first switch output terminal S13, the second non-inverting input terminal is connected to the second Type-C standard voltage V2, and the second comparator 502 outputs a second level signal from the second comparison output terminal to the controller according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage.
When the external device is DFP device or DRP device, the first Type-C standard voltage is 1.23V, and the second Type-C standard voltage is 0.66V, the first level signalTo be at the maintenance time t CCDEBOUNCE If the device is successfully connected, the current outputted by the DFP device or the DRP device is 3A, the controller maintains the time sequence pulse signal at low level, or the first level signal is at the maintaining time t CCDEBOUNCE Outputs a low level in a range of (2), and the second level signal is maintained for a time t CCDEBOUNCE If the device is successfully connected, the DFP device or the DRP device can output a current of 1.5A, and the controller maintains the timing pulse signal at a low level.
When the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, and the second Type-C standard voltage is 0.2V, the first level signal is maintained for a time t CCDEBOUNCE The internal continuous output of high level, the equipment connection is successful, the controller maintains the time sequence pulse signal at low level, or the first level signal is maintained at the time t CCDEBOUNCE Continuously output low level in the range of (2), and the second level signal is at the sustain time t CCDEBOUNCE If the device is successfully connected, the DFP device or the DRP device can output a current of 0.5A, and the controller maintains the timing pulse signal at a low level.
When the external device is UFP device or DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, the first level signal is at the maintaining time t CCDEBOUNCE The second level signal is the high level continuously output in the maintaining time, the equipment is successfully connected, the controller maintains the time sequence pulse signal at the high level and indicates that the current broadcasting capability is 1.5A or 0.5AA, or the first level signal is the high level continuously output in the maintaining time t CCDEBOUNCE Continuously outputting low level in the range of (2), and the second level signal is maintained at time t CCDEBOUNCE If the device is successfully connected, the controller maintains the timing pulse signal at a high level and indicates that the current broadcasting capability at this time is 3AA. If the first level signal is low and the second level signal is also low, this indicates that no device is inserted and that the connection is unsuccessful.
The USB Type-C interface circuit provided by the embodiment not only can identify the Type and the inserting direction of the external equipment, but also can judge the corresponding broadcasting current capability.
Fig. 6 is a schematic block diagram of a USB Type-C interface circuit according to another embodiment of the present invention. As shown in fig. 6, the present embodiment differs from the first embodiment in that: the logic control signal output by the logic circuit does not directly control the comparison module to access the first node voltage or the second node voltage, but the logic circuit generates a first level signal, and the controller receives the first level signal and outputs a second level signal according to the first level signal so as to control the comparison module to access the first node voltage or the second node voltage.
Specifically, the first current source circuit 601 is connected to the first signal terminal CC1 and the controller 602, respectively. The controller 602 outputs a timing pulse signal SW, wherein the timing pulse signal SW is a typical period specified by the Type-C protocol, and specifically, the timing pulse signal SW is a square wave of 75 ms. The second current source circuit 603 is connected to the second signal terminal CC2 and the controller 602, respectively. The first current source circuit 601 and the second current source circuit 603 simultaneously receive the timing pulse signal SW transmitted from the controller 602, and the first current source circuit 601 outputs a first node voltage at the first node 10A connected to the first signal terminal CC1 according to the timing pulse signal SW, and the second current source circuit 603 outputs a second node voltage at the second node 10B connected to the second signal terminal CC2 according to the timing pulse signal SW.
When the first signal terminal CC1 and the second signal terminal CC2 are not connected to the external device, the timing sequence of the first node voltage and the timing sequence of the second node voltage are the same as the timing pulse signal. When the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal is at a high level, the first node voltage jumps from the high level to the low level, and the second node voltage remains at the high level. When the first signal terminal CC1 is connected to the DFP apparatus or the DRP apparatus and the timing pulse signal is at a low level, the first node voltage jumps from the low level to the high level, and the second node voltage remains at the low level. When the second signal terminal CC2 is connected to the UFP device or the DRP device and the timing pulse signal is at a high level, the second node voltage jumps from the high level to the low level, and the first node voltage remains at the high level. When the second signal terminal CC2 is connected to the DFP device or the DRP device and the timing pulse signal is at a low level, the second node voltage jumps from the low level to the high level, and the first node voltage remains at the low level.
The logic circuit 604 is respectively connected to the first node, the second node and the controller 602, and is configured to output a first level signal according to the first node voltage and the second node voltage, and the controller 602 outputs a second level signal according to the first level signal.
The input end of the comparison module 605 is connected with the logic circuit 604, and the output end is connected with the controller 602, and is used for accessing the first node voltage or the second node voltage according to the second level signal. In the process, on one hand, the USB Type-C interface circuit can successfully handshake with external equipment according to the Type of the external equipment, namely, the UFP equipment, the DFP equipment or the DRP equipment is identified, and on the other hand, the external equipment can be connected with the first signal end or the second signal end in a random conversion manner, and the USB Type-C interface circuit can respond to the conversion in time, so that the USB Type-C interface circuit identifies the inserting direction of the external equipment.
When the first signal terminal CC1 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the first level signal output by the logic circuit 604 is a low level signal, so that the second level signal output by the controller 602 is at a high level, and the comparison module 605 is connected to the first node voltage.
When the first signal terminal CC1 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the first level signal output by the logic circuit 604 is a high level signal, so that the second level signal output by the controller 602 is at a high level, and the comparison module 605 is connected to the first node voltage.
When the second signal terminal CC2 is connected to the UFP device or the DRP device and the timing pulse signal SW is at a high level, the first level signal output by the logic circuit 604 is a high level signal, so that the second level signal output by the controller 602 is at a low level, and the comparison module 605 is connected to the second node voltage.
When the second signal terminal CC2 is connected to the DFP device or the DRP device and the timing pulse signal SW is at a low level, the first level signal output by the logic circuit 604 is a low level signal, so that the second level signal output by the controller 602 is at a low level, and the comparison module 605 is connected to the second node voltage.
Fig. 7 is a schematic structural diagram of an USB Type-C interface circuit according to another embodiment of the present invention. As shown in fig. 7, the comparison module 605 includes a first single pole double throw switch S1, a first comparator U1, a second comparator U2, a third comparator U3, a fourth comparator U4, and a fifth comparator U5.
The first single-pole double-throw switch S1 comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with a first node voltage, the second switch input end is connected with a second node voltage, and the first switch control end is connected with a second level signal.
The first inverting input terminal of the first comparator U1 is connected to the first switch output terminal, the first non-inverting input terminal is connected to the first Type-C standard voltage, and the first comparison output terminal outputs the third level to the controller 602.
The second inverting input terminal of the second comparator U2 is connected to the first switch output terminal, the second non-inverting input terminal is connected to the second Type-C standard voltage, and the second comparison output terminal outputs the fourth level to the controller 602.
When the third level is a high level continuously output in the range of the sustain time, the controller 602 maintains the timing pulse signal at the high level; when the fourth level is a high level continuously output in the range of the sustain time, the controller 602 maintains the timing pulse signal at the high level.
The third non-inverting input terminal of the third comparator U3 is connected to the first switch output terminal, the third inverting input terminal is connected to the third Type-C standard voltage, and the third comparison output terminal outputs the fifth level to the controller 602.
The fourth non-inverting input terminal of the fourth comparator U4 is connected to the first switch output terminal, the fourth inverting input terminal is connected to the fourth Type-C standard voltage, and the fourth comparison output terminal outputs the sixth level to the controller 602.
The fifth non-inverting input terminal of the fifth comparator U5 is connected to the first switch output terminal, the fifth inverting input terminal is connected to the fifth Type-C standard voltage, and the fifth comparison output terminal outputs the seventh level to the controller 602.
When the fifth level is a high level continuously output in the range of the sustain time, the controller 602 maintains the timing pulse signal at a low level. When the sixth level is a high level continuously output in the range of the sustain time and the fifth level is a low level continuously output in the range of the sustain time, the controller 602 maintains the timing pulse signal at the low level; when the seventh level is a high level continuously output in the range of the sustain time and the sixth level is a low level continuously output in the range of the sustain time, the controller 602 maintains the timing pulse signal at the low level.
In this embodiment, on the one hand, the USB Type-C interface circuit may successfully handshake with the external device according to the Type of the external device, that is, identify the UFP device or the DFP device or the DRP device, and on the other hand, the external device may be connected to the first signal end or the second signal end in a random transformation manner, and the USB Type-C interface circuit may respond to the transformation in time, so that the USB Type-C interface circuit identifies the insertion direction of the external device.
Fig. 8 is a schematic diagram of a USB Type-C interface circuit according to another embodiment of the present invention. As shown in fig. 8, the present embodiment is different from the above embodiment in that the comparison module 80 of the present embodiment includes a first single pole double throw switch S1, a first comparator 801, and a second comparator 802.
In this embodiment, the first single pole double throw switch S1 includes a first switch input terminal, a second switch input terminal, a first switch output terminal, and a first switch control terminal, where the first switch input terminal is connected to a first node voltage, the second switch input terminal is connected to a second node voltage, and the first switch control terminal is connected to a second level signal.
In this embodiment, a first non-inverting input terminal of the first comparator 801 is connected to the first switch output terminal, the first inverting input terminal is connected to the first Type-C standard voltage, and the first comparator outputs a third level signal from the first comparison output terminal to the controller according to the first Type-C standard voltage and the first node voltage or according to the first Type-C standard voltage and the second node voltage.
The second inverting input terminal of the second comparator 802 is connected to the first switch output terminal, the second non-inverting input terminal is connected to the second Type-C standard voltage, and the second comparator outputs a fourth level signal from the second comparison output terminal to the controller according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage.
When the external device is a DFP device or a DRP device, the first Type-C standard voltage is 1.23V, the second Type-C standard voltage is 0.66V, the third level signal is a high level continuously output in the range of the sustain time, and the controller maintains the timing pulse signal at a low level, or the third level signal is a low level output in the range of the sustain time and the fourth level signal is a high level continuously output in the range of the sustain time, and the controller maintains the timing pulse signal at a low level.
When the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, the second Type-C standard voltage is 0.2V, the third level signal is a high level continuously output in the maintaining time, the controller maintains the timing pulse signal at a low level, or the third level signal is a low level continuously output in the maintaining time range, and the fourth level signal is a high level continuously output in the maintaining time range, the controller maintains the timing pulse signal at a low level.
When the external device is a UFP device or a DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, where the third level signal is a high level continuously output in a maintaining time range, the controller maintains the timing pulse signal at a high level, or the third level signal is a low level continuously output in a maintaining time range, and the fourth level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a high level.
In this embodiment, on the one hand, the USB Type-C interface circuit may successfully handshake with the external device according to the Type of the external device, that is, identify the UFP device or the DFP device or the DRP device, and on the other hand, the external device may be connected to the first signal end or the second signal end in a random transformation manner, and the USB Type-C interface circuit may respond to the transformation in time, so that the USB Type-C interface circuit identifies the insertion direction of the external device.
In various embodiments, the controller may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. Also, the controller herein may be any conventional processor, microprocessor, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The foregoing description is only of embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.

Claims (8)

1. The utility model provides a USB Type-C interface circuit for detect external device, including first signal end and second signal end, its characterized in that includes:
a controller for outputting a timing pulse signal;
the first current source circuit is connected with the controller and is used for outputting a first node voltage at a first node connected with the first signal end according to the time sequence pulse signal;
The second current source circuit is connected with the controller and is used for outputting a second node voltage at a second node connected with the second signal end according to the time sequence pulse signal;
the logic circuit is respectively connected with the first node, the second node and the controller and is used for outputting logic control signals according to the time sequence pulse signals, the first node voltage and the second node voltage;
the input end of the comparison module is connected with the logic circuit, and the output end of the comparison module is connected with the controller and is used for accessing the first node voltage or the second node voltage according to the logic control signal;
when the first signal end and the second signal end are not connected with external equipment, the time sequence of the first node voltage and the time sequence of the second node voltage are the same as the time sequence pulse signals; or alternatively, the process may be performed,
when the first signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is at a high level, the first node voltage jumps from the high level to the low level, and the second node voltage is kept at the high level; or alternatively, the process may be performed,
when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the first node voltage jumps from the low level to the high level, and the second node voltage is kept at the low level; or alternatively, the process may be performed,
When the second signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is at a high level, the second node voltage jumps from the high level to the low level, and the first node voltage keeps at the high level; or alternatively, the process may be performed,
when the second signal end is connected to the DFP equipment or the DRP equipment and the time sequence pulse signal is in a low level, the second node voltage jumps from the low level to the high level, and the first node voltage keeps in the low level.
2. The USB Type-C interface circuit of claim 1, wherein the logic control signals comprise a first logic control signal and a second logic control signal;
when the first signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is in a high level, the logic circuit outputs the first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal; or alternatively, the process may be performed,
when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is in a low level, the logic circuit outputs the first logic control signal, and the comparison module is connected to the first node voltage according to the first logic control signal; or alternatively, the process may be performed,
When the second signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is in a high level, the logic circuit outputs a second logic control signal, and the comparison module is connected to the second node voltage according to the second logic control signal; or alternatively, the process may be performed,
when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is in a low level, the logic circuit outputs the second logic control signal, and the comparison module is connected to the second node voltage according to the second logic control signal.
3. The USB Type-C interface circuit of claim 2, wherein the comparison module comprises:
the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the logic control signal;
the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end of the first comparator is connected with a first Type-C standard voltage, and the first comparison output end outputs a first level to the controller;
The second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparison output end outputs a second level to the controller; when the first level is a high level continuously output in a maintaining time range, the controller maintains the time sequence pulse signal at the high level; when the second level is a high level continuously output in a maintaining time range, the controller maintains the time sequence pulse signal at the high level;
the third non-inverting input end of the third comparator is connected with the first switch output end, the third inverting input end of the third comparator is connected with a third Type-C standard voltage, and the third comparison output end outputs a third level to the controller;
the fourth non-inverting input end of the fourth comparator is connected with the first switch output end, the fourth inverting input end of the fourth comparator is connected with a fourth Type-C standard voltage, and the fourth comparison output end outputs a fourth level to the controller;
the fifth non-inverting input end of the fifth comparator is connected with the first switch output end, the fifth inverting input end of the fifth comparator is connected with a fifth Type-C standard voltage, and the fifth comparison output end outputs a fifth level to the controller; when the third level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the fourth level is a high level continuously output in a range of a sustain time and the third level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the fifth level is a high level continuously output in a range of a sustain time and the fourth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level.
4. The USB Type-C interface circuit of claim 2, wherein the comparison module comprises:
the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the logic control signal;
the first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end is connected with a first Type-C standard voltage, and the first comparator outputs a first level signal to the controller from a first comparison output end according to the first Type-C standard voltage and the first node voltage or according to the first Type-C standard voltage and the second node voltage;
the second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparator outputs a second level signal to the controller from a second comparison output end according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage;
When the external device is a DFP device or a DRP device, the first Type-C standard voltage is 1.23V, and the second Type-C standard voltage is 0.66V, the controller maintains the timing pulse signal at a low level when the first level signal is a high level continuously output in a maintaining time range, or maintains the timing pulse signal at a low level when the first level signal is a low level output in a maintaining time range and the second level signal is a high level continuously output in a maintaining time range; or alternatively, the process may be performed,
when the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, and the second Type-C standard voltage is 0.2V, the first level signal is a high level continuously output in a maintaining time, and the controller maintains the timing pulse signal at a low level, or the first level signal is a low level continuously output in a maintaining time range, and the second level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a low level; or alternatively, the process may be performed,
when the external device is a UFP device or a DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, where the first level signal is a high level continuously output in a maintaining time range, the controller maintains the timing pulse signal at the high level, or the first level signal is a low level continuously output in the maintaining time range, and the second level signal is a high level continuously output in the maintaining time range, and the controller maintains the timing pulse signal at the high level.
5. The utility model provides a USB Type-C interface circuit for detect external device, including first signal end and second signal end, its characterized in that includes:
a controller for outputting a timing pulse signal;
the first current source circuit is connected with the controller and is used for outputting a first node voltage at a first node connected with the first signal end according to the time sequence pulse signal;
the second current source circuit is connected with the controller and is used for outputting a second node voltage at a second node connected with the second signal end according to the time sequence pulse signal;
the logic circuit is respectively connected with the first node, the second node and the controller and is used for outputting a first level signal according to the first node voltage and the second node voltage, and the controller is used for outputting a second level signal according to the first level signal;
the input end of the comparison module is connected with the logic circuit, and the output end of the comparison module is connected with the controller and is used for accessing the first node voltage or the second node voltage according to the second level signal;
when the first signal end and the second signal end are not connected with external equipment, the time sequence of the first node voltage and the time sequence of the second node voltage are the same as the time sequence pulse signals; or alternatively, the process may be performed,
When the first signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is at a high level, the first node voltage jumps from the high level to the low level, and the second node voltage is kept at the high level; or alternatively, the process may be performed,
when the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is at a low level, the first node voltage jumps from the low level to the high level, and the second node voltage is kept at the low level; or alternatively, the process may be performed,
when the second signal end is connected to UFP equipment or DRP equipment and the time sequence pulse signal is at a high level, the second node voltage jumps from the high level to the low level, and the first node voltage keeps at the high level; or alternatively, the process may be performed,
when the second signal end is connected to the DFP equipment or the DRP equipment and the time sequence pulse signal is in a low level, the second node voltage jumps from the low level to the high level, and the first node voltage keeps in the low level.
6. The USB Type-C interface circuit of claim 5, wherein,
when the first signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is in a high level, the first level signal output by the logic circuit is in a low level signal so that the second level signal output by the controller is in a high level, and the comparison module is connected to a first node voltage; or alternatively, the process may be performed,
When the first signal end is connected to a DFP device or a DRP device and the time sequence pulse signal is in a low level, the first level signal output by the logic circuit is in a high level signal so that the second level signal output by the controller is in a high level, and the comparison module is connected to a first node voltage; or alternatively, the process may be performed,
when the second signal end is connected to the UFP device or the DRP device and the time sequence pulse signal is in a high level, the first level signal output by the logic circuit is in a high level signal so that the second level signal output by the controller is in a low level, and the comparison module is connected to a second node voltage; or alternatively, the process may be performed,
when the second signal end is connected to the DFP device or the DRP device and the time sequence pulse signal is in a low level, the first level signal output by the logic circuit is in a low level signal, so that the second level signal output by the controller is in a low level, and the comparison module is connected to a second node voltage.
7. The USB Type-C interface circuit of claim 6, wherein the comparison module comprises:
the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the second level signal;
The first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end of the first comparator is connected with a first Type-C standard voltage, and the first comparison output end outputs a third level to the controller;
the second inverting input end of the second comparator is connected with the output end of the first switch, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparison output end outputs a fourth level to the controller; when the third level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a high level; when the fourth level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a high level;
the third non-inverting input end of the third comparator is connected with the first switch output end, the third inverting input end of the third comparator is connected with a third Type-C standard voltage, and the third comparison output end outputs a fifth level to the controller;
the fourth non-inverting input end of the fourth comparator is connected with the output end of the first switch, the fourth inverting input end of the fourth comparator is connected with a fourth Type-C standard voltage, and the fourth comparison output end outputs a sixth level to the controller;
The fifth non-inverting input end of the fifth comparator is connected with the first switch output end, the fifth inverting input end of the fifth comparator is connected with a fifth Type-C standard voltage, and the fifth comparison output end outputs a seventh level to the controller; when the fifth level is a high level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the sixth level is a high level continuously output in a range of a sustain time and the fifth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level; when the seventh level is a high level continuously output in a range of a sustain time and the sixth level is a low level continuously output in a range of a sustain time, the controller maintains the timing pulse signal at a low level.
8. The USB Type-C interface circuit of claim 6, wherein the comparison module comprises:
the first single-pole double-throw switch comprises a first switch input end, a second switch input end, a first switch output end and a first switch control end, wherein the first switch input end is connected with the first node voltage, the second switch input end is connected with the second node voltage, and the first switch control end is connected with the second level signal;
The first inverting input end of the first comparator is connected with the first switch output end, the first inverting input end is connected with a first Type-C standard voltage, and the first comparator outputs a third level signal to the controller from the first comparing output end according to the first Type-C standard voltage and the first node voltage or according to the first Type-C standard voltage and the second node voltage;
the second inverting input end of the second comparator is connected with the first switch output end, the second non-inverting input end of the second comparator is connected with a second Type-C standard voltage, and the second comparator outputs a fourth level signal to the controller from a second comparison output end according to the second Type-C standard voltage and the first node voltage or according to the second Type-C standard voltage and the second node voltage;
when the external device is a DFP device or a DRP device, the first Type-C standard voltage is 1.23V, and the second Type-C standard voltage is 0.66V, the controller maintains the timing pulse signal at a low level when the third level signal is a high level continuously output in a range of a maintaining time, or maintains the timing pulse signal at a low level when the third level signal is a low level output in a range of a maintaining time and the fourth level signal is a high level continuously output in a range of a maintaining time, and maintains the timing pulse signal at a low level; or alternatively, the process may be performed,
When the external device is a DFP device or a DRP device, the first Type-C standard voltage is 0.66V, and the second Type-C standard voltage is 0.2V, the third level signal is a high level continuously output in a maintaining time, and the controller maintains the timing pulse signal at a low level, or the third level signal is a low level continuously output in a maintaining time range, and the fourth level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a low level; or alternatively, the process may be performed,
when the external device is a UFP device or a DRP device, the first Type-C standard voltage is 1.6V, and the second Type-C standard voltage is 2.6V, where the third level signal is a high level continuously output in a maintaining time range, the controller maintains the timing pulse signal at a high level, or the third level signal is a low level continuously output in a maintaining time range, and the fourth level signal is a high level continuously output in a maintaining time range, and the controller maintains the timing pulse signal at a high level.
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