CN211375595U - Solid state disk recognition device - Google Patents
Solid state disk recognition device Download PDFInfo
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- CN211375595U CN211375595U CN201922481292.6U CN201922481292U CN211375595U CN 211375595 U CN211375595 U CN 211375595U CN 201922481292 U CN201922481292 U CN 201922481292U CN 211375595 U CN211375595 U CN 211375595U
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Abstract
The application discloses solid state hard drives recognition device, recognition device includes: the first signal transceiving end of the CPU module is connected to the second signal transceiving end of the M.2 interface module, a coupling capacitor module is connected in series between the first signal transceiving end and the second signal transceiving end, and the coupling capacitor module is used for isolating direct current signals between the first signal transceiving end and the second signal transceiving end; the first detection interface of the identification module is connected to the protocol level output end of the M.2 interface module, the second detection interface of the identification module is connected to the equipment insertion identification end of the M.2 interface module, the first output end of the identification module is connected to the mode identification end of the CPU module, and the second output end of the identification module is connected to the insertion identification end of the CPU module, wherein when the first isolation transistor Q2 is switched on, the CPU module judges that the M.2 interface module is provided with the solid state disk in an inserted mode. According to the technical scheme, the interface protocol adopted by the inserted solid state disk is automatically identified, and the utilization efficiency of CPU interface resources is improved.
Description
Technical Field
The application relates to the technical field of computer equipment, in particular to a solid state disk identification device.
Background
The Intel introduced an m.2 interface, which is a novel host interface scheme, and is compatible with multiple communication protocols, and for a Solid State Disk (SSD), two common protocol modes are: PCIe mode and SATA mode, and therefore, a solid state disk with a server compatible with these two protocol modes is required.
In the prior art, the CPU in the server usually identifies the protocol mode of the inserted solid state disk by an external signal channel switching chip, and then switches the signal channel of the CPU, which cannot realize automatic identification of the protocol mode of the solid state disk by the CPU. The method not only increases the area and the design cost of the PCB mainboard of the server, but also wastes the interface resources of the CPU.
SUMMERY OF THE UTILITY MODEL
The purpose of this application lies in: the interface protocol adopted by the inserted solid state disk is automatically identified, and the utilization efficiency of CPU interface resources is improved.
The technical scheme of the application is as follows: provided is a solid state disk recognition device, including: the system comprises a CPU module, an M.2 interface module, a coupling capacitor module and an identification module; the first signal transceiving end of the CPU module is connected to the second signal transceiving end of the M.2 interface module, a coupling capacitor module is connected in series between the first signal transceiving end and the second signal transceiving end, and the coupling capacitor module is used for isolating direct current signals between the first signal transceiving end and the second signal transceiving end; the first detection interface of identification module connects in M.2 interface module's protocol level output, identification module's second detection interface connects in M.2 interface module's equipment inserts the discernment end, identification module's first output is connected in CPU module's mode identification end, identification module's second output is connected in CPU module's insertion discernment end, wherein, it has first isolation transistor Q2 to establish ties between second detection interface and the second output, when first isolation transistor Q2 switched on, CPU module judges to insert on the M.2 interface module and is equipped with solid state hard disk.
In any of the above technical solutions, further, the second detection interface of the m.2 interface module is further connected to the first power supply P3V3 through a resistor R6; the insertion identification end of the CPU module is also connected to the second power supply PVGPIO through a resistor R5.
In any one of the above technical solutions, further, the identification module further includes: a logic and module U1 and a second isolation transistor Q1; a first input terminal of the logical and module U1 is connected to the first detection interface, a second input terminal of the logical and module U1 is connected to the third power supply P3V3_ VSB through a resistor R2, an output terminal of the logical and module U1 is connected to an input terminal of a second isolation transistor Q1, and the logical and module U1 is configured to perform an and operation; the output terminal of the second isolation transistor Q1 is connected to the mode identification terminal of the CPU block.
In any of the above technical solutions, further, the output terminal of the and logic module U1 is further connected to the first power supply P3V3 through a resistor R3; the output terminal of the second isolation transistor Q1 is also connected to the second power supply PVGPIO through a resistor R4.
In any of the above technical solutions, further, the first input terminal of the and logic module U1 is further connected to the first power supply P3V3 through a resistor R1.
In any one of the above technical solutions, further, the identification apparatus further includes: a power supply module; the power module is connected in series between a power supply control end of the CPU module and a power supply end of the M.2 interface module, the power module comprises an N-type transistor Q3 and a P-type transistor Q4 which are connected in series, the power supply control end of the CPU module is used for sending a conducting signal to the N-type transistor Q3 to control the conduction of the N-type transistor Q3 and the P-type transistor Q4, and after the P-type transistor Q4 is conducted, the power supply end of the M.2 interface module is conducted with a third power supply P3V3_ VSB.
The beneficial effect of this application is:
according to the technical scheme, the PRSNT pin in the M.2 interface module is used as a device insertion identification end, the PEDET pin is used as a protocol level output end, the high and low voltages of pin input signals are different, simple logic operation is adopted, the interface protocol of the solid state disk is identified, and by arranging a logic and module U1, false operation in the identification process is prevented, and the identification reliability and the utilization efficiency of CPU interface resources are improved.
Drawings
The advantages of the above and/or additional aspects of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a solid state disk identification apparatus according to one embodiment of the present application;
FIG. 2 is a schematic diagram of an M.2 interface module according to one embodiment of the present application;
FIG. 3 is a schematic diagram of interface protocol type detection logic according to one embodiment of the present application.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, the present application will be described in further detail with reference to the accompanying drawings and detailed description. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, however, the present application may be practiced in other ways than those described herein, and therefore the scope of the present application is not limited by the specific embodiments disclosed below.
The present embodiment will be described below with reference to fig. 1 and 2.
In this embodiment, a marine Dhyana type CPU is taken as an example for description.
As shown in fig. 1, the present embodiment provides an identification apparatus for a solid state disk, where the identification apparatus includes: the CPU module 10, the M.2 interface module 20, the coupling capacitor module 40 and the identification module 30; a first signal transceiving end of the CPU module 10 is connected to a second signal transceiving end of the m.2 interface module 20, a coupling capacitor module 40 is connected in series between the first signal transceiving end and the second signal transceiving end, and the coupling capacitor module 40 is used for isolating a direct current signal between the first signal transceiving end and the second signal transceiving end;
specifically, since the PCIE interface protocol and the SATA interface protocol are both 85ohm differential impedances on the hardware connection line, the same impedance on the layout can be achieved, and the coupling capacitance of the PCIE interface protocol is 175nf to 265nf, and the coupling capacitance of the SATA interface protocol is 10nf, therefore, the coupling capacitance module 40 is disposed between the CPU module 10 and the transceiving end of the m.2 interface module 20, which mainly functions to block direct current and alternating current, and in this embodiment, four capacitors of 220nf are selected as four series capacitors in the coupling capacitance module 40.
The first detection interface of the identification module 30 is connected to the protocol level output end of the m.2 interface module 20, the second detection interface of the identification module 30 is connected to the device insertion identification end of the m.2 interface module 20, the first output end of the identification module 30 is connected to the mode identification end of the CPU module 10, the second output end of the identification module 30 is connected to the insertion identification end of the CPU module 10, wherein a first isolation transistor Q2 is connected in series between the second detection interface and the second output end, and when the first isolation transistor Q2 is turned on, the CPU module 10 determines that a solid state disk is inserted into the m.2 interface module 20.
Specifically, as shown in fig. 2, for the m.2 interface module 20, according to the m.2 protocol, the pin 69# is used to identify the interface protocol of the solid state disk, and when the pin 69# is at a low level (PEDET pin), it is corresponding to a PCIE interface protocol at this time; when the level is high, the SATA interface protocol is corresponded. The pin 67# of the m.2 interface module 20 (PRSNT pin) can be used to identify whether a solid state disk is inserted, so that the pin 69# is used as a protocol level output terminal to be connected to the first detection interface of the identification module 30, and the pin 67# is used as a device insertion identification terminal to be connected to the second detection interface of the identification module 30.
Correspondingly, a pin of GPIO01 of the CPU module 10 is used as an insertion identification terminal to detect whether a solid state disk is inserted at the CPU side, and a pin of GPIO00 of the CPU module 10 is used as a mode identification terminal to detect the interface protocol type of the solid state disk.
As shown in fig. 3, after powering on, the CPU module 10 first detects a high-low level of the pin 67# of the m.2 interface module 20, and when it is determined that the high level is high, it indicates that a solid state disk is inserted, and then detects a high-low level of the pin 69# of the m.2 interface module 20, and when it is determined that the high level is high, it indicates that an interface protocol of the inserted solid state disk is an SATA interface protocol.
Further, the second detection interface of the m.2 interface module 20 is further connected to the first power supply P3V3 through a resistor R6; the insertion identification terminal of the CPU module 10 is further connected to a second power supply PVGPIO through a resistor R5, where the second power supply PVGPIO is a power supply of the general-purpose I/O interface.
Specifically, the resistor R6 is used as a pull-up resistor, and the default state of the second detection interface of the m.2 interface module 20 is a high level through the first power supply P3V3, and the second power supply PVGPIO maintains the insertion identification terminal (GPIO01) of the CPU module 10 in a default level state through the resistor R5.
Further, in order to simplify the hardware circuit of the identification module 30 and improve the reliability of the identification module 30, the identification module 30 further includes: a logic and module U1 and a second isolation transistor Q1; a first input terminal of the and logic block U1 is connected to the first detection interface, a second input terminal of the and logic block U1 is connected to the third power supply P3V3_ VSB through a resistor R2, an output terminal of the and logic block U1 is connected to an input terminal of a second isolation transistor Q1, and the and logic block U1 is configured to perform an and operation, wherein the first input terminal of the and logic block U1 is further connected to the first power supply P3V3 through a resistor R1;
specifically, in this embodiment, the logical and module U1 is introduced as a main logical module for interface protocol detection, one end of the logical and module U1 is connected to the third power supply P3V3_ VSB through the resistor R2, only when the PEDET terminal (protocol level output terminal) of the m.2 interface 20 outputs a high level, the logical and module U1 outputs a high level, and controls the second isolation transistor Q1 to be turned on while preventing malfunction, and outputs a high voltage signal, which indicates that the protocol is the SATA interface protocol at this time.
The output terminal of the second isolation transistor Q1 is connected to the mode identification terminal of the CPU block 10, wherein the output terminal of the and logic block U1 is further connected to the first power supply P3V3 through a resistor R3; the output terminal of the second isolation transistor Q1 is also connected to the second power supply PVGPIO through a resistor R4.
Specifically, the resistor R3 and the resistor R4 are pull-up resistors, and provide corresponding high-level signals. In this embodiment, when the logic and module U1 outputs a high level, the second isolation transistor Q1 is turned on, and transmits a high level signal to the mode identification terminal (GPIO00) of the CPU module 10, and the CPU module 10 identifies the high level signal, and further determines that the interface protocol of the inserted solid state disk is the SATA interface protocol, otherwise, the second isolation transistor Q1 is turned off, and the mode identification terminal of the CPU module 10 is a low level, and determines that the interface protocol of the solid state disk is the PCIe interface protocol.
Further, the identification apparatus further includes: a power supply module; the power module is connected in series between the power supply control terminal of the CPU module 10 and the power supply terminal of the m.2 interface module 20, the power module includes an N-type transistor Q3 and a P-type transistor Q4 connected in series, the power supply control terminal of the CPU module 10 is configured to send a turn-on signal to the N-type transistor Q3 to control the N-type transistor Q3 and the P-type transistor Q4 to be turned on, and after the P-type transistor Q4 is turned on, the power supply terminal of the m.2 interface module 20 is turned on with the third power supply P3V3_ VSB.
Specifically, the power supply of the m.2 interface module 20 needs to be controlled by the CPU module 10, so that the SLP _ S5 pin in the CPU module 10 is selected, and the resistor R7 is a pull-up resistor, which ensures that the potential at this point can be pulled up when the CPU module 10 is powered on. And the control of the power supply of the m.2 interface module 20 is realized by arranging an N-type transistor Q3 and a P-type transistor Q4.
The automatic identification test of the fixed hard disk interface protocol is carried out by the marine light dhyan type CPU in the embodiment, the CPU has the characteristics of high bandwidth and low time delay, and has 128 PCIE Lanes, wherein a base pin for multiplexing PCIE signals and SATA signals exists, and a physical basis is provided for automatically identifying M.2 interface insertion equipment.
The test shows that the automatic identification function in the embodiment is normal, the SI eye diagram is adopted to perform the signal integrity test, the PCIE interface protocol and the SATA interface protocol both pass, and no disc loss occurs during the stability test. Through the test, the identification device in the embodiment can automatically and accurately identify the interface protocol type of the inserted solid state disk, and has strong practicability.
The technical solution of the present application is described in detail above with reference to the accompanying drawings, and the present application provides a solid state disk identification device, which includes: the first signal transceiving end of the CPU module is connected to the second signal transceiving end of the M.2 interface module, a coupling capacitor module is connected in series between the first signal transceiving end and the second signal transceiving end, and the coupling capacitor module is used for isolating direct current signals between the first signal transceiving end and the second signal transceiving end; the first detection interface of the identification module is connected to the protocol level output end of the M.2 interface module, the second detection interface of the identification module is connected to the equipment insertion identification end of the M.2 interface module, the first output end of the identification module is connected to the mode identification end of the CPU module, and the second output end of the identification module is connected to the insertion identification end of the CPU module, wherein when the first isolation transistor Q2 is switched on, the CPU module judges that the M.2 interface module is provided with the solid state disk in an inserted mode. According to the technical scheme, the interface protocol adopted by the inserted solid state disk is automatically identified, and the utilization efficiency of CPU interface resources is improved.
In the present application, the terms "mounted," "connected," "fixed," and the like are used in a broad sense, and for example, "connected" may be a fixed connection, a detachable connection, or an integral connection; "coupled" may be direct or indirect through an intermediary. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The shapes of the various elements in the drawings are illustrative and do not preclude the existence of certain differences from the actual shapes, and the drawings are used for the purpose of illustrating the principles of the present application and are not intended to limit the present application.
Although the present application has been disclosed in detail with reference to the accompanying drawings, it is to be understood that such description is merely illustrative and not restrictive of the application of the present application. The scope of the present application is defined by the appended claims and may include various modifications, adaptations, and equivalents of the subject application without departing from the scope and spirit of the present application.
Claims (6)
1. An identification device for a solid state disk, the identification device comprising: the system comprises a CPU module (10), an M.2 interface module (20), a coupling capacitor module (40) and an identification module (30);
a first signal transceiving end of the CPU module (10) is connected to a second signal transceiving end of the m.2 interface module (20), the coupling capacitor module (40) is connected in series between the first signal transceiving end and the second signal transceiving end, and the coupling capacitor module (40) is used to isolate a direct current signal between the first signal transceiving end and the second signal transceiving end;
the first detection interface of identification module (30) connect in the protocol level output of M.2 interface module (20), the second detection interface of identification module (30) connect in the equipment of M.2 interface module (20) inserts the discernment end, the first output of identification module (30) connect in the mode identification end of CPU module (10), the second output of identification module (30) connect in the insertion discernment end of CPU module (10), wherein, the second detect the interface with it has first isolation transistor Q2 to establish ties between the second output, when first isolation transistor Q2 switches on, CPU module (10) judge it is equipped with the solid state hard disk to insert on M.2 interface module (20).
2. The solid state disk identification device of claim 1 wherein the second detection interface of the m.2 interface module (20) is further connected to a first power supply P3V3 through a resistor R6;
the insertion identification end of the CPU module (10) is also connected to a second power supply PVGPIO through a resistor R5.
3. The solid state disk identification device of claim 2, wherein the identification module (30) further comprises: a logic and module U1 and a second isolation transistor Q1;
a first input terminal of the and logic block U1 is connected to the first detection interface, a second input terminal of the and logic block U1 is connected to a third power supply P3V3_ VSB through a resistor R2, an output terminal of the and logic block U1 is connected to an input terminal of the second isolation transistor Q1, and the and logic block U1 is configured to perform an and operation;
the output terminal of the second isolation transistor Q1 is connected to the mode identification terminal of the CPU module (10).
4. The solid state disk identification device of claim 3 wherein the output of the logical and module U1 is further connected to the first power supply P3V3 through a resistor R3;
the output end of the second isolation transistor Q1 is further connected to the second power supply PVGPIO through a resistor R4.
5. The solid state disk identification device of claim 3 wherein the first input of the logical and module U1 is further connected to the first power supply P3V3 through a resistor R1.
6. The solid state disk identification device of any of claims 1 to 5, further comprising: a power supply module;
the power module is connected in series between a power supply control end of the CPU module (10) and a power supply end of the M.2 interface module (20), the power module comprises an N-type transistor Q3 and a P-type transistor Q4 which are connected in series, the power supply control end of the CPU module (10) is used for sending a conducting signal to the N-type transistor Q3 to control the conduction of the N-type transistor Q3 and the P-type transistor Q4, and after the P-type transistor Q4 is conducted, the power supply end of the M.2 interface module (20) is conducted with a third power supply P3V3_ VSB.
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| CN201922481292.6U CN211375595U (en) | 2019-12-31 | 2019-12-31 | Solid state disk recognition device |
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| CN201922481292.6U CN211375595U (en) | 2019-12-31 | 2019-12-31 | Solid state disk recognition device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114385527A (en) * | 2021-12-31 | 2022-04-22 | 南京微智新科技有限公司 | Hard disk compatible platform, mainboard and control method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114385527A (en) * | 2021-12-31 | 2022-04-22 | 南京微智新科技有限公司 | Hard disk compatible platform, mainboard and control method |
| CN114385527B (en) * | 2021-12-31 | 2024-07-02 | 南京微智新科技有限公司 | Control method and main board of hard disk compatible platform |
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