CN104734688A - Programmable impedance transmitter for serial communication - Google Patents
Programmable impedance transmitter for serial communication Download PDFInfo
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- CN104734688A CN104734688A CN201410858178.XA CN201410858178A CN104734688A CN 104734688 A CN104734688 A CN 104734688A CN 201410858178 A CN201410858178 A CN 201410858178A CN 104734688 A CN104734688 A CN 104734688A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
Abstract
Embodiments include apparatuses, methods, and systems for transmitting a data signal over one or more transmission lines. In one embodiment, a transmitter circuit includes a plurality of programmable impedance driver (PID) circuits coupled in parallel with one another to drive a data signal on a transmission line. The individual PID circuits may include a pull-up transistor to receive a pull-up signal, a pull-down transistor to receive a pull-down signal, and first and second resistors coupled in series with one another between the pull-up and pull-down transistors. An output contact may be coupled to a node between the first and second resistors to pass an output signal that is responsive to the pull-up and pull-down signals. The individual PID circuits may further include a switch transistor coupled in parallel with the first and second resistors, and a control contact coupled to the switch transistor to receive a control signal to switch the switch transistor on or off to control an impedance at the output contact.
Description
Technical field
Embodiments of the invention relate in general to electronic circuit technology field, in particular to programmable resistance transmitter circuit.
Background technology
Here the object providing background to describe is that entirety presents the background of invention.The current work being called inventor, the content described by this background parts and other do not regard as the explanation of the prior art in the applying date in scope in, both indefinite also impliedly accreditation for for prior art of the present invention.Unless referred else herein, the scheme described by this part is not prior art for the claim of present disclosure, is not recognized as the prior art included by this part.
Voltage mode high speed I/O (HSIO) transmitter typically comprises driver bit slice (bit-slice) array, and this array is in order to driving data signal on one or more transmission line.This transmitter is by enable or forbid certain driver bit slice and provide programmable impedance output.Therefore, adjustable output impedance carrys out the change of compensate for process, voltage and temperature (PVT) and meets the impedance specification that I/O is connected.But the typical structure of HSIO transmitter has several shortcoming, such as weld tabs capacitance (Cpad) is large, and power consumption is high, and impedance-compensated be associated with operation of postemphasising (such as, one affects another operation).
Accompanying drawing explanation
By the detailed description easy understand embodiments of the invention below in conjunction with accompanying drawing.In order to contribute to understanding this specification, similar Reference numeral represents similar structure.Embodiment is illustrated by the mode of example, not by the restriction of each width figure in accompanying drawing.
Fig. 1 schematically shows the transmitter circuit according to each embodiment.
Fig. 2 illustrates an example of programmable resistance driver (PID) circuit that can be adopted by the transmitter circuit of Fig. 1 according to each embodiment.
Fig. 3 illustrates another PID practical circuit that can be adopted by the transmitter circuit of Fig. 1 according to each embodiment.
Fig. 4 illustrates the impedance-compensated table according to each embodiment.
Fig. 5 shows the deaccentuator according to each embodiment.
Fig. 6 shows the system example being configured to apply apparatus and method as herein described according to each embodiment.
Embodiment
In the following detailed description, with reference to accompanying drawing, wherein accompanying drawing forms the part described in detail, and wherein similar Reference numeral represents similar parts in the text, and is wherein illustrated by the mode of the illustrative examples that can put into practice.Should be appreciated that, only otherwise depart from the scope of the present invention, other embodiment can be adopted, and change that is structural or logicality can be carried out.Therefore, detailed description is below not restrictive, sense, and the scope of embodiment limits by claims and their equivalent.
To contribute to most the mode of theme required for protection, each is operated the multiple discrete movement or operation that are described as successively.But the order of description should not be construed as these operations of hint and must be correlated with by order.Particularly, these operations can not perform with presented order.Described operation can be different from described embodiment order carry out.In other embodiments, other operation multiple can be performed, and/or described operation can be omitted.
For present disclosure, phrase " A and/or B " and " A or B " represent, (A), (B), or (A and B).For present disclosure, phrase " A, B, and/or C " represents (A), (B), (C), (A and B), (A and C); (B and C), or (A, B and C).
This specification can adopt phrase " in one embodiment ", or " in various embodiments ", its each can refer to one or more identical or different embodiment.In addition, the term that each embodiment for present disclosure uses " comprises ", and " comprising ", " having " etc. is synonym.
As used herein, term " module " can refer to, it is a part for following parts, or comprise: application-specific integrated circuit (ASIC) (ASIC), electronic circuit, performs the processor (shared, special, or group) of one or more software or firmware program and/or memory (shared, special or group), combinational logic circuit, and/or other hardware be applicable to that described function is provided.As used herein, " method that computer performs " can refer to by one or more processor, there is the computer system of one or more processor, such as smart phone (it can comprise one or more processor), panel computer, notebook computer, Set Top Box, any method of the mobile device execution of game machine etc.
Fig. 1 shows the transmitter circuit 100 according to each embodiment.This transmitter circuit 100 can be coupled on one or more transmission line 104a-b, to drive the data-signal on this one or more transmission line 104a-b.Transmitter circuit 100 can be coupled to and/or be included in communication apparatus, to make this communication apparatus by transmission line 104a-b to another communication apparatus transmission of data signals.In various embodiments, transmission line 104a-b can transmit serial data signal.Transmitter circuit 100 can be high speed I/O (HSIO) transmitter, and any suitable serial communication protocol can be used, such as camera serial line interface (CSI), mobile industrial processor interface (MIPI) M-PHY, Peripheral Component Interconnect at a high speed (PCIe), Serial Advanced Technology Attachment, and/or USB (USB).
In certain embodiments, transmitter circuit 100 can transmit differential data signals.In these embodiments, transmitter circuit can drive positive data signal Vo+ (such as on the first transmission line 104a, the half of this differential data signals), the second transmission line 104b drives negative data signal Vo-(such as, this differential data signals second half).In certain embodiments, other transmission line can be coupling between communication apparatus, such as, for transmitting ground signalling and/or electrical power.In certain embodiments, transmission line 104a-104b can be the partial cables be connected between communication apparatus at least partially.
In other embodiments, transmitter circuit 100 can transmit single ended data signal on wall scroll transmission line.
In various embodiments, transmitter circuit 100 can comprise multiple bit slice drive circuit 108a-c.Transmitter circuit 100 can comprise the bit slice drive circuit of any applicable quantity.Single bit slice drive circuit 108a-c can comprise the first programmable resistance driver (PID) the circuit 112a-c (also referred to as positive PID circuit 112a-c) being coupled to the first transmission line 104a and the 2nd PID circuit 112d-f (also referred to as negative PID circuit 112d-f) being coupled to the second transmission line 104b.PID circuit 112a-f can drive the output signal on every transmission lines 104a-b.In various embodiments, PID circuit 112a-f can be the driver of voltage mode.
Positive PID circuit 112a-c can be connected in parallel to each other coupling, and is coupled on the first transmission line 104a, to drive positive data signal Vo+.Negative PID circuit 112d-f can be connected in parallel to each other coupling, and is coupled on the second transmission line 104b, to drive negative data signal Vo-.
In various embodiments, transmitter circuit 100 also can comprise the multiple driver logic unit 116a-c be coupled on respective bit slice drive circuit 108a-c.Driver logic unit 116a-c can be received in the input data signal of transmission on transmission line 104a-b, and can produce one or more drive singal, to control the voltage level of the output signal produced by single PID circuit based on this input data signal.Such as, driver logic unit 116a-c can produce the positive pull-up signal (P_up) of the output voltage increasing positive PID circuit 112a-c, in order to reduce the positive pulldown signal (P_dn) of the output voltage of positive PID circuit 112a-c, in order to increase the negative pull-up signal (N_up) of the output voltage of negative PID circuit 112d-f, in order to reduce the negative pulldown signal (N_dn) of the output voltage of negative PID circuit 112d-f.Below with reference to Fig. 2 and 3, the operation of PID circuit 112a-f in response to this drive singal is discussed further.
In various embodiments, transmitter circuit 100 also can comprise deaccentuator 118, in order to perform to the data-signal of just input operation of postemphasising before this input data signal is sent to driver logic unit 116a-c.Postemphasis in operation at this, deaccentuator 118 can by the delay of input data signal and anti-phase distortion sends the driver logic unit 116a-c of programmable number to.The quantity receiving the delay of this input data signal the driver logic unit 116a-c of anti-phase distortion can be selected, to realize multiple of postemphasising in level of the output signal of transmission on transmission line 104a-b.To the operation of postemphasising of postemphasising in logical one 18 be discussed further for Fig. 5 below.
In various embodiments, the impedance that single PID circuit 112a-f presents can respond one or more control signal of PID circuit 112a-f reception and switch between two or more value.Therefore, the output impedance by regulating the impedance of single bit slice drive circuit 112a-c or 112d-f to present on transmission line 104a or 104b to regulate transmitter circuit 100 respectively.
In various embodiments, transmitter circuit 100 can comprise R-comp logical one 20, in order to control the impedance of single PID circuit.In order to the convenience demonstrated, R-comp logical one 20 is depicted as and is coupled on bit slice drive circuit 108c, but it is evident that, R-comp logical one 20 can be coupled on multiple bit slice drive circuit 108a-c, to control each PID circuit 112a-f.In certain embodiments, transmitter circuit 100 also can comprise the R-comp decoder 124 be coupling between R-comp logical one 20 and PID circuit 112a-f, and the R-comp code in order to produce according to R-comp logical one 20 produces the control signal of Control PID circuit 112a-f.That discusses that R-comp logical one 20 and R-comp decoder 124 provide below further is impedance-compensated.
Fig. 2 shows the example of the PID circuit 200 according to each embodiment.In certain embodiments, PID circuit 200 can be included in the PID circuit 112a-f of transmitter circuit 100.
PID circuit 200 can comprise pull up transistor 204 and pull-down transistor 208.PID circuit 200 also can be included in the first resistor 212 and the second resistor 216 coupled in series with one another between 204 and pull-down transistor 208 that pull up transistor.Such as, the first resistor 212 can be coupled to pull up transistor 204 drain terminal, the second resistor 216 can be coupled to the source terminal of pull-down transistor 208.First resistor 212 and the second resistor 216 can have identical resistance (R).Pull up transistor 204 can be coupled to power contact 218 (such as, pull up transistor 204 source terminal), to receive supply voltage (Vreg).Pull-down transistor 208 can be coupling to ground voltage 220 (such as, at the drain terminal of pull-down transistor 208).
204 gate terminals that can pull up transistor at this that pull up transistor receive pull-up signal by pull-up contact 224, wherein this pull-up contact 224 be coupled to pull up transistor 204 gate terminal.This pull-up signal can be such as, P_up or N_up produced according to this input data signal by the drive circuit 116a-c of transmitter circuit 100.Pull-down transistor 204 can receive pulldown signal at the gate terminal of this pull-down transistor 208 by drop-down contact 228, and the gate terminal of pull-down transistor 208 is coupled in this drop-down contact 228.Pulldown signal can be such as P_dn or N_dn produced according to this input data signal by the drive circuit 116a-c of transmitter circuit 100.
In various embodiments, PID circuit 200 can comprise output contact 232, and this output contact 232 is coupled on the node 236 between the first resistor 212 and the second resistor 216.PID circuit 200 can produce output signal according to this pull-up signal and pulldown signal, and can transmit this and output signal to output contact 232.Such as, this pull-up signal optionally conducting this pull up transistor 204, thus output contact 232 conducting is connected on power contact 216, because this increasing the voltage of output signal.Pulldown signal is this pull-down transistor 208 of conducting optionally, to be connected on ground voltage 220 by output contact 232 conducting, because this reducing the voltage of output signal.
PID circuit 200 also can comprise the switching transistor 240 with this first resistor 212 and the second resistor 216 parallel coupled.Such as, the source terminal of switching transistor 240 can be coupled on the first resistor 212 and the node 244 that pulls up transistor between 204, and the drain terminal of switching transistor 240 can be coupled on the node 248 between the second resistor 212 and pull-down transistor 208.Control the gate terminal that switching transistor 240 can be coupled in contact 252, with reception control signal.This control signal can conducting or shutdown switch transistor 240, to control the output impedance on output contact 232.
In various embodiments, the impedance of PID circuit 200 can switch between high impedance and Low ESR in response to this control signal.Such as, when switching transistor 240 turns off, the output impedance on output contact 232 can equal the impedance (and impedance of the second resistor 216) of the first resistor 212, such as R.When switching transistor 240 conducting, the output impedance on output contact 232 can equal the half (and half of the second resistor 216 impedance) of the first resistor 212 impedance, such as R/2.
In various embodiments, for the transmitter circuit 100 comprising multiple PID circuit 200, R-comp logical one 20 is by controlling the single switch transistor 240 of multiple PID circuit 200 (such as, each control signal produced by R-comp logical one 20 is adopted according to the R-comp code that R-comp logic produces), carry out the overall impedance that controlled transmitter presents on the transmission line.Such as, R-comp logical one 20 can realize the desired output impedance that presented by transmitter circuit 100 by Control PID circuit 200.In certain embodiments, impedance on transmission line 104a and/or 104b and reference impedance can compare by R-comp logical one 20, and can conducting or turn off one or more switching transistor 240, thus realize output impedance and approximate reference impedance, wherein this reference impedance approximates desired output impedance.
Fig. 3 schematically shows another example of the PID circuit 300 according to each embodiment.PID circuit 300 can be included in the PID circuit 112a-f of transmitter circuit 100.PID circuit 300 can comprise multiple impedance control unit 302a-d, and each impedance control unit 302a-d can switch between high impedance and Low ESR.
Single impedance control unit 302a-d can comprise the 304a-d that pulls up transistor, pull-down transistor 308a-d, first resistor 312, second resistor 316, and switching transistor 340, itself and PID circuit 200 pull up transistor 204, pull-down transistor 208, first resistor 212, second resistor 216 and switching transistor 240 are distinguished similar.The gate terminal of whole 304a-d that pulls up transistor can be coupled on pull-up contact 324, to receive pull-up signal.The gate terminal of whole pull-down transistor 308a-d can be coupled on drop-down contact 328, to receive pulldown signal.Output contact 332 can be coupling on the node 336a-d between each the first resistor 312a-d and the second resistor 316a-d, the output signal of PID circuit 300 to be sent on output contact 332.
In various embodiments, the gate terminal of switching transistor 340a-d can be coupled on each control contact 352a-d, to receive each control signal.Therefore, switching transistor 340a-d can control separately, with the overall impedance regulating PID circuit 300 to present on output contact 332.
In various embodiments, first resistor 312a and the second resistor 316a of control unit 302a can have the first resistance value R1, first resistor 312b and the second resistor 316b of control unit 302b can have the second resistance value R2, first resistor 312c and the second resistor 316c of control unit 302c can have the 3rd resistance value R3, and the first resistor 312d and the second resistor 316d of control unit 302d can have the 4th resistance value R4.Following discussion further, resistance value R1-R4 may be the same or different.
Impedance control unit 302a-d can be connected in parallel to each other coupling.Therefore, for the PID circuit 300 with four control unit 302a-d, PID circuit 300 is programmed for one in 16 different resistance values, the minimum impedance value of PID circuit 300 equals (R1//R2//R3//R4)/2, the maximum impedance value of PID circuit 300 equals R1//R2//R3//R4, and wherein symbol R1//R2 represents the resistance value of R1 and R2 parallel connection.
PID circuit 300 can comprise R1, any desired value of R2, R3, R4.Such as, in certain embodiments, these values can in accordance with lower relation of plane: R1 >=R2 >=R3 >=R4.In certain embodiments, resistance value R1, R2, R3 and R4 can have binary relationship, and the resistance value of R2 equals R1//R1, and the resistance value of R3 equals R1//R1//R1//R1, and the resistance value of R4 equals R1//R1//R1//R1//R1//R1//R1//R1.In other embodiments, first resistor of at least one control unit 302a-d and the resistance value of the second resistor can be identical with the resistance value of the second resistor with first resistor of at least another control unit 302a-d, different with the resistance value of the second resistor from the first resistor of at least one other control unit.Such as, in one embodiment, R2 can equal R1, and R3 can equal R1//R1, and R4 can equal R1//R1//R1.
In certain embodiments, each resistor 312a-d and 316a-d can be formed by one or more resistance elements of the coupling that is connected in parallel to each other, and wherein whole resistance elements has identical resistance value.Therefore, as compared to for forming binary relationship between R1, R2, R3 and R4, above-mentioned R1, the resistance element that the nonbinary configuration of R2, R3 and R4 can make formation resistor 312a-d and 316a-d used is less.In other embodiments, resistance value R1, R2, R3 and R4 are equal to each other.
In various embodiments, compared with the drive circuit of existing voltage mode, PID circuit 200 and 300 can comprise less resistor, and/or provides less pad electric capacity.In addition, impedance-compensated process and process of postemphasising can be separated by PID circuit 200 and 300, and these processes can perform separately like this, and a process can not affect another process significantly.
As mentioned above, multiple PID circuit 300 can be included in transmitter circuit (such as, transmitter circuit 100).In certain embodiments, the control unit 302a-d of multiple PID circuit 300 can organize into groups in groups, in order to receive identical control signal.Such as, the control contact 352a-d of given group can be coupled on common control line together, to receive identical control signal.In certain embodiments, single group can comprise the control unit 302a-d of different PID circuit 300.
Fig. 4 shows the example of the impedance-compensated table 400 for transmitter circuit (such as transmitter circuit 100), and wherein this transmitter circuit comprises 12 PID circuit 300, and each PID circuit 300 comprises 4 control unit 302a-d.Table 400 represents that the control unit 302a-d of each PID circuit 300 is the R1-R4 arranging arrangement respectively.Table 400 shows 16 groups of control units, and often group comprises 3 the control unit 302a-d with same impedance value (such as, R1, R2, R3 or R4) from different PID circuit 300.The group of control unit can control by respective control signal C1-C16.The switching transistor 304a-d of corresponding control unit 302a-d can be carried out conducting or shutoff by control signal C1-C16, is switched by control unit 302a-d thus between high impedance value and low impedance value.Control signal C1-C16 can have first logical value (such as, logical zero) of shutoff related switch transistor 304a-d or second logical value (such as, logical one) of conducting related switch transistor 304a-d.
In certain embodiments, control signal can produce from the R-comp code with multiple, and the quantity of the plurality of position is less than the quantity of control unit group.Such as, 16 control signals can produce from 4 R-comp control routines.Refer again to Fig. 1, R-comp logical one 20 can produce this 4 R-comp control routines, and R-comp decoder 124 can produce R-comp control signal from this R-comp code.
In certain embodiments, R-comp logical one 20 and R-comp decoder 124 can serviceability temperature meter encoding schemes (thermometer coding scheme).Such as, these 4 R-comp codes may correspond in 16 different R-comp set points (such as, 1 to 16).For the R-comp settings of Integer n, R-comp decoder 124 can setup control signal C1-Cn, with their relevant switching transistors of conducting, and sets Cn+1-C16 to turn off their relevant switching transistors.Such as, be that 7, C1-C7 can be set to their relevant switching transistors of conducting for R-comp set point, C8-C16 can be set to turn off their relevant switching transistors.
Adopting this thermometer coding scheme, there are 17 possible set points (such as, whole logical zero, or control signal 1 to 16 has logical one) in control signal C1-C16.Therefore, in certain embodiments, a control signal C1-C16 (such as C1 or C16) forever can be set to the first or second logical value.It is evident that, other control programs of control unit 302a-d can use in the embodiments described herein.
Fig. 5 schematically shows the deaccentuator 500 according to each embodiment, and this deaccentuator 500 can be implemented by transmitter circuit 100.Such as, deaccentuator 500 can be implemented by the deaccentuator 118 of transmitter circuit 100.
In various embodiments, deaccentuator 500 can receive input data signal, and transmits this input data signal to multiple drive circuit 504.This single drive circuit 504 can comprise driver logic unit (such as, driver logic unit 116a-c) and bit slice drive circuit (such as bit slice drive circuit 108a-c), this bit slice drive circuit has one or more PID circuit (such as, PID circuit 112a-f).The drive circuit 504 of any suitable quantity can be coupled on deaccentuator 500.Such as, the deaccentuator 500 shown in Fig. 5 can be coupled to 12 drive circuits 504.
In various embodiments, deaccentuator 500 can comprise delayed-trigger 508, inverter 512, and multiplexer 516.Delayed-trigger 508 can receive input data signal and relevant clock signal clk, and the delayed deformation of exportable input data signal.Such as, delayed-trigger 508 can by a clock cycle of input data signal delay clock signals CLK.
Inverter 512 can receive the input data signal of this delay and can be undertaken anti-phase by the input data signal of this delay.Multiplexer 516 can be coupled on inverter 512, to receive this delay and anti-phase input data signal.Multiplexer 516 also can receive untreated input data signal (such as, not being delayed by and anti-phase input data signal).Multiplexer 516 can be coupled on multiple drive circuit 504.Multiplexer 516 can receive control signal of postemphasising, and is will to postpone and anti-phase input data signal or untreated input data signal are sent on each drive circuit 504 of multiple drive circuits 504 that this multiplexer 516 is coupled to control multiplexer 516.
In certain embodiments, untreated input data signal can be sent on one or more drive circuit 504 by deaccentuator 500, and does not transmit this input data signal by this multiplexer 516.Such as, in the embodiment shown in fig. 5,8 in 12 drive circuits 504 can receive untreated input data signal, and this input data signal is not transported through in this multiplexer 516,12 drive circuits 504 4 and can receive this untreated input data signal or this delay and anti-phase input data signal from this multiplexer 516.
In various embodiments, can select to receive this delay and the quantity of the drive circuit 504 of anti-phase input data signal, postemphasis level with the expectation of the outputting data signals realizing drive circuit 504.Such as, arrange 0,1,2,3, or 4 drive circuits 504 receive this delay and anti-phase input data signal can realize 0 decibel (dB) respectively, 1.5dB, 3.5dB, 6dB or 9.5dB.This level that postemphasises may correspond to usually in the high-pass filtering level performed on input data signal (such as, in order to the low frequency component of the high fdrequency component or the input data signal that postemphasises that increase the weight of input data signal).This level that postemphasises may be selected to the bandwidth of the communication port improved on transmission line (such as, transmission line 104a-b).
As mentioned above, drive circuit 504 can receive one or more R-comp control signal, to control the impedance that single drive circuit 504 presents.In various embodiments, this postemphasises and impedance-compensatedly can to perform separately, with postemphasis level and the output impedance of controlled transmitter circuit (such as transmitter circuit 100) respectively.
Fig. 6 shows the example of the computing equipment 600 according to each embodiment, and it can adopt device as herein described or method (such as, transmitter circuit 100, PID200, PID300, impedance-compensated table 400, deaccentuator 500).As shown in the figure, computing equipment 600 can comprise multiple parts, such as one or more processor 604 (only illustrating) and at least one communication chip 606.In various embodiments, each processor of this one or more processor 604 can comprise one or more processor cores.In various embodiments, this at least one communication chip 606 can physics or be electrically coupled on this one or more processor 604.In further execution mode, communication chip 606 can become a part for this one or more processor 604.In various embodiments, computing equipment 600 can comprise printed circuit board (PCB) (PCB) 602.For these embodiments, this one or more processor 604 and communication chip 606 can be arranged on it.In alternative embodiments, this all parts can not adopt PCB602 to be coupled.
According to its application, computing equipment 600 can comprise can or can not physics or the miscellaneous part that is electrically coupled on PCB602.These miscellaneous parts comprise, but be not limited to, storage control 605, volatile memory (such as, DRAM 608), such as read-only memory 610 (ROM), flash memory 612, and memory device 611 (such as, and so on HDD) nonvolatile memory, I/O controller 614, digital signal processor (not shown), cipher processor (not shown), graphic process unit 616, one or more antenna 618, display (not shown), touch screen displays 620, touch screen controller 622, battery 624, audio coder (not shown), video encoder (not shown), global positioning system (GPS) equipment 628, compass 630, accelerometer (not shown), free gyroscope (not shown), loud speaker 632, camera 634, and Large Copacity storage facilities (such as hard disk drive, solid-state drive, CD (CD), Digital video disc (DVD)) (not shown), etc..In various embodiments, processor 604 can be on the same wafer integrated with miscellaneous part, forms systems-on-a-chip (SoC).
In certain embodiments, this one or more processor, flash memory 612 and/or memory device 611 can comprise the associated firmware (not shown) storing programming instruction, described programming instruction is configured such that computing equipment 600 can in response to the execution of these one or more processors 604 pairs of programming instructions, thus put into practice the whole of methods described herein or selected aspect (process of such as, postemphasising and/or impedance-compensated process).In various embodiments, these aspects can adopt in addition or alternatively with this one or more processor 604, and flash memory 612, the hardware that memory device 611 separates is implemented.
In various embodiments, one or more parts of this computing equipment 600 can comprise the transmitter circuit 100 for transmitting data described herein.Such as, this transmitter circuit 100 can be included in I/O controller 614, processor 604, Memory Controller 605, and/or in another parts of computing equipment 600.In certain embodiments, I/O controller 614 can be connected with one or more external equipment, carrys out transmission of data signals to adopt this transmitter circuit 100.In other embodiments, this transmitter circuit 100 be used in computing equipment 600 two parts between transmission of data signals.
Communication chip 606 can enable wired and/or wireless telecommunications, for transmitting data from computing equipment 600 or sending data to computing equipment 600.Term " wireless " and derivative thereof can be used for describing the circuit by using modulated electromagnetic radiation to carry out data communication, and equipment, system, method, technology, communication channel etc., wherein this modulated electromagnetic radiation is undertaken by non-solid medium.This term not hint relevant device does not comprise any circuit, although they can not comprise in certain embodiments.Communication chip 606 can realize any one in multiple wireless standard or agreement, including, but not limited to IEEE702.20, GPRS (GPRS), evolution data optimization (Ev-DO), evolution high-speed packet access (HSPA+), evolution high-speed slender body theory (HSDPA+), evolution high speed uplink packet access (HSUPA+), global system for mobile communications (GSM), the enhanced data rates (EDGE) of GSM evolution, code division multiple access (CDMA), time division multiple access (TDMA), digitlization enhanced wireless telecommunications (DECT), bluetooth, and derivative, be labeled as 3G, 4G, 5G and other wireless protocols afterwards.Computing equipment 600 can comprise multiple communication chip 606.Such as, the first communication chip 606 can be exclusively used in short-distance wireless communication, such as Wi-Fi and bluetooth and so on, and the second communication chip 606 is exclusively used in the wireless telecommunications of long distance, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and other.
In each execution mode, computing equipment 600 can be kneetop computer, net book, notebook computer, super notebook, smart phone, panel computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, Set Top Box, amusement control unit (such as, game machine or automatically amusement unit), digital camera, utensil, portable music player, or digital video recorder.In further execution mode, computing equipment 600 can be any other electronic equipment of deal with data.
Some nonrestrictive example is provided below.
Example 1 is a kind of circuit for transmission of data signals, and this circuit comprises: pull up transistor, and receives pull-up signal at this gate terminal pulled up transistor; Pull-down transistor, receives pulldown signal at the gate terminal of this pull-down transistor; Pull up transistor and the first resistor coupled in series with one another and the second resistor between pull-down transistor at this; Be coupled to the output contact on the node between the first resistor and the second resistor, in order to transmit the output signal of this pull-up signal of response and pulldown signal; The switching transistor be coupled with this first resistor and the second capacitor in parallel; And control contact, this control coupling contact points, on switching transistor, carrys out conducting in order to reception control signal or turns off this switching transistor, to control the impedance at output contact place.
Example 2 is circuit of example 1, and wherein, the first resistor is coupled to the drain terminal pulled up transistor, and the second resistor is coupled to the source terminal of pull-down transistor.
Example 3 is circuit of example 2, and the source terminal wherein pulled up transistor is coupled to power contact to receive supply voltage, and wherein the drain terminal of pull-down transistor is coupling to ground current potential.
Example 4 is circuit of example 1, wherein this pull up transistor, pull-down transistor, switching transistor, the first resistor and the second resistor and control contact and be included in the first control unit, and this circuit comprises programmable resistance drive circuit (PID), this programmable resistance drive circuit has the multiple control units comprising this first control unit; Each control unit wherein said receives independent control signal to control the output impedance at output contact place.
Example 5 is circuit of example 4, and wherein this PID circuit comprises four control units.
Example 6 is circuit of example 4, and wherein the resistance value of the first resistor of the first control unit is different from the resistance value of the first resistor of the second control unit in the plurality of control unit.
Example 7 is circuit of example 6, and wherein the resistance value of the first resistor of this first control unit is also identical with the resistance value of the first resistor of the 3rd control unit of the plurality of control unit.
Example 8 is circuit of any one example of example 4 to 7, and wherein this circuit comprises multiple PID circuit, and the output contact of the plurality of PID circuit is connected in parallel to each other coupling.
Example 9 is PID circuit of example 8, and multiple control coupling contact points of being wherein correlated with from different PID circuit are to receiving identical control signal together.
Example 10 is PID circuit of example 8, also comprises: be coupled to the driver logic unit on each PID circuit, and this driver logic unit receives input data signal, produces the respective pull-up signal and pulldown signal that are used for PID circuit; And deaccentuator, in order to transmit the delay of this input data signal and anti-phase distortion to multiple driver logic unit, wherein the quantity of this driver logic unit is programmable.
Example 11 is a kind of circuit for transmission of data signals, and this circuit comprises: impedance compensation circuit, in order to produce multiple control signal, with the impedance on controls transfer line; And multiple programmable resistance driver (PID) circuit be coupled on this impedance compensation circuit, PID circuit is connected in parallel to each other coupling to drive the output signal on transmission line, wherein each PID circuit comprises multiple control unit, wherein the impedance of each control unit can switch between high impedance and Low ESR in response in the plurality of control signal, and wherein the marshalling of this control unit in groups, for receiving identical control signal, at least one group comprises the control unit from different PID circuit.
Example 12 is circuit of example 11, wherein this at least one PID circuit comprises the first control unit, second control unit and the 3rd control unit, and wherein the high impedance of the first control unit equals the high impedance of the second control unit, and be different from the high impedance of the 3rd control unit.
Example 13 is circuit of example 12, and wherein this at least one PID circuit also comprises the 4th control unit, and its high impedance is different from the high impedance of first, second, and third control unit.
Example 14 is circuit of example 11, and wherein this impedance compensation circuit comprises the R-comp logic producing R-comp code, and produce the R-comp decoder of control signal based on this R-comp code, wherein the figure place of R-comp code is less than the quantity of the group of control unit.
Example 15 is circuit of example 11, has identical high impedance comprising the control unit in each group.
Example 16 is circuit of arbitrary example in example 11 to 15, and wherein this each control unit comprises: pull up transistor, and receives pull-up signal at this gate terminal pulled up transistor; Pull-down transistor, receives pulldown signal at the gate terminal of this pull-down transistor; Pull up transistor and the first resistor coupled in series with one another and the second resistor between pull-down transistor at this, wherein output contact is coupled on the node between the first resistor of all control circuits of each PID circuit and the second resistor; The switching transistor be coupled with this first resistor and the second capacitor in parallel, this switching transistor in order to receive each control signal at third transistor gate terminal place, in order to conducting or turn off this switching transistor, to switch between high impedance and Low ESR.
Example 17 is the systems for transmission of data signals, and this system comprises: processor; And transmitter circuit, this transmitter circuit is coupled on this processor, in order to transmit data by transmission line data-signal to processor or from processor, this transmitter circuit comprises multiple coupling that is connected in parallel to each other, to drive programmable resistance driver (PID) circuit of the data-signal on transmission line.This each PID circuit comprises: first input end receiving pull-up signal; Receive the second input terminal of pulldown signal; Transmit the first output contact outputing signal to transmission line; And one or more control unit.This control unit comprises: pull up transistor, and receives this pull-up signal at this gate terminal pulled up transistor; Pull-down transistor, receives this pulldown signal at the gate terminal of this pull-down transistor; Pull up transistor and the first resistor coupled in series with one another and the second resistor between pull-down transistor at this, wherein this output contact is coupled on the node between the first resistor and the second resistor; And the switching transistor to be coupled with this first resistor and the second capacitor in parallel, this switching transistor, in order to be received in the control signal of the gate terminal of third transistor, with conducting or turn off this switching transistor, thus controls the output impedance at output contact place.
Example 18 is systems of example 17, and wherein this transmitter circuit also comprises driver logic unit, the input data signal that its reception will be transmitted, and produces pull-up signal and pulldown signal based on this input data signal.
Example 19 is systems of example 17, wherein this transmitter circuit also comprises deaccentuator, for receive input data signal and transmit the delay of this input data signal and anti-phase distortion to multiple driver logic unit, wherein the quantity of this driver logic unit is programmable.
Example 20 is systems of example 17, wherein this data-signal is positive data signal, this transmission line is positive transmission line, and the plurality of PID circuit is positive PID circuit, and wherein this transmitter circuit also comprises multiple negative PID circuit, to drive negative data signal on negative transmission line, thus form differential data signals with positive data signal.
Example 21 is systems of example 17, wherein a PID circuit of the plurality of PID circuit comprises multiple control unit, the plurality of control unit comprises first, second, and third control unit, and wherein the resistance value of the first resistor of the first control unit is identical with the resistance value of the first resistor of the second control unit, different from the resistance value of the first resistor of the 3rd control unit.
Example 22 is systems of arbitrary example in example 17 to 21, and the plurality of control unit of wherein different PID circuit receives identical control signal.
Example 23 is systems of arbitrary example in example 17 to 21, also comprises impedance compensation circuit, in order to the impedance on transmission line to be compared control the switching transistor of control unit according to this compared with reference impedance.
Example 24 is a kind of methods for transmission of data signals, and the method comprises: produce the impedance that multiple control signal is come on controls transfer line; And send each control signal to often group programmable resistance driver (PID) circuit, this PID circuit is connected in parallel to each other coupling to drive the output signal on transmission line, wherein this each PID circuit comprises multiple control unit, the wherein impedance response of each control unit in multiple control signal and switching between high impedance and Low ESR, and wherein the group of this control unit is in order to receive identical control signal, at least one group of control unit comprised from different PID circuit.
Example 25 is methods of claim 24, at least one wherein in PID circuit comprises the first control unit, the second control unit and the 3rd control unit, and wherein the high impedance of this first control unit is identical with the high impedance of the second control unit, different from the high impedance of the 3rd control unit.
Example 26 is methods of claim 25, and wherein this at least one PID circuit also comprises the 4th control unit, and the high impedance of the 4th control unit is different from the high impedance of first, second, and third control unit.
Example 27 is methods of claim 24, and wherein the multiple control signal of this generation comprises: produce the R-comp code with multiple; And producing control signal according to this R-comp code, the figure place of this R-comp code is less than the quantity of the group of control unit.
Example 28 is methods of claim 24, has identical high impedance value comprising the control unit in each group.
Example 29 is methods of claim 24, and wherein this each control unit comprises: pull up transistor, and receives pull-up signal at this gate terminal pulled up transistor; Pull-down transistor, receives drop-down data-signal at the gate terminal of this pull-down transistor; Pulling up transistor and the first resistor coupled in series with one another and the second resistor between pull-down transistor, wherein output contact is coupled on the node between the first resistor of all control circuits of each PID circuit and the second resistor; And the switching transistor to be coupled with this first resistor and the second capacitor in parallel, this switching transistor is in order to receive each control signal at the gate terminal place of third transistor, with this switching transistor of turn-on and turn-off, thus switch between high impedance and Low ESR.
Although in order to the object described illustrate and describes specific embodiment in this article, the application is intended to cover change or the change of described embodiment herein.Therefore, it is obviously intended to embodiment as herein described and is only limited by claim.
When present disclosure refer to " one " or " first " element or its equivalent, thisly openly comprise one or more this element, neither also must not get rid of two or more this element.In addition, the order indicant (such as, first of the element determined, second or the 3rd) for distinguishing between elements, do not represent or imply the required or limited quantity of these elements, they do not indicate the specific position of these elements or order yet, except non-expert describes.
Claims (23)
1., for a circuit for transmission of data signals, comprising:
Pull up transistor, receive pull-up signal at the described gate terminal place pulled up transistor;
Pull-down transistor, receives pulldown signal at the gate terminal place of described pull-down transistor;
Pull up transistor and the first resistor coupled in series with one another between described pull-down transistor and the second resistor described;
Output contact, described output contact is coupled to the node between described first resistor and described second resistor, to transmit the output signal in response to described pull-up signal and described pulldown signal;
The switching transistor be coupled with described first resistor and described second capacitor in parallel; And
Control contact, described control coupling contact points, to the gate terminal of described switching transistor, carrys out conducting with reception control signal or turns off described switching transistor, thus controls the impedance at described output contact place.
2. circuit according to claim 1, wherein, the drain terminal pulled up transistor described in described first resistor is coupled to, and described second resistor is coupled to the source terminal of described pull-down transistor.
3. circuit according to claim 2, wherein, described in the source terminal that pulls up transistor be coupled to power contact to receive supply voltage, and wherein, the drain terminal of described pull-down transistor is coupling to ground current potential.
4. circuit according to claim 1, wherein, describedly to pull up transistor, described pull-down transistor, described switching transistor, described first resistor and described second resistor and described control contact be included in the first control unit, and wherein, described circuit comprises programmable resistance drive circuit (PID), described programmable resistance drive circuit has the multiple control units comprising described first control unit, wherein, each control unit receives independent control signal to control the output impedance at described output contact place.
5. circuit according to claim 4, wherein, described PID circuit comprises four control units.
6. circuit according to claim 4, wherein, the resistance value of described first resistor of described first control unit is different from the resistance value of described first resistor of the second control unit of described multiple control unit.
7. circuit according to claim 6, wherein, the described resistance value of described first resistor of described first control unit is identical with the resistance value of described first resistor of the 3rd control unit of described multiple control unit.
8. the circuit according to any one of claim 4-7, wherein, described circuit comprises multiple PID circuit, and the described output contact of described multiple PID circuit is connected in parallel to each other coupling.
9. circuit according to claim 8, wherein, is coupled together to receive identical control signal from multiple control contacts that different PID circuit is associated.
10. circuit according to claim 8, also comprises:
Be coupled to the driver logic unit of each PID circuit, described driver logic unit receives input data signal and produces each pull-up signal and pulldown signal of being used for described PID circuit; And
Deaccentuator, described deaccentuator is by the delay of described input data signal and anti-phase distortion sends multiple driver logic unit to, and wherein, the quantity of described multiple driver logic unit is programmable.
11. 1 kinds, for the circuit of transmission of data signals, comprising:
Impedance compensation circuit, described impedance compensation circuit produces multiple control signal with the impedance on controls transfer line; And
Be coupled to multiple programmable resistance driver (PID) circuit of described impedance compensation circuit, described PID circuit is connected in parallel to each other coupling to drive the output signal on described transmission line, wherein, each PID circuit comprises multiple control unit, wherein, the impedance of each control unit can switch between high impedance and Low ESR in response to a control signal in described multiple control signal, and wherein, described control unit is organized as the group receiving identical control signal, and at least one group in described group comprises the control unit from different PID circuit.
12. circuit according to claim 11, wherein, at least one PID circuit in described PID circuit comprises the first control unit, the second control unit and the 3rd control unit, and wherein, the described high impedance of described first control unit is identical from the described high impedance of described second control unit and different with the described high impedance of described 3rd control unit.
13. circuit according to claim 12, wherein, at least one PID circuit described also comprises the 4th control unit, and the high impedance of described 4th control unit is different from the described high impedance of the described high impedance of described first control unit, described second control unit and the described high impedance of described 3rd control unit.
14. circuit according to claim 11, wherein, described impedance compensation circuit comprises the R-comp logical block producing R-comp code and the R-comp decoder producing described control signal based on described R-comp code, wherein, the figure place of described R-comp code is less than the quantity of described group of control unit.
15. circuit according to claim 11, wherein, the described control unit be included in each group has identical high impedance value.
16. circuit according to any one of claim 11-15, wherein, each control unit described comprises:
Pull up transistor, receive pull-up signal at the described gate terminal place pulled up transistor;
Pull-down transistor, receives drop-down data-signal at the gate terminal place of described pull-down transistor;
Pull up transistor and the first resistor coupled in series with one another between described pull-down transistor and the second resistor described, wherein, output contact is coupled to the node between described first resistor of all control units of each PID circuit and described second resistor; And
The switching transistor be coupled with described first resistor and described second capacitor in parallel, the corresponding control signal that described switching transistor receives the gate terminal place of described third transistor is with conducting or turn off described switching transistor, thus switches between described high impedance and described Low ESR.
17. 1 kinds, for the system of transmission of data signals, comprising:
Processor;
Be coupled to the transmitter circuit of described processor, described transmitter circuit via transmission line data-signal to described processor or from described processor transmission of data signals, described transmitter circuit comprises multiple programmable resistance driver (PID) circuit of the coupling that is connected in parallel to each other to drive the described data-signal on described transmission line, wherein, each PID circuit comprises:
Receive first input end of pull-up signal;
Receive the second input terminal of pulldown signal;
First output contact, described first output contact sends output signal to described transmission line; And
One or more control unit, described one or more control unit comprises:
Pull up transistor, described in pull up transistor and receive described pull-up signal at the described gate terminal place pulled up transistor;
Pull-down transistor, described pull-down transistor receives described pulldown signal at the gate terminal place of described pull-down transistor;
Pull up transistor and the first resistor coupled in series with one another between described pull-down transistor and the second resistor described, wherein, described output contact is coupled to the node between described first resistor and described second resistor; And
The switching transistor be coupled with described first resistor and described second capacitor in parallel, the control signal that described switching transistor receives the gate terminal place of described third transistor is with conducting or turn off described switching transistor, thus controls the output impedance at described output contact place.
18. systems according to claim 17, wherein, described transmitter circuit also comprises driver logic unit to receive the input data signal that will be transmitted, and produces described pull-up signal and described pulldown signal based on described input data signal.
19. systems according to claim 17, wherein, described transmitter circuit also comprises deaccentuator to receive input data signal, and by the delay of described input data signal and anti-phase distortion sends multiple driver logic unit to, wherein, the quantity of described multiple driver logic unit is programmable.
20. systems according to claim 17, wherein, described data-signal is positive data signal, described transmission line is positive transmission line, and described multiple PID circuit is positive PID circuit, and wherein, described transmitter circuit also comprises multiple negative PID circuit to drive the negative data signal on negative transmission line, thus forms differential data signals with described positive data signal.
21. systems according to claim 17, wherein, one PID circuit of described multiple PID circuit comprises multiple control unit, described multiple control unit comprises the first control unit, the second control unit and the 3rd control unit, and wherein, the resistance value of described first resistor of described first control unit is identical from the resistance value of described first resistor of described second control unit and different with the resistance value of described first resistor of described 3rd control unit.
22. according to claim 17 to the system according to any one of 21, and wherein, the multiple control units from different PID circuit receive identical control signal.
23., according to claim 17 to the system according to any one of 21, also comprise impedance compensation circuit, in order to the impedance on described transmission line and reference impedance to be compared, and based on the described described switching transistor relatively controlling described control unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| US14/107,993 US9537479B2 (en) | 2013-12-16 | 2013-12-16 | Programmable impedance transmitter for serial communication |
| US14/107,993 | 2013-12-16 |
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| CN104734688A true CN104734688A (en) | 2015-06-24 |
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| US20150171829A1 (en) | 2015-06-18 |
| US9537479B2 (en) | 2017-01-03 |
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