CN109412558B - Transmitting circuit for eliminating random code dithering noise in mipi - Google Patents
Transmitting circuit for eliminating random code dithering noise in mipi Download PDFInfo
- Publication number
- CN109412558B CN109412558B CN201811646219.3A CN201811646219A CN109412558B CN 109412558 B CN109412558 B CN 109412558B CN 201811646219 A CN201811646219 A CN 201811646219A CN 109412558 B CN109412558 B CN 109412558B
- Authority
- CN
- China
- Prior art keywords
- signal
- register
- din
- random code
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
Abstract
The invention discloses a transmitting circuit for eliminating random code dithering noise in a mipi, which comprises a first register, an exclusive-OR gate, an inverter, a transmission gate, a second register and a third register, wherein a data signal DIN_pre and a first clock signal CLK generate a delay signal DIN_DL through the first register; the delay signal DIN_DL and the data signal DIN_pre are exclusive-OR-ed to generate an exclusive-OR signal DXOR; when the data signal DIN_pre has continuous 0 or 1, the exclusive OR signal DXOR is 0, the transmission gate is opened, the second clock signal CLK2 generates the transition signal DINC through the second register and the inverted signal DIND of the transition signal DINC; the data signal din_pre and the second clock signal CLK2 pass through the third register to generate the random code signal DIN and the inverted signal DINB of the random code signal DIN. The invention fundamentally eliminates the dithering noise caused by the random code.
Description
Technical Field
The invention relates to the technical field of a mipi (mobile industry processor interface) high-speed signal transmission circuit, in particular to a transmission circuit for eliminating random code jitter noise in mipi.
Background
In a high-speed signal transmission circuit such as a mipi circuit, power supplies of a driving circuit and a front-stage driving circuit are usually supplied by a low drop out (low dropout) voltage regulator (LDO), as shown in fig. 2, when a high-speed random code signal DIN is transmitted, current loads of the LDO are also randomly switched at high speed, the non-capacitive LDO responds to the high-frequency current loads to be limited, random ripples which cannot be eliminated are formed, and when ripples with random magnitudes act on signal edges of the driving circuit and the front-stage driving circuit, the signals generate jitters A1, A2 and A3, the sizes of the jitters are different, so that rising edge speeds of the signals are different, and eye pattern quality is affected. In fig. 2, VLDO represents voltage. The traditional method is to improve the transient response speed of the capacitor-free LDO, but the on-chip capacitor area is large and the effect is limited.
Disclosure of Invention
The invention aims to provide a transmitting circuit for eliminating random code dithering noise in mipi, which eliminates dithering noise caused by random codes.
The technical scheme for achieving the purpose is as follows:
a transmitting circuit for eliminating random code dithering noise in mipi comprises a first register, an exclusive-OR gate, an inverter, a transmission gate, a second register and a third register,
the data signal DIN_pre and the first clock signal CLK passing through the first register to generate a slow one bit delay signal DIN_DL;
the delay signal DIN_DL and the data signal DIN_pre are exclusive-OR-gate, generating an exclusive-OR signal DXOR;
the exclusive-or signal DXOR is connected with two control ends of the transmission gate through an inverted signal generated by the inverter, and the second clock signal CLK2 is connected with the input end of the transmission gate; the output end of the transmission gate is connected with the second register;
when the data signal DIN_pre has a continuous 0 or 1, the exclusive OR signal DXOR is 0, the transmission gate is turned on, the second clock signal CLK2 generates the transition signal DINC and the inverted signal DIND of the transition signal DINC through the second register;
the data signal din_pre and the second clock signal CLK2 pass through the third register to generate the random code signal DIN and the inverted signal DINB of the random code signal DIN.
The beneficial effects of the invention are as follows: the invention adopts an effective structural design, solves the problem of random ripple of random code signals in the drive circuit to the LDO output power supply, and further fundamentally eliminates jitter noise caused by random codes.
Drawings
Fig. 1 is a circuit diagram of a transmitting circuit of the present invention;
FIG. 2 is a schematic diagram of a prior art random code signal and output voltage;
FIG. 3 is a schematic diagram of signals in a transmit circuit of the present invention;
FIG. 4 is a schematic diagram of the random code signal and the output voltage according to the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1 and 3, the transmission circuit for eliminating random code dithering noise in the mipi of the present invention includes a first register 1, an exclusive or gate 2, an inverter 3, a transmission gate 4, a second register 5, and a third register 6.
The data signal din_pre and the first clock signal CLK pass through the first register 1 to generate a delayed signal din_dl that is one bit slower. The delay signal DIN_DL and the data signal DIN_pre pass through the exclusive OR gate 2 to generate the exclusive OR signal DXOR. The exclusive-or signal DXOR is connected to two control ends of the transmission gate 4 via an inverted signal generated by the inverter 3, and the second clock signal CLK2 is connected to an input end of the transmission gate 4; the output of the transmission gate 4 is connected to a second register 5.
When the data signal din_pre has consecutive 0 s or 1 s, the exclusive or signal DXOR is 0, the transmission gate 4 is turned on, the second clock signal CLK2 generates the transition signal DINC through the second register 5, and the inverted signal DIND of the transition signal DINC.
The data signal din_pre and the second clock signal CLK2 pass through the third register 6 to generate the random code signal DIN and the inverted signal DINB of the random code signal DIN.
Referring to fig. 4, four signals are generated: the random code signal DIN, the inverted signal DINB of the random code signal DIN, the jump signal DINC and the inverted signal DIND of the jump signal DINC each pass through four identical signal paths, and then at the edge of any two data of the random code signal DIN, the four signal paths all comprise a rising edge, a falling edge, a high level and a low level, so that the LDO load is changed from random to regular, the output voltage VLDO can have ripples with the same magnitude, such as jitter B1, B2 and B3, which are the same, and thus the rising edge speeds of the signals are the same, and jitter noise caused by random codes is eliminated.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (1)
1. A transmitting circuit for eliminating random code dithering noise in mipi is characterized by comprising a first register, an exclusive-OR gate, an inverter, a transmission gate, a second register and a third register,
the data signal DIN_pre and the first clock signal CLK passing through the first register to generate a slow one bit delay signal DIN_DL;
the delay signal DIN_DL and the data signal DIN_pre are exclusive-OR-gate, generating an exclusive-OR signal DXOR;
the exclusive-or signal DXOR is connected with two control ends of the transmission gate through an inverted signal generated by the inverter, and the second clock signal CLK2 is connected with the input end of the transmission gate; the output end of the transmission gate is connected with the second register;
when the data signal DIN_pre has a continuous 0 or 1, the exclusive OR signal DXOR is 0, the transmission gate is turned on, the second clock signal CLK2 generates the transition signal DINC and the inverted signal DIND of the transition signal DINC through the second register;
the data signal din_pre and the second clock signal CLK2 pass through the third register to generate the random code signal DIN and the inverted signal DINB of the random code signal DIN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811646219.3A CN109412558B (en) | 2018-12-29 | 2018-12-29 | Transmitting circuit for eliminating random code dithering noise in mipi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811646219.3A CN109412558B (en) | 2018-12-29 | 2018-12-29 | Transmitting circuit for eliminating random code dithering noise in mipi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109412558A CN109412558A (en) | 2019-03-01 |
| CN109412558B true CN109412558B (en) | 2023-09-05 |
Family
ID=65461816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811646219.3A Active CN109412558B (en) | 2018-12-29 | 2018-12-29 | Transmitting circuit for eliminating random code dithering noise in mipi |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109412558B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151612A (en) * | 1989-06-22 | 1992-09-29 | Nissan Motor Co., Ltd. | Circuit for eliminating digital noise or short pulses utilizing set/reset shift register |
| CN103389892A (en) * | 2013-06-25 | 2013-11-13 | 浙江大学 | Self-refreshing triple-modular redundancy counter |
| CN106385251A (en) * | 2016-09-14 | 2017-02-08 | 豪威科技(上海)有限公司 | Clock data recovery circuit |
| CN207321227U (en) * | 2017-10-18 | 2018-05-04 | 南京邮电大学南通研究院有限公司 | A kind of control circuit of transition detection device and clock frequency regulating system |
| CN209072443U (en) * | 2018-12-29 | 2019-07-05 | 灿芯半导体(上海)有限公司 | The transmitting line of random code jittering noise is eliminated in a kind of mipi |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8135768B2 (en) * | 2005-03-02 | 2012-03-13 | Mtekvision Co., Ltd. | Adder with reduced capacitance |
| US7880554B2 (en) * | 2009-02-03 | 2011-02-01 | Qualcomm Incorporated | Periodic timing jitter reduction in oscillatory systems |
-
2018
- 2018-12-29 CN CN201811646219.3A patent/CN109412558B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151612A (en) * | 1989-06-22 | 1992-09-29 | Nissan Motor Co., Ltd. | Circuit for eliminating digital noise or short pulses utilizing set/reset shift register |
| CN103389892A (en) * | 2013-06-25 | 2013-11-13 | 浙江大学 | Self-refreshing triple-modular redundancy counter |
| CN106385251A (en) * | 2016-09-14 | 2017-02-08 | 豪威科技(上海)有限公司 | Clock data recovery circuit |
| CN207321227U (en) * | 2017-10-18 | 2018-05-04 | 南京邮电大学南通研究院有限公司 | A kind of control circuit of transition detection device and clock frequency regulating system |
| CN209072443U (en) * | 2018-12-29 | 2019-07-05 | 灿芯半导体(上海)有限公司 | The transmitting line of random code jittering noise is eliminated in a kind of mipi |
Non-Patent Citations (1)
| Title |
|---|
| 戚忠雪.一种基于0.18μm工艺的LDO的设计.《中国优秀硕士学位论文全文数据库信息科技辑》.2013,I135-200. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109412558A (en) | 2019-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106294244B (en) | USB Type-C interface circuit | |
| JP2021500792A (en) | Orthogonal clock correction circuit for transmitter | |
| JP6866392B2 (en) | 3 Intelligent equalization of transmitter multi-phase system | |
| US20200409444A1 (en) | Power consumption management in protocol-based redrivers | |
| CN102739209B (en) | Clock pulse width modulation circuit and clock pulse width modulation method | |
| KR100499157B1 (en) | High speed serializer | |
| WO2016058495A1 (en) | Hardware apparatus and method for multiple processors dynamic asymmetric and symmetric mode switching | |
| EP3095218A1 (en) | Analog behavior modeling for 3-phase signaling | |
| KR100423898B1 (en) | Universal serial bus low speed transceiver with improved corssover performance | |
| CN110710109A (en) | Noise cancellation circuit and data transmission circuit | |
| CN108984446B (en) | PHY interface based on FPGA primitive and FPGA chip | |
| CN209072443U (en) | The transmitting line of random code jittering noise is eliminated in a kind of mipi | |
| KR20090013481A (en) | Source driver circuit and liquid crystal display device having the same | |
| JP5109717B2 (en) | Transmitter circuit | |
| CN109412558B (en) | Transmitting circuit for eliminating random code dithering noise in mipi | |
| JP2009118449A (en) | Circuit and method for clock data recovery for highly integrated system | |
| CN104901656A (en) | Method and device for digital filtering and de-jittering | |
| US7830166B2 (en) | Pulse shift modulation for reducing cross-talk of single ended I/O interconnects | |
| KR102583820B1 (en) | Data transmission circuit | |
| KR101405241B1 (en) | Transmitter for data communication | |
| TWI676888B (en) | Systems and methods providing a low-power mode for serial links | |
| CN103457447B (en) | Power supply chip modulation and switching width control device | |
| CN111682873A (en) | Low-power-consumption output buffer circuit | |
| KR102513739B1 (en) | Equalizing system of mipi d-phy high-speed transmitter | |
| EP4354731A1 (en) | Delay circuit, pulse generation circuit, chip and server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |