CN103389892A - Self-refreshing triple-modular redundancy counter - Google Patents
Self-refreshing triple-modular redundancy counter Download PDFInfo
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- CN103389892A CN103389892A CN2013102576232A CN201310257623A CN103389892A CN 103389892 A CN103389892 A CN 103389892A CN 2013102576232 A CN2013102576232 A CN 2013102576232A CN 201310257623 A CN201310257623 A CN 201310257623A CN 103389892 A CN103389892 A CN 103389892A
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Abstract
The invention discloses a self-refreshing triple-modular redundancy counter, which comprises three counters J1, J2 and J3 and three voters B1, B2 and B3, which are mutually connected. According to the triple-modular redundancy counter disclosed by the invention, by feeding back results of the voters to the counters, the counting results of the counters can be refreshed timely, and accordingly the error cumulative effect of the counters can be eliminated; as long as two of the three counters do not go wrong simultaneously, the whole triple-modular redundancy counter can continue to normally work.
Description
Technical field
The invention belongs to digital circuit counter technical field, be specifically related to a kind of triplication redundancy counter of self-refresh.
Background technology
Variational OR was just Probabilistic logics and synthesis of reliable organisms from unreliable components(in Automata Studies at title as far back as 1956, C.Shannon and J.McCarthy, Eds.Princeton University Press, 1956, pp.43 – 98.) propose in document to utilize redundancy and majority voting device to construct reliable system.From then on multi-mode redundant and triplication redundancy just are widely used in belief system as the most basic a kind of technology.Because triplication redundancy needs extra hardware spending less, and its reliability makes the triplication redundancy technology be widely used at industry, traffic control and aerospace field very near multi-mode redundant.
The triplication redundancy counter often is used to the state machine counter in hardened system, in case because mistake appears in the state machine counter, thereby can cause the state machine state misjudgment to cause the system misoperation.Tradition triplication redundancy counter structure as shown in Figure 1.Voting machine in Fig. 1 is to put to the vote according to the principle of " the minority is subordinate to the majority ", and namely the majority value in three inputs has determined the output of voting machine.The structure of its voting machine and truth table are as shown in Figure 2.With three input signals in twos one group carry out AND operation, then the result of AND operation is carried out after inclusive-OR operation voting result output as voting machine.
Clearly voting machine also may be made mistakes, and single voting machine may become the bottleneck that improves the triple-modular redundancy system reliability, therefore prior art has also been carried out the triplication redundancy reinforcing to voting machine, this improvement structure is called complete triplication redundancy structure, as shown in Figure 3.Fully the structure of triplication redundancy has good antijamming capability in the circuit structure that pure combinational circuit or combinational circuit are in the great majority, but for the more circuit of counter, the triplication redundancy structure can not solve the cumulative errors effect of counter fully.Suppose that soft error appears in the counter 3 in Fig. 3, the result that is counter 3 has become 4 by 3, as shown in Figure 4, when mistake appears in counter 3, this moment is because the count value of counter 1 sum counter 2 is the same, the voting result that obtains after three voting machines so or the same, namely this moment, whole complete triplication redundancy counter still worked, and not there will be mistake.But after a period of time, when mistake appears in counter 2 when counting down to 6, because the error count result of counter 3 is not corrected, this moment, three Counter Values were all different, cause voting machine to work, last three voting machines output is all 0, thereby makes whole complete triplication redundancy rolling counters forward mistake.
Summary of the invention
For the existing above-mentioned technological deficiency of prior art, the invention provides a kind of triplication redundancy counter of self-refresh, feed back to counter by the voting result with voting machine, with the count results of refresh counter, thereby eliminate the error accumulation effect of counter.
A kind of triplication redundancy counter of self-refresh, comprise three counter J1～J3 and three voting machine B1～B3; Wherein:
the clock end of three counter J1～J3 all receives given counting clock, the output terminal of counter J1 is connected with the first input end of three voting machine B1～B3, the output terminal of counter J2 is connected with the second input end of three voting machine B1～B3, the output terminal of counter J3 is connected with the 3rd input end of three voting machine B1～B3, the output terminal of voting machine B1 is connected and exports count results with the input end of counter J1, the output terminal of voting machine B2 is connected and exports count results with the input end of counter J2, the output terminal of voting machine B3 is connected and exports count results with the input end of counter J3.
Described counter is used the Output rusults of corresponding voting machine as self input signal, when counting clock is effective, input signal is added 1 rear as count value and output; If described count value reaches the counting maximal value of counter self, counter when counting clock is effective next time with described count value zero clearing.
Described voting machine is used the Output rusults of three counter J1～J3 as self input signal, if having at least two groups identical in three groups of input signals, voting machine is exported this identical input signal, otherwise is output as 0.
Described three counter J1～J3 all adopt three digit counters, and three voting machine B1～B3 all adopt three voting machines; Described three voting machines comprise three three input voting machine H1～H3, the output terminal of three three input voting machine H1～H3 forms three output terminals of three voting machines, three input ends of three input voting machine H1 receive respectively first Output rusults of three counter J1～J3, three input ends of three input voting machine H2 receive respectively the second Output rusults of three counter J1～J3, and three input ends of three input voting machine H3 receive respectively the 3rd Output rusults of three counter J1～J3.
described three digit counters comprise three d type flip flop D1～D3, two same or door TOR1～TOR2, a phase inverter and Sheffer stroke gates, wherein: the input end of phase inverter is connected with the first input end of Sheffer stroke gate and is first input end of three digit counters, the output terminal of phase inverter with or the door first input end of TOR1 and the D input end of d type flip flop D1 be connected, the Q output terminal of d type flip flop D1 is first output terminal of three digit counters, the second input end of Sheffer stroke gate is connected with the second input end same or door TOR1 and is the second input end of three digit counters, output terminal same or door TOR1 is connected with the D input end of d type flip flop D2, the Q output terminal of d type flip flop D2 is the second output terminal of three digit counters, the output terminal of Sheffer stroke gate is connected with first input end same or door TOR2, the second input end same or door TOR2 is the 3rd input end of three digit counters, output terminal same or door TOR2 is connected with the D input end of d type flip flop D3, the Q output terminal of d type flip flop D3 is the 3rd output terminal of three digit counters, the clock end of three d type flip flop D1～D3 connects and the count pick up clock altogether.
preferably, described three input voting machines comprise two transmission gate C1～C2, an XOR gate and a phase inverter, wherein: the first input end of XOR gate is the first input end of three input voting machines, the second input end of XOR gate is connected with the input end of transmission gate C1 and is the second input end of three input voting machines, the input end of transmission gate C2 is the 3rd input end of three input voting machines, the output terminal of XOR gate and the input end of phase inverter, the P management and control utmost point processed of transmission gate C1 and the N management and control system of transmission gate C2 extremely are connected, the output terminal of phase inverter extremely is connected with the P management and control utmost point processed of transmission gate C2 and the N management and control system of transmission gate C1, the output terminal of transmission gate C1 is connected with the output terminal of transmission gate C2 and is the output terminal of three input voting machines.This constructional hardware expense and low in energy consumption.
Triplication redundancy counter of the present invention by with the result feedback of voting machine to counter, the count results of refresh counter timely, thus eliminate the error accumulation effect of counter; As long as wherein two counters are not made mistakes simultaneously, the normal operation of whole triplication redundancy counter with regard to continuing.
Description of drawings
Fig. 1 is the structural representation of traditional triplication redundancy counter.
Fig. 2 (a) is the structural representation of voting machine in traditional triple-modular redundancy system.
Fig. 2 (b) is the truth table of voting machine in traditional triple-modular redundancy system.
Fig. 3 is the structural representation of complete triplication redundancy counter.
Fig. 4 is the Output simulation schematic diagram of each device under a counter error situation in complete triplication redundancy counter.
Fig. 5 is the structural representation of triplication redundancy counter of the present invention.
Fig. 6 is the structural representation of three voting machines.
Fig. 7 is the structural representation of three digit counters.
Fig. 8 is the Output simulation schematic diagram of each device under a counter error situation in triplication redundancy counter of the present invention.
Embodiment
, in order more specifically to describe the present invention, below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention and relative theory thereof are elaborated.
As shown in Figure 5, a kind of triplication redundancy counter of self-refresh, comprise three counter J1～J3 and three voting machine B1～B3; Wherein:
the clock end of three counter J1～J3 all receives given counting clock, the output terminal of counter J1 is connected with the first input end of three voting machine B1～B3, the output terminal of counter J2 is connected with the second input end of three voting machine B1～B3, the output terminal of counter J3 is connected with the 3rd input end of three voting machine B1～B3, the output terminal of voting machine B1 is connected and exports count results with the input end of counter J1, the output terminal of voting machine B2 is connected and exports count results with the input end of counter J2, the output terminal of voting machine B3 is connected and exports count results with the input end of counter J3.
Counter is used the Output rusults of corresponding voting machine as self input signal, when counting clock is effective, input signal is added 1 rear as count value and output; If count value reaches the counting maximal value of counter self, counter when counting clock is effective next time with the count value zero clearing.in present embodiment, three counter J1～J3 all adopt three digit counters, and three digit counters comprise three d type flip flop D1～D3, two same or door TOR1～TOR2, a phase inverter and Sheffer stroke gates, as shown in Figure 7, wherein: the input end of phase inverter is connected with the first input end of Sheffer stroke gate and is first input end of three digit counters, the output terminal of phase inverter with or the door first input end of TOR1 and the D input end of d type flip flop D1 be connected, the Q output terminal of d type flip flop D1 is first output terminal of three digit counters, the second input end of Sheffer stroke gate is connected with the second input end same or door TOR1 and is the second input end of three digit counters, output terminal same or door TOR1 is connected with the D input end of d type flip flop D2, the Q output terminal of d type flip flop D2 is the second output terminal of three digit counters, the output terminal of Sheffer stroke gate is connected with first input end same or door TOR2, the second input end same or door TOR2 is the 3rd input end of three digit counters, output terminal same or door TOR2 is connected with the D input end of d type flip flop D3, the Q output terminal of d type flip flop D3 is the 3rd output terminal of three digit counters, the clock end of three d type flip flop D1～D3 connects and the count pick up clock altogether.
Voting machine is used the Output rusults of three counter J1～J3 as self input signal, if having at least two groups identical in three groups of input signals, voting machine is exported this identical input signal, otherwise is output as 0.In present embodiment, three voting machine B1～B3 all adopt three voting machines; Three voting machines comprise three three input voting machine H1～H3, the output terminal of three three input voting machine H1～H3 forms three output terminals of three voting machines, three input ends of three input voting machine H1 receive respectively first Output rusults of three counter J1～J3, three input ends of three input voting machine H2 receive respectively the second Output rusults of three counter J1～J3, and three input ends of three input voting machine H3 receive respectively the 3rd Output rusults of three counter J1～J3; In three voting machine B1～B3, three output terminals of arbitrary voting machine are connected with three input ends of corresponding counter respectively.
as shown in Figure 6, three input voting machines comprise two transmission gate C1～C2, an XOR gate and a phase inverter, wherein: the first input end of XOR gate is the first input end of three input voting machines, the second input end of XOR gate is connected with the input end of transmission gate C1 and is the second input end of three input voting machines, the input end of transmission gate C2 is the 3rd input end of three input voting machines, the output terminal of XOR gate and the input end of phase inverter, the P management and control utmost point processed of transmission gate C1 and the N management and control system of transmission gate C2 extremely are connected, the output terminal of phase inverter extremely is connected with the P management and control utmost point processed of transmission gate C2 and the N management and control system of transmission gate C1, the output terminal of transmission gate C1 is connected with the output terminal of transmission gate C2 and is the output terminal of three input voting machines.
Three input voting machines are used the carry-out bit of three counter J1～J3 as self input signal, if in three groups of input signals, at least two groups are arranged, are 1, and three input voting machines are output as 1, otherwise are output as 0.Wherein, XOR gate use in three groups of input signals any two groups as self input signal, if these two groups of input signals are all 0 or 1, XOR gate is output as 0; If these two groups of input signals are different, XOR gate is output as 1.Phase inverter is done anti-phase processing to the Output rusults of XOR gate, if the Output rusults of XOR gate is 1, phase inverter is output as 0; If the Output rusults of XOR gate is 0, phase inverter output 1.Transmission gate C1 is used arbitrary input signal of XOR gate as self input signal, use the Output rusults of the Output rusults of XOR gate and phase inverter as self control signal, if the Output rusults of XOR gate be 0 and the Output rusults of phase inverter be 1, transmission gate C1 directly exports self input signal, otherwise output signal not.Transmission gate C2 is used in three groups of input signals by XOR gate as last group signal of residue of input as self input signal, use the Output rusults of the Output rusults of XOR gate and phase inverter as this self control signal, if the Output rusults of XOR gate be 1 and the Output rusults of phase inverter be 0, transmission gate C2 directly exports self input signal, otherwise output signal not.
Fig. 8 is the simulation result of present embodiment, can find out that the improper value 4 that counter J3 occurs just is refreshed correctly (not so the value after this counters error accumulation should be 5) when next counting clock is effective, the improper value 7 of in like manner counter J2 appearance also is refreshed correctly when next counting clock is effective.As long as wherein two counters are not made mistakes simultaneously, the self-refresh triplication redundancy counter of present embodiment just can well be eliminated the cumulative errors of counter, thereby guarantees the reliability of triple-modular redundancy system.
Claims (6)
1. the triplication redundancy counter of a self-refresh, is characterized in that: comprise three counter J1～J3 and three voting machine B1～B3; Wherein:
the clock end of three counter J1～J3 all receives given counting clock, the output terminal of counter J1 is connected with the first input end of three voting machine B1～B3, the output terminal of counter J2 is connected with the second input end of three voting machine B1～B3, the output terminal of counter J3 is connected with the 3rd input end of three voting machine B1～B3, the output terminal of voting machine B1 is connected and exports count results with the input end of counter J1, the output terminal of voting machine B2 is connected and exports count results with the input end of counter J2, the output terminal of voting machine B3 is connected and exports count results with the input end of counter J3.
2. triplication redundancy counter according to claim 1 is characterized in that: described counter is used the Output rusults of corresponding voting machine as self input signal, when counting clock is effective, input signal is added 1 rear as count value and output; If described count value reaches the counting maximal value of counter self, counter when counting clock is effective next time with described count value zero clearing.
3. triplication redundancy counter according to claim 1, it is characterized in that: described voting machine is used the Output rusults of three counter J1～J3 as self input signal, if have at least two groups identical in three groups of input signals, voting machine is exported this identical input signal, otherwise is output as 0.
4. triplication redundancy counter according to claim 1, it is characterized in that: described three counter J1～J3 all adopt three digit counters, and three voting machine B1～B3 all adopt three voting machines; Described three voting machines comprise three three input voting machine H1～H3, the output terminal of three three input voting machine H1～H3 forms three output terminals of three voting machines, three input ends of three input voting machine H1 receive respectively first Output rusults of three counter J1～J3, three input ends of three input voting machine H2 receive respectively the second Output rusults of three counter J1～J3, and three input ends of three input voting machine H3 receive respectively the 3rd Output rusults of three counter J1～J3.
5. triplication redundancy counter according to claim 4 is characterized in that: described three digit counters comprise three d type flip flop D1～D3, two with or door TOR1～TOR2, a phase inverter and Sheffer stroke gates, wherein: the input end of phase inverter is connected with the first input end of Sheffer stroke gate and is first input end of three digit counters, the output terminal of phase inverter with or the door first input end of TOR1 and the D input end of d type flip flop D1 be connected, the Q output terminal of d type flip flop D1 is first output terminal of three digit counters, the second input end of Sheffer stroke gate is connected with the second input end same or door TOR1 and is the second input end of three digit counters, output terminal same or door TOR1 is connected with the D input end of d type flip flop D2, the Q output terminal of d type flip flop D2 is the second output terminal of three digit counters, the output terminal of Sheffer stroke gate is connected with first input end same or door TOR2, the second input end same or door TOR2 is the 3rd input end of three digit counters, output terminal same or door TOR2 is connected with the D input end of d type flip flop D3, the Q output terminal of d type flip flop D3 is the 3rd output terminal of three digit counters, the clock end of three d type flip flop D1～D3 connects and the count pick up clock altogether.
6. triplication redundancy counter according to claim 4 is characterized in that: described three input voting machines comprise two transmission gate C1～C2, an XOR gate and a phase inverter, wherein: the first input end of XOR gate is the first input end of three input voting machines, the second input end of XOR gate is connected with the input end of transmission gate C1 and is the second input end of three input voting machines, the input end of transmission gate C2 is the 3rd input end of three input voting machines, the output terminal of XOR gate and the input end of phase inverter, the P management and control utmost point processed of transmission gate C1 and the N management and control system of transmission gate C2 extremely are connected, the output terminal of phase inverter extremely is connected with the P management and control utmost point processed of transmission gate C2 and the N management and control system of transmission gate C1, the output terminal of transmission gate C1 is connected with the output terminal of transmission gate C2 and is the output terminal of three input voting machines.
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| CN103731130A (en) * | 2013-12-27 | 2014-04-16 | 华为技术有限公司 | Universal fault-tolerant error-correction circuit, universal decoder and triple-module redundancy circuit |
| CN104575589A (en) * | 2014-12-27 | 2015-04-29 | 中国电子科技集团公司第三十八研究所 | Radiation-resistant SRAM self-refresh circuit with high utilizable ratio, and self-refresh method of radiation-resistant SRAM self-refresh circuit |
| CN104866390A (en) * | 2015-04-15 | 2015-08-26 | 中国科学院高能物理研究所 | Triple modular redundancy controller for static random access memory |
| CN108055031A (en) * | 2017-12-14 | 2018-05-18 | 北京时代民芯科技有限公司 | A kind of triplication redundancy structure of self- recoverage anti-single particle soft error accumulation |
| CN109412558A (en) * | 2018-12-29 | 2019-03-01 | 灿芯半导体(上海)有限公司 | The transmitting line of random code jittering noise is eliminated in a kind of mipi |
| CN111525919A (en) * | 2020-05-27 | 2020-08-11 | 上海微阱电子科技有限公司 | Redundancy structure with feedback correction |
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| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
| CN103578567B (en) * | 2013-11-18 | 2016-06-29 | 中国电子科技集团公司第五十八研究所 | Based on triplication redundancy Flouride-resistani acid phesphatase self-refresh register |
| CN103731130A (en) * | 2013-12-27 | 2014-04-16 | 华为技术有限公司 | Universal fault-tolerant error-correction circuit, universal decoder and triple-module redundancy circuit |
| CN103731130B (en) * | 2013-12-27 | 2017-01-04 | 华为技术有限公司 | General fault-tolerant error correction circuit and the decoder of application thereof and triplication redundancy circuit |
| US9577960B2 (en) | 2013-12-27 | 2017-02-21 | Huawei Technologies Co., Ltd. | Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it |
| CN104575589B (en) * | 2014-12-27 | 2017-06-30 | 中国电子科技集团公司第三十八研究所 | A kind of radiation-resistant SRAM self-refresh circuits of availability high and its self-refresh method |
| CN104575589A (en) * | 2014-12-27 | 2015-04-29 | 中国电子科技集团公司第三十八研究所 | Radiation-resistant SRAM self-refresh circuit with high utilizable ratio, and self-refresh method of radiation-resistant SRAM self-refresh circuit |
| CN104866390A (en) * | 2015-04-15 | 2015-08-26 | 中国科学院高能物理研究所 | Triple modular redundancy controller for static random access memory |
| CN104866390B (en) * | 2015-04-15 | 2018-07-20 | 中国科学院高能物理研究所 | Asynchronous static random access memory triplication redundancy controller |
| CN108055031A (en) * | 2017-12-14 | 2018-05-18 | 北京时代民芯科技有限公司 | A kind of triplication redundancy structure of self- recoverage anti-single particle soft error accumulation |
| CN108055031B (en) * | 2017-12-14 | 2021-04-13 | 北京时代民芯科技有限公司 | Self-recovery triple modular redundancy structure for resisting single-particle soft error accumulation |
| CN109412558A (en) * | 2018-12-29 | 2019-03-01 | 灿芯半导体(上海)有限公司 | The transmitting line of random code jittering noise is eliminated in a kind of mipi |
| CN109412558B (en) * | 2018-12-29 | 2023-09-05 | 灿芯半导体(上海)股份有限公司 | Transmitting circuit for eliminating random code dithering noise in mipi |
| CN111525919A (en) * | 2020-05-27 | 2020-08-11 | 上海微阱电子科技有限公司 | Redundancy structure with feedback correction |
| CN111525919B (en) * | 2020-05-27 | 2023-09-26 | 上海微阱电子科技有限公司 | Redundant structure with feedback correction |
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