CN103248352A - Low-voltage differential signal driving circuit and electronic device compatible with wired transmission - Google Patents

Abstract

A low voltage differential signal driving circuit and an electronic device compatible with wired transmission are provided. The low voltage differential signal driving circuit has positive and negative differential output terminals, an automatic level selector, an output level detector, and a transition accelerator. The positive and negative differential output terminals are used for supplying a differential output signal of a transmission interface according to a data signal. The automatic level selector outputs a reference voltage based on the transmission interface. The output level detector generates a low-to-high (or high-to-low) transition acceleration control signal based on the data signal, the reference voltage, and the VTXP signal on the positive differential output (or the VTXN signal on the negative differential output). According to the low-to-high (or high-to-low) transition acceleration control signal, the transition accelerator is coupled to the positive (or negative) differential output terminal to the high voltage source and coupled to the negative (or positive) differential output terminal to the low voltage source to accelerate the transition of the differential output signal.

Description

Low-voltage differential signal driving circuit and electronic device compatible with wired transmission

technical field

The invention relates to a low voltage differential signal (low voltage differential signal, LVDS) drive circuit and an electronic device using the circuit.

Background technique

Low operating voltage is a common power saving design.

However, regarding high-speed transmission interfaces, for example, high-definition multimedia interface (high-definition multimedia interface, HDMI), serial advanced technology attachment (serial advanced technology attachment, SATA) interface, peripheral component interconnect express (PCIE) interface, universal serial bus (universal serial bus, USB) interface, etc., the applied low-voltage differential signal drive circuit is limited by the low operating voltage, and its signal transition rate (slew rate) is dragged down, which affects the transmission efficiency.

Contents of the invention

The invention discloses a low voltage differential signal (LVDS) drive circuit and an electronic device compatible with wired transmission.

A low-voltage differential signal driving circuit realized according to an embodiment of the present invention includes a positive differential output terminal, a negative differential output terminal, an automatic level selector, an output level detector, and a transition state accelerator. The positive and negative differential output terminals are coupled to a transmission interface, and a differential output signal is provided to the transmission interface according to a data signal. The automatic level selector outputs a reference voltage according to the transmission interface. Based on the data signal, the reference voltage, and a VTXP signal on the positive differential output, the output level detector generates a low-to-high transition acceleration control signal. According to the low-to-high transition acceleration control signal, the transition accelerator couples the positive differential output terminal to a high voltage source, and couples the negative differential output terminal to a low voltage source. In this way, the low-to-high transition of the differential output signal can be effectively accelerated.

A low-voltage differential signal driving circuit realized according to an embodiment of the present invention includes: a positive differential output terminal, a negative differential output terminal, an automatic level selector, an output level detector, and an Transition accelerator. The above-mentioned positive, negative differential output terminals are coupled to a transmission interface, and a differential output signal is supplied to the transmission interface according to a data signal. Corresponding to the transmission interface, the automatic level selector outputs a reference voltage. The output level detector generates a high-to-low transition acceleration control signal based on an inverted signal of the data signal, the reference voltage, and a VTXN signal on the negative differential output terminal. According to the high-to-low transition acceleration control signal, the transition accelerator couples the positive differential output terminal to a low voltage source, and couples the negative differential output terminal to a high voltage source. In this way, the high-to-low transition of the differential output signal can be effectively accelerated.

Another embodiment of the present invention further discloses an electronic device compatible with wired transmission. The electronic device includes the aforementioned low-voltage differential signal drive circuit and a microprocessor. The microprocessor is used for identifying a transmission interface coupled to the low voltage differential signal driving circuit. According to the identification result, the microprocessor controls the automatic level selector to generate the reference voltage corresponding to the transmission interface.

Another embodiment of the present invention discloses a low-voltage differential signal driving circuit for a transmission interface including: a sending circuit, a transition accelerator, and an output level detector. The sending circuit respectively generates potentials at a positive differential output terminal and a negative differential output terminal to supply a differential output signal. When the differential output signal transitions from low level to high level, the transition accelerator connects the positive differential output terminal to a high voltage source, and connects the negative differential output terminal to a low voltage source. When the differential output signal transitions from high level to low level, the transition accelerator connects the positive differential output terminal to the low voltage source, and connects the negative differential output terminal to the high voltage source. The control of the transition accelerator by the output level detector refers to a reference voltage corresponding to the transmission interface and the potential on the positive differential output terminal or the negative differential output terminal.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, the following specific examples will be described in detail with reference to the accompanying drawings.

Description of drawings

Fig. 1 illustrates an embodiment of a signal transceiving structure;

FIG. 2 illustrates a low voltage differential signal driving circuit 200 according to an embodiment of the present invention;

FIG. 3 illustrates the waveforms of the first to fourth control signals CS1...CS4 and the differential output signal Vo (ie TXP-TXN);

FIG. 4 is a block diagram illustrating an automatic level selector 402 and an output level detector 404 according to one embodiment of the present invention;

FIG. 5 illustrates an automatic level selector 500 according to an embodiment of the present invention;

FIG. 6 illustrates an output level detector 600 according to an embodiment of the present invention;

Fig. 7 illustrates waveforms of control signals CS1...CS4, VTXP and VTXN signals, and differential output signal Vo according to an embodiment of the present invention, wherein the action time interval of transition acceleration is adapted to the currently used transmission interface; and

FIG. 8 illustrates an electronic device according to an embodiment of the present invention.

【Symbol Description】

100~ Signal transceiver system;

102~sending end; 104~receiving end;

106~digital signal transmitter; 108~digital signal receiver;

200~ low voltage differential signal drive circuit;

202~transition accelerator; 204~sending circuit;

402~automatic level selector; 404~output level detector;

500~ automatic level selector;

600~ output level detector;

702~Arrows indicate the disabling trigger of CS3;

704~Arrows indicate the disabling trigger of CS4;

800~electronic device; 802~receiving end;

804~low differential signal drive circuit; 806~microprocessor;

AND1, AND2~AND gate;

CS1, CS2~first and second control (or data) signals;

~ The inversion signal of CS1 and CS2;

CS3, CS4~the third and fourth control signals (also known as low-to-high transition acceleration control signal, high-to-low transition acceleration control signal);

~CS3、CS4的反相信号；

~The inversion signal of CS3 and CS4;

DT~ the enable pin of the comparator;

I1...I6, Itotal~current;

I_path1, I_path2~the first and second current paths;

Is ~ current source;

ISP~current control signal; ISP<0:5>~multiple bits of ISP;

N1...N4~N channel device;

P1...P4~P channel device;

R, R1 and R2~ resistance;

SP, SN~connection nodes provided by different current sources Is;

~电源关闭信号PD的反相信号；

~The inversion signal of the power off signal PD;

Sync_COMP1 and Sync_COMP2 ~ comparator;

SW1...SW6~ current control switch;

TI1, TI2, TI3 three different transmission interfaces;

TXP, TXN~ positive and negative differential output (end);

Vbias ~ bias voltage;

VDD, VSS~high and low voltage sources;

VIN and VIP, VON and VOP~the input and output pins of the comparator;

Vlevel~reference voltage;

Vo~ differential output signal (ie TXP-TXN);

VTXP, VTXN~signals on the positive and negative differential outputs.

Detailed ways

Various embodiments of the present invention are disclosed below for the purpose of explaining the basic principles of the present invention and not intended to limit the scope of the invention. The scope of the invention should be defined by the claims.

FIG. 1 illustrates a signal transceiving structure. A signal transceiving system 100 includes a sending end 102 and a receiving end 104 . The sending end 102 includes a digital signal transmitter 106 . The receiving end 104 includes a digital signal receiver 108 . The digital signal transmitter 106 uses a positive differential output TXP and a negative differential output TXN to provide a differential output signal Vo for digital signal transmission. The digital signal receiver 108 receives the positive differential output TXP and the negative differential output TXN from the digital signal transmitter 106, and uses a comparator to compare the received signals, thereby converting the differential output signal Vo into a digital model.

The signal transceiving structure 100 can be realized by various digital signal transmission interfaces, for example, HDMI interface, SATA interface, USB interface, PCIE interface, etc.

A low voltage differential signaling (LVDS) driving circuit is used to generate and drive the positive and negative differential outputs TXP and TXN.

FIG. 2 illustrates an LVDS driving circuit 200 disclosed according to an embodiment of the present invention. The LVDS driving circuit 200 includes a positive differential output terminal (also labeled as TXP) and a negative differential output terminal (also labeled as TXN) for supplying a differential output signal Vo. The LVDS driving circuit 200 further includes a transition accelerator 202 for accelerating the transition of the differential output signal Vo based on the transition action of the differential output signal Vo. The operation of the transition accelerator 202 is discussed below. When the differential output signal Vo changes from a low level to a high level, the transition accelerator 202 couples the positive differential output terminal TXP to a high voltage source VDD, and couples the negative differential output terminal TXN to a low voltage source. Voltage source VSS. When the differential output signal Vo changes from a high level to a low level, the transition accelerator 202 couples the positive differential output terminal TXP to the low voltage source VSS, and couples the negative differential output terminal TXN to the High voltage source VDD. In this way, the differential output signal Vo can transition at an appropriate speed without being affected by the low operating voltage.

The following paragraphs discuss the LVDS driver circuit 200 in detail.

In the illustrated embodiment, the circuit 200 further includes a transmitting circuit 204, which includes an impedance unit (implemented by resistors R1 and R2 in this embodiment) and two current path generating circuits (details are described in subsequent paragraphs). The impedance unit (composed of R1 and R2 ) is coupled between the positive differential output terminal TXP and the negative differential output terminal TXN. The two current path generation circuits are enabled in turn to form a first current path I_path1 and a second current path I_path2 respectively, allowing current to flow through the impedance unit (R1 and R2) in different directions—in this way, That is, the differential output signal Vo supplied by the above-mentioned positive and negative differential output terminals TXP and TXN can be controlled. The current flowing through the first current path I_path1 or the second current path I_path2 is supplied by a first current source coupled to the high voltage source VDD and a second current source coupled to the low voltage source VSS. As shown in FIG. 2 , the first and second current sources are both marked with Is. The first and the second current source are coupled to each other via the first or the second current path I_path1 or I_path2. As shown in FIG. 2 , the first current source Is coupled to the high voltage source VDD supplies a connection point SP, and the second current source Is coupled to the low voltage source VSS supplies a connection point SN. The connection points SP and SN are coupled to each other via the first current path I_path1 or the second current path I_path2 .

(为第一控制信号CS1的反相信号)控制。第二电流路径控制开关N1耦接在该负差动输出端TXN以及该连结点SN之间，由该第一控制信号CS1控制。第一以及第二电流路径控制开关P1以及N1由该第一控制信号CS1的高电平状态导通，以建立所述第一电流路径I_path1，引导电流流经该阻抗单元(R1与R2)。如此一来，正与负差动输出端TXP与TXN之间形成正电位差，差动输出信号Vo为高电平。This paragraph discusses the first current path generation circuit forming the first current path I_path1. The first current path generation circuit includes a first current path control switch and a second current path control switch. In the embodiment shown in FIG. 2 , the first current path control switch is realized by a P-channel device P1 , and the second current path control switch is realized by an N-channel device N1 . The first current path control switch P1 is coupled between the connection point SP and the positive differential output terminal TXP, controlled by an inverted first control signal

(is the inversion signal of the first control signal CS1) control. The second current path control switch N1 is coupled between the negative differential output terminal TXN and the node SN, and is controlled by the first control signal CS1. The first and second current path control switches P1 and N1 are turned on by the high level state of the first control signal CS1 to establish the first current path I_path1 to guide current to flow through the impedance unit ( R1 and R2 ). In this way, a positive potential difference is formed between the positive and negative differential output terminals TXP and TXN, and the differential output signal Vo is at a high level.

(为第二控制信号CS2的反相信号)控制。第四电流路径控制开关N2耦接在正差动输出端TXP以及连结点SN之间，由第二控制信号CS2控制。第二控制信号CS2的相位可为(并不限定的)第一控制信号CS1的反相。第三以及第四电流路径控制开关P2以及N2可由该第二控制信号CS2的高电平状态导通，以形成所述第二电流路径I_path2使电流流经该阻抗单元(R1以及R2)。如此一来，正与负差动输出端TXP以及TXN之间存在一负电位差，差动输出信号Vo为低电平。This paragraph discusses the second current path generation circuit forming the second current path I_path2. The second current path generation circuit includes a third current path control switch and a fourth current path control switch. In the embodiment shown in FIG. 2 , the third current path control switch is realized by a P-channel device P2 , and the fourth current path control switch is realized by an N-channel device N2 . The third current path control switch P2 is coupled between the connection point SP and the negative differential output terminal TXN, controlled by an inverted second control signal

(is the inversion signal of the second control signal CS2) control. The fourth current path control switch N2 is coupled between the positive differential output terminal TXP and the node SN, and is controlled by the second control signal CS2. The phase of the second control signal CS2 may be (not limited to) the inverse phase of the first control signal CS1. The third and fourth current path control switches P2 and N2 can be turned on by the high level state of the second control signal CS2 to form the second current path I_path2 for current to flow through the impedance unit ( R1 and R2 ). In this way, there is a negative potential difference between the positive and negative differential output terminals TXP and TXN, and the differential output signal Vo is at a low level.

Regarding the embodiment shown in FIG. 2 , when the first control signal CS1 switches to the enabled state (high level) and the second control signal CS2 switches to the disabled state (low level), the differential output signal Vo changes from low level to transition to a high level. When the first control signal CS1 is switched to a disabled state and the second control signal CS2 is switched to an enabled state, the differential output signal Vo changes from a high level to a low level.

以及一第三控制信号CS3控制，

可为CS3的反相信号，且CS3又可称为低至高转态加速控制信号。第一以及第二转态加速开关P3以及N3可在该差动输出信号Vo自低电平转态为高电平时导通。随着第一控制信号CS1切换为致能状态(即，差动输出信号Vo由低电平转态为高电平)，第三控制信号CS3可切换成致能状态。第三转态加速开关P4用于耦接该负差动输出端TXN至高电压源VDD，且该第四转态加速开关N4用于耦接该正差动输出端TXP至该低电压源VSS。第三以及第四转态加速开关P4以及N4分别由一反相第四控制信号以及一第四控制信号CS4控制。

可为CS4的反相信号，且CS4又命名为高至低转态加速控制信号。第三以及第四转态加速开关P4以及N4可在该差动输出信号Vo由高电平转态为低电平时导通。随着第二控制信号CS2切换为致能状态(即，差动输出信号Vo由高电平转态为低电平)，第四控制信号CS4可切换为致能状态。This paragraph discusses the structure of the transition accelerator 202, which includes four transition acceleration switches. In one embodiment, the first transition acceleration switch is realized by a P channel device P3, the second transition acceleration switch is realized by an N channel device N3, and the third transition acceleration switch is realized by a P channel device P4 Realize, and the fourth transition acceleration switch is realized by an N-channel device N4. As shown in the figure, the first transition acceleration switch P3 is used to couple the positive differential output terminal TXP to the high voltage source VDD, and the second transition acceleration switch N3 is used to couple the negative differential output terminal TXN to the low voltage source VDD. Voltage source VSS. The first and second transition acceleration switches P3 and N3 are respectively controlled by an inverted third control signal

and a third control signal CS3 control,

It can be the inversion signal of CS3, and CS3 can also be called the low-to-high transition acceleration control signal. The first and second transition acceleration switches P3 and N3 are turned on when the differential output signal Vo transitions from a low level to a high level. As the first control signal CS1 switches to the enabled state (that is, the differential output signal Vo transitions from low level to high level), the third control signal CS3 may switch to the enabled state. The third transition acceleration switch P4 is used for coupling the negative differential output terminal TXN to the high voltage source VDD, and the fourth transition acceleration switch N4 is used for coupling the positive differential output terminal TXP to the low voltage source VSS. The third and fourth transition acceleration switches P4 and N4 are respectively controlled by an inverted fourth control signal and controlled by a fourth control signal CS4.

It can be the inversion signal of CS4, and CS4 is also named as high-to-low transition acceleration control signal. The third and fourth transition acceleration switches P4 and N4 are turned on when the differential output signal Vo transitions from a high level to a low level. As the second control signal CS2 switches to the enabled state (that is, the differential output signal Vo transitions from high level to low level), the fourth control signal CS4 can switch to the enabled state.

(低至高转态加速控制信号CS3的反相信号)。此外，N通道装置N3以其源极直接连结低电压源VSS，并以漏极直接连结负差动输出端TXN，且更以栅极接收该低至高转态加速控制信号CS3。P通道装置P4以其源极直接连结高电压源VDD，并以漏极直接连结负差动输出端TXN，更以栅极接收信号

(高至低转态加速控制信号CS4的反相信号)。N通道装置N4以其源极直接连结低电压源VSS，并以漏极直接连结正差动输出端TXP，更以栅极接收该高至低转态加速控制信号CS4。Specifically, in order to reduce head room reduction in the embodiment shown in FIG. 2 , the first and third transition acceleration switches P3 and P4 are directly connected to the high voltage source VDD, and the second and fourth The transition acceleration switches N3 and N4 are directly connected to the low voltage source VSS. The source of the P-channel device P3 is directly connected to the high voltage source VDD, the drain is directly connected to the positive differential output terminal TXP, and the gate receives the signal

(The inverse signal of the low-to-high transition acceleration control signal CS3). In addition, the source of the N-channel device N3 is directly connected to the low voltage source VSS, the drain is directly connected to the negative differential output terminal TXN, and the gate receives the low-to-high transition acceleration control signal CS3. The P-channel device P4 directly connects its source to the high voltage source VDD, directly connects its drain to the negative differential output terminal TXN, and uses its gate to receive signals

(inverted signal of high-to-low transition acceleration control signal CS4). The source of the N-channel device N4 is directly connected to the low voltage source VSS, the drain is directly connected to the positive differential output terminal TXP, and the gate receives the high-to-low transition acceleration control signal CS4.

FIG. 3 illustrates waveforms of the first to fourth control signals CS1 to CS4 and the differential output signal Vo (ie, TXP-TXN). As shown in the figure, the transition accelerator 202 (controlled by the third and fourth control signals CS3 and CS4, CS3 and CS4 are respectively called the low-to-high transition acceleration control signal and the high-to-low transition acceleration control signal) will accelerate The transition of the differential output signal Vo. In particular, in some implementations, enabling of the third and fourth control signals CS3 and CS4 is limited to a preset time interval. The preset time interval is adjusted based on the transmission interface used. The output signals of different transmission interfaces may have different potential requirements. The conduction intervals of the first to fourth transition acceleration switches P3 , N3 , P4 , and N4 are therefore limited to avoid over-acceleration of signal transitions to meet the specifications of the applied transmission interface.

The transition acceleration design disclosed in this application works particularly well in low operating voltage environments. For example, referring to FIG. 2 , the transition accelerator 202 acts directly on the two ends of the impedance unit (composed of R1 and R2 ). Therefore, the RC charging time constant is considerably reduced, so that the transition rate of the differential output signal Vo is effectively increased. For at least the above reasons, the impact of the low operating voltage environment on the signal transition rate is not significant.

In another embodiment, a low-voltage differential signal driver may further include an automatic level selector and an output level detector for generating the low-to-high transition acceleration control signal CS3 or/and the high-to- Low transition acceleration control signal CS4. FIG. 4 illustrates a block diagram of an automatic level selector 402 and an output level detector 404 implemented according to an embodiment of the present invention. The current control signal ISP controls a plurality of current sources and is related to the transmission interface driven by the LVDS driving circuit. The automatic level selector 402 outputs a reference voltage Vlevel according to the current control signal ISP. The reference voltage Vlevel is input together with the control signals CS1 and CS2 (referred to as the first and second data signals respectively), the VTXP signal on the positive differential output terminal TXP, and the VTXN signal on the negative differential output terminal TXN. level detector 404 . According to the signals CS1, CS2, VTXP, VTXN, and Vlevel, the output level detector 404 generates the low-to-high transition acceleration control signal CS3, the high-to-low transition acceleration control signal CS4, and the inverted signal of the two as well as

FIG. 5 illustrates an automatic level selector 500 implemented according to one embodiment of the present invention. The automatic level selector 500 includes a resistance element R, a plurality of current sources (as shown in the figure, namely, the transistors biased by Vbias to generate currents I1 to I6 respectively), and a plurality of current control switches SW1 to SW6. The current control switches SW1 to SW6 are respectively connected in series with the current sources, and are turned on or off according to the corresponding bits in the signal ISP<0:5>, so as to control the current Itotal flowing through the resistance element R. The aspect ratios (W/L) of the transistors generating the currents I1 . . . I6 are specially designed to generate corresponding Itotal according to different value combinations of ISP<0:5>. In one embodiment, the first and second current sources Is in the sending circuit are also controlled by the signal ISP in the same manner. The signal ISP<0:5> is set according to the voltage specification of the output signal of the transmission interface. Therefore, the value of the current Itotal is adjusted according to different requirements of different transmission interfaces. The reference voltage Vlevel required by the operating conditions of different transmission interfaces is adjusted by controlling the current control signal ISP to set the current Itotal flowing through the impedance element R.

FIG. 6 illustrates an output level detector 600 implemented according to one embodiment of the present invention. The output level detector 600 includes two comparators Sync_COMP1 and Sync_COMP2 and two AND gates AND1 and AND2.

以及控制信号CS1，且具有一输出端耦接该比较器Sync_COMP1的致能引脚DT。与门AND2接收该反相电源关闭信号

以及控制信号CS2，且具有一输出端耦接该比较器Sync_COMP2的致能引脚DT。电源关闭信号PD在正常操作下为低电平逻辑。因此，比较器Sync_COMP1以及Sync_COMP2的致能引脚DT分别随控制信号CS1、CS2转态。当电源关闭信号PD启动(高电平逻辑)，比较器Sync_COMP1以及Sync_COMP2除能。电源关闭信号PD于该低电压差动信号驱动电路为一电源关闭状态时致能，以除能上述比较器Sync_COMP1以及Sync_COMP2，目的为节省电力、或关闭采该传输接口的电子装置。The AND gate AND1 receives an inverted power-off signal

and the control signal CS1, and has an output end coupled to the enable pin DT of the comparator Sync_COMP1. AND gate AND2 receives the inverting power off signal

and the control signal CS2, and has an output terminal coupled to the enable pin DT of the comparator Sync_COMP2. The power down signal PD is logic low in normal operation. Therefore, the enable pins DT of the comparators Sync_COMP1 and Sync_COMP2 respectively change states according to the control signals CS1 and CS2. When the power down signal PD is enabled (high level logic), the comparators Sync_COMP1 and Sync_COMP2 are disabled. The power-off signal PD is enabled when the low-voltage differential signal driving circuit is in a power-off state to disable the above-mentioned comparators Sync_COMP1 and Sync_COMP2 for saving power or shutting down electronic devices adopting the transmission interface.

Under the operation of the output signal of the AND gate AND1, the comparator Sync_COMP1 is enabled according to CS1, and compares the VTXP signal with the reference voltage Vlevel. When the comparator Sync_COMP1 is enabled under the high level drive of CS1, if the VTXP signal is lower than the reference voltage Vlevel, the comparator Sync_COMP1 maintains the enable state of the low-to-high transition acceleration control signal CS3 (CS3 is high level and is low); otherwise, the low-to-high transition acceleration control signal CS3 is disabled. According to the above design, if the VTXP signal reaches the reference voltage Vlevel, the low-to-high transition acceleration operation provided by the first and second transition acceleration switches P3 and N3 of the transition accelerator 202 in FIG. 2 is suspended. Since the magnitude of the reference voltage Vlevel is related to the transmission interface, the action time interval of the low-to-high transition acceleration is properly adjusted according to the transmission interface used.

为低电平)；否则，该高至低转态加速控制信号CS4除能。根据以上设计，如果VTXN信号达到参考电压Vlevel，图2转态加速器202的第三以及第四转态加速开关P4以及N4所提供的高至低转态加速操作中止。由于参考电压Vlevel的大小与传输接口相关，该高至低转态加速的动作时间区间乃随着所使用的传输接口适当调节。Under the operation of the output signal of the AND gate AND2, the comparator Sync_COMP2 is enabled according to CS2, and compares the VTXN signal with the reference voltage Vlevel. When the comparator Sync_COMP2 is enabled under the high level drive of CS2, if the VTXN signal is lower than the reference voltage Vlevel, the comparator Sync_COMP2 maintains the enable state of the high-to-low transition acceleration control signal CS4 (CS4 is high level and

is low); otherwise, the high-to-low transition acceleration control signal CS4 is disabled. According to the above design, if the VTXN signal reaches the reference voltage Vlevel, the high-to-low transition acceleration operation provided by the third and fourth transition acceleration switches P4 and N4 of the transition accelerator 202 in FIG. 2 is suspended. Since the magnitude of the reference voltage Vlevel is related to the transmission interface, the action time interval of the high-to-low transition acceleration is properly adjusted according to the transmission interface used.

The above AND gates AND1 and AND2 are unnecessary components. In other implementations, the control signals CS1 and CS2 may be directly connected to enable pins DT of the comparators Sync_COMP1 and Sync_COMP2 respectively.

According to one embodiment, FIG. 7 illustrates the waveforms of the above-mentioned control signals CS1 to CS4, the above-mentioned VTXP and VTXN signals, and the Vo (ie TXP-TXN) signal, which introduces the transition acceleration action time interval adjusted with the transmission interface. The control signals CS1 and CS2 generate a positive/negative difference between the differential output terminals TXP and TXN to transmit the differential output signal Vo. According to the control signals CS1 and CS2, the signals of the terminals TXP and TXN transition, and the signals CS3 and CS4 are formed accordingly. As indicated by arrow 702 , the control signal CS3 enabled according to the low-to-high transition of CS1 is disabled when the VTXP signal reaches the reference voltage Vlevel. The disabling of the control signal CS3 will cause the acceleration of the low-to-high transition of (TXP-TXN) to stop accordingly, so as to meet the operation requirements of the adopted transmission interface. In addition, referring to arrow 704 , the control signal CS4 enabled according to the low-to-high transition of CS2 is disabled when the VTXN signal reaches the reference voltage Vlevel. The disabling of the control signal CS4 will cause the acceleration of the high-to-low transition of (TXP-TXN) to stop accordingly, so as to meet the operation requirements of the adopted transmission interface. In one implementation manner, the control signals CS1 and CS2 are complementary operations (that is, opposite phases of each other). In another embodiment, the control signals CS1 and CS2 are not limited to complementary operations.

The operation time interval control of the transition acceleration may be applied only to the low-to-high transition acceleration, or may be applied only to the high-to-low transition acceleration. In one embodiment, the output level detection can work according to the CS1, VTXP signal and the reference voltage Vlevel without detecting the VTXN signal—for example, using the components AND1 and Sync_COMP1 in the upper half of Figure 6, but without the lower part of Figure 6 Half of the components AND2 and Sync_COMP2; in this way, only the operating time interval from low to high transition acceleration is adjusted with the transmission interface. In another embodiment, the output level detection can work according to the CS2, VTXN signal and the reference voltage Vlevel without detecting the VTXP signal—for example, using the components AND2 and Sync_COMP2 in the lower half of Figure 6, but without the components shown in Figure 6 The components AND1 and Sync_COMP1 in the upper half; in this way, only the operating time range of high to low transition acceleration is adjusted with the transmission interface.

FIG. 8 illustrates an electronic device 800 implemented according to an embodiment of the present invention. The electronic device 800 is compatible with various transmission interfaces (as shown in the figure, it is compatible with three different transmission interfaces TI1 , TI2 and TI3 ). In the figure, the transmission interface TI2 is selected to establish the wired transmission between the electronic device 800 and a receiving end 802 . The electronic device 800 may include the LVDS driving circuit 804 disclosed above and a microprocessor 806 . The positive and negative differential output terminals TXP and TXN of the low voltage differential signal driving circuit 804 are coupled to the transmission interface TI2 . If the selected interface is detected to be the transmission interface TI2 , the microprocessor 806 sets a corresponding signal ISP (ie, the control signal ISP of the automatic level selector 402 in FIG. 4 ) to the transmission interface TI2 . In this way, the transition acceleration operation time interval of the (TXP-TXN) signal is adjusted to suit the transmission interface TI2.

In another embodiment, the electronic device having the low voltage differential signal driving circuit disclosed above is only compatible with a single transmission interface. At this time, the ISP setting signal corresponding to the single transmission interface can be stored in a register by the manufacturer.

To sum up, the disclosure of the present application includes a transition accelerator for accelerating the transition of a low-voltage differential signal of a transmission interface. The transition accelerator directly connects the differential output terminal to the voltage source. Therefore, the resistor-capacitor charging time constant is significantly suppressed, and the transition speed of the differential output signal is effectively increased. Signal transition speed is thus not limited by low operating voltage environments. The control of the transition accelerator can be based on a reference voltage corresponding to the transmission interface and the voltage value of the differential output terminal, so that the overshoot condition of the signal transition can be effectively avoided.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention The scope defined by the appended claims shall prevail.

Claims (25)

1. A low-voltage differential signal drive circuit, comprising: A positive differential output terminal and a negative differential output terminal are coupled to a transmission interface to provide a differential output signal of the transmission interface according to a first data signal and a second data signal; An automatic level selector, outputting a reference voltage according to the transmission interface; an output level detector for generating a low-to-high transition acceleration control signal based on the first data signal, the reference voltage, and a VTXP signal on the positive differential output; and A transition accelerator is coupled to the positive differential output terminal to a high voltage source and coupled to the low differential output terminal to a low voltage source according to the low-to-high transition acceleration control signal. 2. The low voltage differential signal driving circuit as claimed in claim 1, wherein the output level detector comprises: A first comparator is enabled with the first data signal to compare the VTXP signal with the reference voltage, wherein when the first comparator is enabled with the high level state of the first data signal, and When the VTXP signal is lower than the reference voltage, the first comparator continuously enables the low-to-high transition acceleration control signal; otherwise, the first comparator disables the low-to-high transition acceleration control signal. 3. The low voltage differential signal driving circuit as claimed in claim 2, wherein: The first comparator is also disabled based on a power off signal. 4. The low voltage differential signal driving circuit as claimed in claim 1, wherein: the output level detector also generates a high-to-low transition acceleration control signal based on the second data signal, the reference voltage, and a VTXN signal on the negative differential output; and The transition accelerator is also coupled to the positive differential output terminal to the low voltage source and the negative differential output terminal to the high voltage source according to the high-to-low transition acceleration control signal. 5. The low voltage differential signal driving circuit as claimed in claim 4, wherein the output level detector further comprises: a second comparator enabled according to the second data signal to compare the VTXN signal with the reference voltage, wherein when the second comparator is enabled according to a high level state of the second data signal and the When the VTXN signal is lower than the reference voltage, the second comparator keeps enabling the high-to-low transition acceleration control signal, otherwise, the second comparator disables the high-to-low transition acceleration control signal. 6. The low voltage differential signal driving circuit as claimed in claim 5, wherein: The second comparator is also disabled based on a power off signal. 7. The low voltage differential signal driving circuit as claimed in claim 1, wherein the automatic level selector comprises: a resistive element; and a plurality of current sources and a plurality of current control switches, wherein the plurality of current control switches are respectively connected in series with the plurality of current sources, in: The current source supplies current to the resistance element according to the state of the corresponding current control switch, and the generation of the reference voltage is based on the resistance element and a current value flowing through the resistance element; and The current control switch is turned on or off according to the transmission interface. 8. The low voltage differential signal driving circuit as claimed in claim 4, wherein the transition accelerator comprises: a first transition acceleration switch, which is turned on when the low-to-high transition acceleration control signal is enabled, to couple the positive differential output terminal to the high voltage source; a second transition acceleration switch, which is turned on when the low-to-high transition acceleration control signal is enabled, to couple the negative differential output terminal to the low voltage source; a third transition acceleration switch, which is turned on when the high-to-low transition acceleration control signal is enabled, to couple the negative differential output terminal to the high voltage source; and A fourth transition acceleration switch is turned on when the high-to-low transition acceleration control signal is enabled, so as to couple the positive differential output terminal to the low voltage source. 9. An electronic device compatible with wired transmission, comprising: The low voltage differential signal driving circuit as claimed in claim 4; and A microprocessor detects the transmission interface coupled to the positive and negative differential output terminals to provide detection results to the automatic level selector to generate the reference voltage. 10. A low-voltage differential signal drive circuit designed for a transmission interface, and comprising: a transmitting circuit generating a potential on a positive differential output terminal and generating a potential on a negative differential output terminal to supply a differential output signal; A transition accelerator, when the differential output signal is in a low-to-high transition, connects the positive differential output terminal to a high voltage source, and connects the negative differential output terminal to a low voltage source, and connects the differential output terminal to a low voltage source. connecting the positive differential output to the low voltage source and the negative differential output to the high voltage source when the output signal is in a high-to-low transition; and An output level detector controls the transition accelerator according to a reference voltage corresponding to the transmission interface and the potential on the above-mentioned positive or negative differential output terminal. 11. The LVDS driving circuit as claimed in claim 10, wherein the output level detector comprises: A first comparator, used to control the positive differential output terminal to connect to the high voltage source when the differential output signal is in a low-to-high transition state and the potential on the positive differential output terminal is lower than the reference voltage , and control the negative differential output terminal to connect with the low voltage source. 12. The LVDS driving circuit as claimed in claim 11, wherein the first comparator is also disabled based on a power-off signal. 13. The LVDS driving circuit as claimed in claim 10, wherein the output level detector comprises: A second comparator, used to control the negative differential output terminal to connect to the high voltage source when the differential output signal is in a high-to-low transition state and the potential on the negative differential output terminal is lower than the reference voltage, And control the positive differential output terminal to connect with the negative voltage source. 14. The LVDS driving circuit as claimed in claim 13, wherein the second comparator is also disabled based on a power-off signal. 15. The low voltage differential signal driving circuit as claimed in claim 10, further comprising: An automatic level selector generates the reference voltage according to a current control signal. 16. The low voltage differential signal driving circuit as claimed in claim 15, wherein the automatic level selector comprises: a resistance element; multiple current sources; and multiple current control switches, Wherein, the current source provides current to the resistance element according to the state of the current control switch, Wherein, the conduction state of the current control switch is based on the current control signal, Wherein, the reference voltage is generated based on the resistance element and the current control signal. 17. The LVDS driving circuit as claimed in claim 15, wherein the sending circuit comprises a current source generating a current based on the current control signal. 18. The low voltage differential signal driving circuit as claimed in claim 10, wherein the transition accelerator comprises: a first transition acceleration switch, which is turned on when the differential output signal makes a low-to-high transition, to connect the positive differential output terminal to the high voltage source; and A second transition acceleration switch is turned on when the differential output signal transitions from low to high, so as to connect the negative differential output terminal to the low voltage source. 19. The low-voltage differential signal driving circuit as claimed in claim 18, wherein the conduction condition of the first transition acceleration switch and the second transition acceleration switch further includes that the potential of the positive differential output terminal is lower than the reference Voltage. 20. The LVDS driving circuit as claimed in claim 10, wherein the transition accelerator comprises: a third transition acceleration switch, which is turned on when the differential output signal is in a high-to-low transition, to connect the negative differential output terminal to the high voltage source; and A fourth transition acceleration switch is turned on when the differential output signal transitions from high to low, so as to connect the positive differential output terminal to the low voltage source. 21. The low voltage differential signal driving circuit as claimed in claim 20, wherein the turn-on condition of the third transition acceleration switch and the fourth transition acceleration switch further includes that the potential of the negative differential output terminal is lower than the reference Voltage. 22. The low voltage differential signal driving circuit as claimed in claim 10, wherein the transmitting circuit comprises: a first current path control switch coupled between a first current source coupled to the high voltage source and the positive differential output; and A second current path control switch is coupled between a second current source and the negative differential output terminal, and the second current source is coupled to the low voltage source. 23. The low voltage differential signal driving circuit as claimed in claim 22, wherein the first current source and the second current source generate current according to a current control signal, and the reference voltage is generated based on the current control signal. 24. The low voltage differential signal driving circuit as claimed in claim 10, wherein the transmitting circuit comprises: a third current path control switch coupled between a first current source coupled to the high voltage source and the negative differential output terminal; and A fourth current path control switch is coupled between a second current source and the positive differential output terminal, and the second current source is coupled to the low voltage source. 25. The low voltage differential output signal driving circuit as claimed in claim 24, wherein the first current source and the second current source generate current according to a current control signal, and the reference voltage is generated based on the current control signal.

Images