JP5410318B2 - Output driver circuit - Google Patents

Description

  The present invention relates to an output driver circuit, and more particularly to a technique effective when applied to an output driver circuit for high-speed communication typified by an optical communication system.

  For example, FIG. 6 of Patent Document 1 shows a differential drive circuit in which a driver circuit and an emphasis circuit are commonly connected to a differential output terminal. The driver circuit is constituted by a bridge circuit composed of four MOS transistors, and the power supply voltage is supplied via the source follower circuit. The emphasis circuit is also constituted by a bridge circuit composed of four MOS transistors, and the power supply current is supplied by a constant current source.

Japanese Patent Laying-Open No. 2005-223872

  In recent years, with an increase in communication speed, for example, the communication speed of an optical communication system has changed from 10 Gbps to 25 Gbps, 40 Gbps, and the like. In such a high-speed communication field, it is naturally necessary to increase the circuit speed, and it is desirable to realize reduction of power consumption and improvement of transmission waveform quality. Therefore, these were examined.

  FIGS. 15A and 15B are circuit diagrams showing an example of the configuration of the output driver circuit studied as a premise of the present invention. The output driver circuit shown in FIG. 15A is a so-called CML (Current Mode Logic) differential amplifier circuit DAMP. The DAMP is provided with an external load resistance having an impedance Z0, and the external load resistance having an impedance 2 × Z0 is driven by the DAMP. Further, the output driver circuit shown in FIG. 15B is different from the differential amplifier circuit DAMP shown in FIG. 15A in a pre-emphasis circuit (waveform equalization) including differential pair transistors sharing the differential output node. Circuit) This is a configuration example in which an EMP is provided.

  Here, for example, the data input signal DIN [n] of the current cycle [n] is input to one of the differential inputs in the DAMP, and the inverted data input signal of the previous cycle [n−1] is input to one of the differential inputs in the EMP. When / DIN [n−1] is input, it is possible to generate a data output signal in consideration of intersymbol interference from the previous cycle in the current cycle. When the configuration examples as shown in FIGS. 15A and 15B are used, high-speed operation is possible along with the operation in the current mode. Further, impedance matching and waveform equalization can be easily performed, so that transmission waveform quality can be improved. However, for example, when a tail current of 4 × I0 is supplied to DAMP, only the current I0 that is a quarter of that is supplied to the external load resistor, and the power consumption becomes very large.

  FIGS. 16A and 16B are circuit diagrams showing examples of other configurations in the output driver circuit studied as a premise of the present invention. The output driver circuit shown in FIG. 16A includes a plurality (two in this case) of slice circuits SLC1 and SLC2, and each slice circuit includes two driver circuits DV1 and DV2 each having a CMOS inverter configuration. . In each slice circuit, the output of DV1 is commonly connected to one end of an external load resistor having impedance 2 × Z0, and the output of DV2 is commonly connected to the other end of the external load resistor. For example, when the positive data input signal DIN_P is input to DV1 and the negative data input signal DIN_N is input to DV2, the path of the PMOS transistor MPz11 of DV1 and the NMOS transistor MNz22 of DV2 or the PMOS transistors MPz21 and DV1 of DV2 The external load resistor is driven by the path of the NMOS transistor MNz12.

  Here, when driving the external load resistor, it is necessary to set the impedance on the PMOS transistor side and the impedance on the NMOS transistor side to Z0 for impedance matching. The slice circuits SLC1 and SLC2 have a configuration for realizing this. That is, although not shown, each slice circuit can be set to valid / invalid, and when set to invalid, each MOS transistor constituting DV1 and DV2 is fixed to off. Therefore, since the impedance can be adjusted depending on how many slice circuits are enabled, the impedance can be set to Z0 even if, for example, manufacturing variations occur, and transmission waveform quality can be improved. Further, when such a configuration example is used, since all the power source current is supplied to the external load resistor, it is possible to reduce power consumption. However, since it is a voltage mode operation, there is a possibility that the speed cannot be increased.

  The output driver circuit shown in FIG. 16B has a configuration example in which the waveform equalization function as described above is added to the driver circuit DV1 in FIG. That is, the output is shared with the driver circuit DVp1 to which the positive polarity data input signal DIN_P [n] of the current cycle [n] is inputted, and the negative polarity data input signal DIN_N [n−1] of the previous cycle [n−1]. ] Is added to the driver circuit DVp2. The size (W) of each MOS transistor constituting DVp1 is set larger than the size (W) of each MOS transistor constituting DVp2.

  In such a configuration example, waveform equalization can be performed in the same manner as in FIG. 15B using DVp2 as a pre-emphasis circuit, so that transmission waveform quality can be improved. However, in this case, it is necessary to perform impedance matching including the pre-emphasis circuit (DVp2). For example, when the DVp1 PMOS transistor and the DVp2 NMOS transistor are turned on according to the data pattern, the parallel resistance of the PMOS transistor on-resistance Rp and the NMOS transistor on-resistance Rn is set to the impedance Z0. It is necessary to set validity / invalidity of the above-described slice circuit. Therefore, the impedance adjustment is slightly complicated. Further, when a pre-emphasis circuit is added, for example, a through current from DVp1 to DVp2 is generated, so that power consumption increases.

  As described above, it is not easy to reduce power consumption and improve transmission waveform quality in addition to circuit speedup. Therefore, it is conceivable to use the configuration as described in Patent Document 1 described above. In the configuration of Patent Document 1, as shown in FIGS. 7 to 9, waveform equalization is performed by using both current drive by an emphasis signal (EMP +) and voltage drive by an input signal (IN +) for each data cycle. It is carried out. However, with the technique of Patent Document 1, for example, it is not always possible to sufficiently improve the transmission waveform quality as described above. In order to improve the transmission waveform quality (that is, to expand the eye of the so-called eye pattern), it is desirable to have a circuit configuration that can set an optimal waveform equalization amount and signal amplitude according to the conditions of the communication system. However, the technique of Patent Document 1 cannot cope with these. Furthermore, in the technique of Patent Document 1, there is a possibility that the circuit configuration cannot sufficiently cope with further speeding up depending on the case.

  The present invention has been made in view of the above, and one of its purposes is an output driver circuit capable of reducing power consumption or improving transmission waveform quality in addition to increasing the communication speed. Is to provide. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The first output driver circuit according to the present embodiment receives a voltage signal generation circuit block that drives a differential output node with a voltage according to the logic level of the differential input node, and a transition of the logic level of the differential input node. A pulse signal generation circuit that generates a one-shot pulse signal, and a first current signal generation circuit block that drives the differential output node with a current during the period of the pulse width of the one-shot pulse signal. . The voltage signal generation circuit block performs voltage driving with a first impedance on each of the positive and negative differential output nodes.

  When such a configuration is used, when the signal of the differential output node is transitioned, current driving is performed by the first current signal generation circuit block, so that high-speed signal transition is possible. Thereafter, after the pulse period of the one-shot pulse signal has elapsed, the voltage signal generation circuit block determines the steady-state voltage signal level at the differential output node. In this signal transition period and steady state, the voltage signal generation circuit block functions as an impedance matching circuit. As a result, the transmission waveform quality can be improved. Furthermore, by appropriately setting the pulse period of the one-shot pulse signal according to the applied communication system, appropriate pre-emphasis can be achieved, and transmission waveform quality can be improved. The first current signal generation circuit block may be realized by a single-stage transistor that is turned on by a one-shot pulse signal while a current path is connected between the differential output node and the power supply node. desirable. This can further increase the speed.

  In addition, the second output driver circuit according to the present embodiment includes a voltage signal generation circuit block that drives the differential output node with a voltage according to the logic level of the differential input node, and a logic level of the differential input node. And a second current signal generation circuit block for driving the differential output node with a current having a first current value. The voltage signal generation circuit block connects one of the positive and negative differential output nodes to a first power supply having a first voltage value via a first impedance, and connects the other of the positive and negative differential output nodes to the second voltage. A second power supply having a value is connected via a first impedance. The first current value is set to (first voltage value−second voltage value) / (2 × first impedance).

  When such a configuration is used, current drive by the second current signal generation circuit block is performed not only when the signal of the differential output node is changed but also when the signal is kept in a steady state. The speed can be increased by using the second current signal generation circuit block at the time of signal transition. By using the second current signal generation circuit block in the steady state of the signal, it is possible to expand the voltage amplitude of the differential output node in the steady state as compared with the case where voltage driving by the voltage signal generation circuit block is used. Become. As a result, the transmission waveform quality can be improved. In this signal transition period and steady state, the voltage signal generation circuit block functions as an impedance matching circuit. As a result, the transmission waveform quality can be improved.

  Further, the third output driver circuit according to the present embodiment is a combination of the first output driver circuit and the second output driver circuit described above. That is, at the time of signal transition at the differential output node, current driving is mainly performed by the first and second current signal generation circuit blocks, and at this time, the first current signal generation circuit block functions as a pre-emphasis circuit. As a result, the speed can be increased and the transmission waveform quality can be improved. Thereafter, when the signal at the differential output node becomes a steady state, the second current signal generation circuit block mainly performs current driving. As a result, the voltage amplitude at the differential output node can be increased, and the transmission waveform quality can be improved. In this signal transition period and steady state, the voltage signal generation circuit block functions as an impedance matching circuit. As a result, the transmission waveform quality can be improved.

  When the first to third output driver circuits described above are used, in particular, in the second and third output driver circuits, the steady state voltage amplitude at the differential output node is wide according to the applied communication system. Can be determined from the range. In this way, by using a configuration in which the voltage amplitude is determined from a wide range, it is possible to achieve a reduction in power consumption and an improvement in transmission waveform quality in a balanced manner.

  The effects obtained by the representative embodiments of the invention disclosed in this application will be briefly described. In the output driver circuit, in addition to increasing the communication speed, the power consumption is reduced or the transmission waveform quality is reduced. Improvement can be achieved.

1 is a block diagram illustrating a configuration example of an optical communication system to which an output driver circuit according to a first embodiment of the present invention is applied. (A) is the schematic which shows an example of the structure in the output driver circuit by Embodiment 1 of this invention, (b) is explanatory drawing which shows an example of the power supply voltage relationship of (a). FIG. 3 is a circuit diagram showing a detailed configuration example of the output driver circuit of FIG. 2. (A) is a circuit diagram showing a detailed configuration example of the variable delay circuit in the pulse signal generation circuit of FIG. 3, (b) is a circuit diagram showing a detailed configuration example of the inverting selector circuit in (a). is there. FIG. 4 is a waveform diagram showing an example of the operation of the output driver circuit of FIG. 3. FIG. 6 is a circuit diagram showing an example of the configuration of an output driver circuit according to a second embodiment of the present invention. FIG. 7 is a waveform diagram showing an example of the operation of the output driver circuit of FIG. 6. (A) is a circuit diagram which shows an example of the structure in the output driver circuit by Embodiment 3 of this invention, (b) is explanatory drawing which shows an example of the power supply voltage relationship of (a). FIG. 9 is a waveform diagram showing an example of the operation of the output driver circuit of FIG. FIG. 9 is a circuit diagram showing a detailed configuration example of the output driver circuit of FIG. (A), (b) is a circuit diagram which shows the structural example of the circuit which produces | generates a reference voltage in the output driver circuit of FIG. (A) is a circuit diagram showing a modification of the power supply generation circuit in the output driver circuit of FIG. 10, and (b) is a circuit diagram showing a comparative example. FIG. 10 is a circuit diagram showing an example of the configuration of an output driver circuit according to a fourth embodiment of the present invention. FIG. 10 is a schematic diagram showing an example of the configuration of an output driver circuit according to a fifth embodiment of the present invention. (A), (b) is a circuit diagram which shows an example of the structure in the output driver circuit examined as a premise of this invention. (A), (b) is a circuit diagram which shows an example of another structure in the output driver circuit examined as a premise of this invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), but a non-oxide film is not excluded as a gate insulating film. Absent. In the drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding a circle symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of an optical communication system to which the output driver circuit according to Embodiment 1 of the present invention is applied. The optical communication system shown in FIG. 1 includes an optical / electrical conversion block OFE_BLK, a serial / parallel conversion block (SerDes: SERializer / DESerializer) SD_BLK, and an upper layer logical block PU. OFE_BLK is, for example, an optical / electrical conversion circuit OEC that converts an optical input data signal IN_OP into an electrical signal via a photodiode or the like, and an electrical / optical conversion that converts an electrical signal into an optical output data signal OUT_OP via a laser diode or the like. A circuit EOC is provided.

  SD_BLK, as an input system circuit, reproduces a data output signal DO and a clock signal CLKo from an input circuit IF_I that amplifies a minute data signal from the OEC into a data signal of a predetermined voltage level, and a data input signal DI that is an output thereof. A signal reproduction circuit CDR and a serial / parallel conversion circuit SPC for converting DO as serial data into a parallel data signal DATo using CLKo are provided. The upper layer logical block PU receives the CLKo and DATAo and performs predetermined information processing. The SD_BLK outputs, as an output system circuit, a parallel / serial conversion circuit PSC that converts the parallel data signal DATi from the PU into a serial data signal using the clock signal CLKi from the PU, and a data input signal DIN that is output from the parallel / serial conversion circuit PSC. And an output circuit IF_O for driving the electrical / optical conversion circuit EOC by the data output signal DOUT.

  In such an optical communication system, high-speed communication exceeding several tens of Gbps is performed in recent years, and accordingly, transmission waveform quality is lowered, and it is becoming increasingly difficult to expand the so-called eye of the eye pattern. There is also an increasing demand for system power saving. In such a situation, it is beneficial to apply an output driver circuit according to the present embodiment to be described later to an output circuit IF_O, for example.

  FIG. 2A is a schematic diagram showing an example of the configuration of the output driver circuit according to Embodiment 1 of the present invention, and FIG. 2B is an example of the power supply voltage relationship of FIG. It is explanatory drawing shown. The output driver circuit TX_BK1 shown in FIG. 2 includes a voltage signal generation circuit block VSG_BK, current signal generation circuit blocks ISG_BKp1 and ISG_BKn1, pulse signal generation circuits PGEN1 and PGEN2, a positive output node TXP, and a negative output node TXN. .

  VSG_BK includes resistors Rp1, Rp2, Rn1, and Rn2, and switch circuits SWp1, SWp2, SWn1, and SWn2. Rp1, Rp2, Rn1, and Rn2 each have an impedance Z0. One end of Rp1 and Rp2 is applied with the high potential output power supply voltage VOH, and one end of Rn1 and Rn2 is provided with the low potential output power supply voltage VOL. Applied. The other ends of Rp1, Rp2, Rn1, and Rn2 are connected to one ends of SWp1, SWp2, SWn1, and SWn2, respectively. The other ends of SWp1 and SWn2 are connected to TXP, and the other ends of SWp2 and SWn1 are connected to TXN. SWp1 and SWn1 are turned on when the positive data input signal DIN_P is at the “H” level (negative data input signal DIN_N is at the “L” level), and SWp2 and SWn2 are at the negative data input signal DIN_N at the “H” level. It is controlled to be on when the positive data input signal DIN_P is at the “L” level.

  PGEN1 receives DIN_P and / or DIN_N, and a pulse signal having a predetermined pulse width when DIN_P transitions from 'L' level to 'H' level (DIN_N changes from 'H' level to 'L' level) Is generated. PGEN2 receives DIN_P and / or DIN_N, and in contrast to PGEN1, when DIN_N transitions from 'L' level to 'H' level (DIN_P changes from 'H' level to 'L' level), a predetermined pulse width is set. The prepared pulse signal is generated.

  The ISG_BKp1 includes a constant current source IS1 having one end connected to the power supply voltage VDD, and switch circuits SWp3 and SWp4 having one end commonly connected to the other end of IS1. The other end of SWp3 is connected to TXP, and the other end of SWp4 is connected to TXN. Similarly, ISG_BKn1 includes a constant current source IS2 having one end connected to the ground power supply voltage GND, and switch circuits SWn3 and SWn4 having one end connected in common to the other end of IS2. The other end of SWn3 is connected to TXN, and the other end of SWn4 is connected to TXP. IS1 and IS2 are set to the same current value. SWp3 and SWn3 are driven on while the pulse signal from PGEN1 is active, and SWp4 and SWn4 are driven on while the pulse signal from PGEN2 is active.

  Here, an external load resistor Rld having an impedance (2 × Z0) is connected between TXP and TXN. When DIN_P transitions from 'L' level to 'H' level to drive this Rld, VOH and TXP are connected via SWp1, and VOL and TXN are connected via SWn1. Conversely, when DIN_P transitions from the “H” level to the “L” level, VOH and TXN are connected via SWp2, and VOL and TXP are connected via SWn2. In each of these states, impedance matching is performed. However, relatively large capacitors Cp1 and Cp2 are added to TXP and TXN along with pad electrodes, ESD (Electro Static Discharge) elements, and the like. Therefore, the rising and falling speeds of TXP and TXN are slow, and the communication speed cannot be increased.

  Therefore, in response to the transition of DIN_P from the ‘L’ level to the ‘H’ level, PGEN1 outputs a pulse signal and drives SWp3 and SWn3 to ON during the pulse width. Then, the charging current from IS1 is supplied to TXP, and the discharging current from IS2 is supplied to TXN. Therefore, Cp1 can be charged and Cp2 can be discharged at high speed. On the other hand, in response to the transition of DIN_P from the “H” level to the “L” level, PGEN2 outputs a pulse signal and drives SWp4 and SWn4 to ON during the pulse width. Then, since the charging current from IS1 is supplied to TXN and the discharging current from IS2 is supplied to TXP, it becomes possible to discharge Cp1 and charge Cp2 at high speed.

  In this way, for example, the following effects can be obtained by using the output driver circuit of FIG. First, the communication speed can be increased. That is, since the current signal generation circuit blocks ISG_BKp1 and ISG_BKn1 can charge and discharge Cp1 and Cp2 at a high speed during data transition, the influence of the capacitance can be reduced, and the rising and falling speeds of TXP and TXN can be improved. it can. Second, transmission waveform quality can be improved. That is, since the constant current sources IS1 and IS2 usually have high impedance, the influence on the impedance matching state associated with the voltage signal generation circuit block VSG_BK described above is small, and waveform reflection hardly occurs. Furthermore, by appropriately adjusting the current values of IS1 and IS2 and the pulse width of the pulse signal from PGEN1, it is possible to perform appropriate pre-emphasis (waveform equalization) according to the communication system. Transmission waveform quality is improved.

  Third, power consumption can be reduced. That is, for example, in the configuration as shown in FIG. 16 described above, there is a concern about an increase in power consumption due to pre-emphasis, but in the configuration example in FIG. 2, an increase in power consumption can be achieved by appropriately adjusting the pre-emphasis amount. Can be suppressed. For example, in the pre-emphasis, by setting the pulse width of the pulse signal from PGEN 1 and PGEN 2 to a value smaller than one cycle of the data rate, compared to the case where pre-emphasis is performed in the entire period of one cycle, Excessive pre-emphasis can be avoided and power consumption can be suppressed. However, conversely, when a large amount of pre-emphasis is required depending on the communication system, it is of course possible to set the pulse width to a value larger than one cycle.

  Fourth, it is possible to achieve a reduction in power consumption and improvement in transmission waveform quality in a balanced manner while maintaining the above-described increase in communication speed. That is, when the pulse signals from PGEN1 and PGEN2 are inactive (in other words, when the data output signals from TXP and TXN are in a steady state), the external load resistor Rld is voltage-driven by VSG_BK. become. At this time, in order to reduce the power consumption, it is desirable to reduce the amplitude of the data output signal in the steady state. However, if the amplitude is reduced too much, the transmission waveform quality is deteriorated (that is, the eye of the eye pattern is reduced). to shrink. In other words, since there is an optimum amplitude according to the applied communication system in view of the balance between power consumption and transmission waveform quality, it is desirable that the output driver circuit be configured so that this amplitude can be selected in a wide range.

  Under these circumstances, the side of reducing the amplitude of the data output signal can be easily realized by lowering VOH and increasing VOL, but the side of increasing the amplitude needs to be studied. For example, if the constant current sources IS1 and IS2 are realized by the saturation region operation of the MOS transistor, the threshold voltage is set to Vth, and IS1 can raise the voltages TXP and TXN only to VDD-Vth. The voltages of TXP and TXN can be lowered only to Vth. Therefore, an amplitude larger than this is generated by voltage driving with VSG_BK. That is, as shown in FIG. 2B, the loss of Vth is covered by increasing VOH and decreasing VOL in VSG_BK. In this case, there is a concern that the rising / falling speed is lowered due to the voltage driving of VSG_BK. However, in reality, the driving is driven by ISG_BKp1 and ISG_BKn1 during most of the rising / falling periods, so the speed reduction is a problem. It will not be. Therefore, by using the configuration example of FIG. 2, the amplitude of the data output signal can be selected in a wide range according to the applied communication system.

  FIG. 3 is a circuit diagram showing a detailed configuration example of the output driver circuit of FIG. The output driver circuit TX_BK1a shown in FIG. 3 includes a voltage signal generation circuit block VSG_BK, pulse signal generation circuits PGEN1a and PGEN2a, current signal generation circuit blocks ISG_BK1 and ISG_BK2, power supply generation circuits VGEN_H and VGEN_L, and a plurality of inverter circuits IV3. To IV6.

  VSG_BK is configured by a plurality (three in this case) of slice circuits SLC1 to SLC3. Each of the slice circuits SLC1 to SLC3 includes a CMOS inverter circuit [1] composed of a PMOS transistor MPz1 and an NMOS transistor MNz2, and a CMOS inverter circuit [2] composed of a PMOS transistor MPz2 and an NMOS transistor MNz1. The CMOS inverter circuit [1] receives a negative data input signal DIN_N via IV3 and IV4, and the CMOS inverter circuit [2] receives a positive data input signal DIN_P via IV5 and IV6. MPz1, MPz2, MNz1, and MNz2 correspond to Rp1 and SWp1, Rp2 and SWp2, Rn1 and SWn1, Rn2 and SWn2, respectively, in FIG. Then, as described with reference to FIG. 16A, by setting the validity / invalidity of each of the slice circuits SLC1 to SLC3, the impedances on the PMOS transistor side and the NMOS transistor side can be set to Z0.

  VGEN_H is a power supply regulator circuit including an amplifier circuit AMPh, a PMOS transistor MPh, and a capacitor Cr1, and generates a high potential side output power supply voltage VOH. In AMPh, a set voltage VOHref (for example, 0.7 V) is input to the negative input node, an output node is connected to the gate of MPh, and a positive input node is connected to the drain of MPh. The source of MPh is connected to the power supply voltage, and Cr1 is connected between the source and drain of MPh. When such a configuration is used, VOH having a value set by VOHref is output from the drain of MPh, and supplied to VSG_BK and IV3 to IV6.

  VGEN_L is a power supply regulator circuit including an amplifier circuit AMP1, an NMOS transistor MN1, and a capacitor Cr2, and generates a low potential side output power supply voltage VOL. In AMP1, a set voltage VOLref (for example, 0.3V) is input to the negative input node, an output node is connected to the gate of MN1, and a positive input node is connected to the drain of MN1. The source of MNl is connected to the ground power supply voltage, and Cr2 is connected between the source and drain of MNl. When such a configuration is used, a VOL having a value set by VOLref is output from the drain of MNl and supplied to VSG_BK and IV3 to IV6.

  PGEN1a includes a variable delay circuit VDLY1, an inverter circuit IV1, an OR operation circuit OR1, and an AND operation circuit AD1. VDLY1 receives DIN_N (or DIN_P) and delays it for a predetermined time. IV1 inverts and outputs the delayed signal. OR1 receives an output signal of DIN_N and IV1 and performs an OR operation. AD1 receives the DIN_N and IV1 output signals and performs an AND operation. On the other hand, PGEN2a includes a variable delay circuit VDLY2, an inverter circuit IV2, an OR operation circuit OR2, and an AND operation circuit AD2. VDLY2 receives DIN_P (or DIN_N) and delays it for a predetermined time. IV2 inverts and outputs the delayed signal. OR2 receives the output signals of DIN_P and IV2 and performs an OR operation. AD2 receives the output signals of DIN_P and IV2, and performs an AND operation.

  The ISG_BK1 includes a PMOS transistor MPi3 and an NMOS transistor MNi4. MPi3 has a source connected to power supply voltage VDD, a drain connected to TXP, and a gate controlled by the output of OR1. In MNi4, the source is connected to the ground power supply voltage GND, the drain is connected to TXP, and the gate is controlled by the output of AD1. MPi3 corresponds to IS1 and SWp3 in FIG. 2, and MNi4 corresponds to IS2 and SWn4 in FIG.

  The ISG_BK2 includes a PMOS transistor MPi4 and an NMOS transistor MNi3. In MPi4, the source is connected to VDD, the drain is connected to TXN, and the gate is controlled by the output of OR2. MNi3 has a source connected to GND, a drain connected to TXN, and a gate controlled by the output of AD2. MPi4 corresponds to IS1 and SWp4 in FIG. 2, and MNi3 corresponds to IS2 and SWn3 in FIG.

  4A is a circuit diagram showing a detailed configuration example of the variable delay circuit VDLY in the pulse signal generation circuit PGEN of FIG. 3, and FIG. 4B is a detail of the inverting selector circuit in FIG. 4A. It is a circuit diagram which shows a structural example. The variable delay circuit VDLY shown in FIG. 4A includes a delay inverter circuit IV [0], a two-input inverting selector circuit IVSEL0, and n delay inverter circuits IV [1 connected in series to the output thereof. ] To IV [n], (n-1) two-input inverting selector circuits IVSEL [0] to IVSEL [n-2], and an inverter circuit IV10. The IVSEL0 selects and outputs the input signal IN or a signal obtained by delaying the inverted input signal (/ IN) by IV [0] based on the delay amount selection signal Sdsel.

  One input of IVSEL [n-2] is an output of IV [n-2], and the other input is an output of IV [n]. One input of IVSEL [n-3] is an output of IV [n-3], and the other input is an output of IVSEL [n-2]. In IVSEL [n-4], one input is an output of IV [n-4] (not shown, but preceding stage of IVSEL [n-3]), and the other input is an output of IVSEL [n-3]. It has become. That is, IVSEL [n-3] to IVSEL [1] have the same connection relationship. In IVSEL [m], one input is an output of IV [m] and the other input is IVSEL [m + 1]. Output. One input of IVSEL [0] is an output of IVSEL0, and the other input is an output of IVSEL [1]. The output of IVSEL [0] becomes an output signal OUT through IV10. Each selection path of IVSEL [0] to IVSEL [n-2] is controlled by a delay amount selection signal Sdsel.

  Each of the inverting selector circuits IVSEL0 and IVSEL [m] includes two CMOS switch circuits CSW each having one input connected to each of the two inputs and the other connected in common, as shown in FIG. 4B. The inverter circuit IV11 for inverting and outputting the signal of the common connection node is provided. The two CSWs are complementarily controlled on and off based on the delay amount selection signal Sdsel [m] and its inverted signal.

  In such a configuration, assuming that the delay amount of each IVSEL [m] is equal to the delay amount (Tdly) of the delay inverter circuit IV [m], first, the delay amount at the time of setting the minimum delay is set as follows. , IVSEL [0], and IV10. Subsequently, the second smallest delay amount is when / IN is output via IV [0], IVSEL0, IVSEL [0], and IV10, and Tdly is smaller than the delay amount when the minimum delay is set. Will join. Next, the third smallest delay amount is when IN is output via IVSEL0, IV [1], IVSEL [1], IVSEL [0], and IV10, and Tdly is equal to the second delay amount. Will join. Similarly, the delay amount can be controlled in the Tdly step thereafter. Thereby, the pulse widths of the pulse signal generation circuits PGEN1a and PGEN2a can be set with high resolution.

  FIG. 5 is a waveform diagram showing an example of the operation of the output driver circuit TX_BK1a of FIG. For example, as shown in cycle S501 of FIG. 5, when DIN_P transitions from 'L' level to 'H' level (DIN_N changes from 'H' level to 'L' level), delay and inversion of VDLY2 with respect to DIN_P A signal obtained by adding the delay and inversion of VDLY1 to DIN_N is output from IV1. As a result, an 'L' pulse signal having a pulse width based on the delay amount of VDLY1 is applied to the gate of MPi3, and an 'H' pulse signal having a pulse width based on the delay amount of VDLY2 is applied to the gate of MNi3. The Then, a current from TXP to TXN flows through MPi3 and MNi3 during this pulse width period.

  Also, as shown in cycle S502 of FIG. 5, when DIN_P transitions from 'H' level to 'L' level (DIN_N changes from 'L' level to 'H' level), delay and inversion of VDLY2 with respect to DIN_P A signal obtained by adding the delay and inversion of VDLY1 to DIN_N is output from IV1. As a result, an 'H' pulse signal having a pulse width based on the delay amount of VDLY1 is applied to the gate of MNi4, and an 'L' pulse signal having a pulse width based on the delay amount of VDLY2 is applied to the gate of MPi4. The Then, a current from TXN to TXP flows through MPi4 and MNi4 during this pulse width period.

  On the other hand, as shown in cycles S503a and S503b of FIG. 5, when DIN_P is at the “H” level (DIN_N is at the “L” level) or DIN_P is at the “L” level (DIN_N is at the “H” level). MPi3, MNi4, MPi4, and MNi3 remain off, and TXP and TXN are driven by VSG_BK. Here, when an external load resistor Rld having an impedance of 2 × Z0 is connected between TXP and TXN, since the PMOS transistor side and the NMOS transistor side have impedance Z0 in VSG_BK, respectively, (VOH A voltage amplitude of -VOL) / 2 is generated.

  As described above, when the output driver circuit TX_BK1a of FIG. 3 is used, for example, the following effects can be obtained in addition to the various effects described in FIG. First, in the current signal generation circuit blocks ISG_BK1 and ISG_BK2 in FIG. 3, the constant current source and the switch circuit (for example, IS1 and SWp3) in the current signal generation circuit blocks ISG_BKp1 and ISG_BKn1 in FIG. 2 are replaced with one MOS transistor (for example, IS1 and SWp3). Since this is realized by MPi3), the communication speed can be further increased. That is, for example, when the constant current source and the switch circuit are realized by vertically stacked two-stage MOS transistors, the rise and fall speeds may be hindered due to the delay components (capacitance and on-resistance) of the MOS transistors. However, if it is realized with a single-stage MOS transistor, a sufficiently high speed can be achieved.

  Second, by supplying VOH and VOL with the power generation circuits VGEN_H and VGEN_L serving as power supply regulator circuits, a sufficient current can be supplied to the external load resistor Rld and sufficient impedance matching can be achieved. That is, for example, if the impedance (resistance value) of Rld is 100Ω and an attempt is made to obtain a voltage amplitude of 0.4 V between TXP and TXN, a current of 4 mA is required. On the other hand, in order to perform high-precision impedance matching in the voltage signal generation circuit block VSG_BK, it is desirable that the line impedances of VOH and VOL be as close to zero as possible. Therefore, if a power supply regulator circuit is used, a relatively large current can be supplied with a low output impedance, so that such a requirement can be satisfied.

  As described above, by using the output driver circuit of the first embodiment, typically, in addition to increasing the communication speed, power consumption can be reduced. In addition to increasing the communication speed, transmission waveform quality can be improved.

(Embodiment 2)
In the second embodiment, a modification of the output driver circuit TX_BK1a of FIG. 3 described in the first embodiment will be described. FIG. 6 is a circuit diagram showing an example of the configuration of the output driver circuit according to the second embodiment of the present invention. The output driver circuit TX_BK1b illustrated in FIG. 6 has a configuration in which the pulse signal generation circuits PGEN1a and PGEN2a illustrated in FIG. 3 are replaced with the pulse signal generation circuits PGEN1b and PGEN2b illustrated in FIG. 6 as compared with the TX_BK1a illustrated in FIG. Further, in FIG. 6, unlike FIG. 3, the voltage signal generation circuit block VSG_BK is configured by one slice circuit. Since the configuration other than these is the same as that of FIG. 3, detailed description thereof is omitted.

  Here, VSG_BK is composed of one slice circuit, so that the impedance adjustment is different from the case of FIG. 3 and controls the voltage values of the high potential side output power supply voltage VOH and the low potential side output power supply voltage VOL. To do. In this case, the circuit area can be reduced as compared with the case of FIG. However, on the other hand, the values of VOH and VOL cannot be freely set. Therefore, when it is desired to individually set the impedance and the values of VOH and VOL, it is necessary to provide a plurality of slice circuits as shown in FIG.

  PGEN1b includes variable delay circuits VDLY1a and VDLY1b, inverter circuits IV1a and IV1b, an OR operation circuit OR1, and an AND operation circuit AD1. VDLY1a and VDLY1b receive DIN_N (or DIN_P) and delay it by a predetermined time. IV1a inverts and outputs the signal delayed by VDLY1a. IV1b inverts and outputs the signal delayed by VDLY1b. OR1 receives an output signal from DIN_N and IV1a and performs an OR operation. AD1 receives the output signals of DIN_N and IV1b and performs an AND operation. In the current signal generation circuit block ISG_BK1, the PMOS transistor MPi3 is driven by the output of OR1, and the NMOS transistor MNi4 is driven by the output of AD1.

  PGEN2b includes variable delay circuits VDLY2a and VDLY2b, inverter circuits IV2a and IV2b, an OR operation circuit OR2, and an AND operation circuit AD2. VDLY2a and VDLY2b receive DIN_P (or DIN_N) and delay it by a predetermined time. IV2a inverts and outputs the signal delayed by VDLY2a. IV2b inverts and outputs the signal delayed by VDLY2b. OR2 receives an output signal from DIN_P and IV2a and performs an OR operation. AD2 receives the output signals of DIN_P and IV2b and performs an AND operation. In the current signal generation circuit block ISG_BK2, the PMOS transistor MPi4 is driven by the output of OR2, and the NMOS transistor MNi3 is driven by the output of AD2.

  FIG. 7 is a waveform diagram showing an example of the operation of the output driver circuit TX_BK1b of FIG. For example, as shown in cycle S701 of FIG. 7, when DIN_P transitions from 'L' level to 'H' level (DIN_N changes from 'H' level to 'L' level), the gate of MPi3 increases the pulse width of VDLY1a. The gate of MNi3 is driven by an 'H' pulse signal having a pulse width of VDLY2b. Therefore, a current from TXP to TXN flows through MPi3 and MNi3 during this pulse width period.

  Also, as shown in cycle S702 of FIG. 7, when DIN_P transitions from 'H' level to 'L' level (DIN_N changes from 'L' level to 'H' level), the gate of MPi4 increases the pulse width of VDLY2a. The gate of MNi4 is driven by the 'H' pulse signal having the pulse width of VDLY1b. Therefore, a current from TXN to TXP flows through MPi4 and MNi4 during this pulse width period.

  If such a configuration example is used, the on-pulse widths of MPi3, MNi3, MPi4, and MNi4 can be individually set, so that it is possible to suppress a decrease in waveform quality due to manufacturing variations and the like. That is, if transistor size variation or the like occurs relatively among MPi3, MNi3, MPi4, and MNi4, the charge current and the discharge current may be imbalanced, and transmission waveform quality may be degraded. In the configuration example of FIG. 3, since the pulse width is set in units of two of MPi3, MNi3, MPi4, and MNi4, it is difficult to adjust all of these relative variations. In the configuration example, since the pulse width can be individually set, it is possible to adjust all relative variations.

  As described above, by using the output driver circuit of the second embodiment, typically, as in the case of the first embodiment, in addition to increasing the communication speed, the power consumption can be reduced. In addition to increasing the communication speed, transmission waveform quality can be improved. Further, the transmission waveform quality can be further improved as compared with the first embodiment.

(Embodiment 3)
The output driver circuits of the first and second embodiments described above are driven by the current signal when the data signal transitions, and are driven by the voltage signal when the data signal is steady. In the third embodiment, A method of driving with a current signal even when the data signal is steady will be described. FIG. 8A is a circuit diagram showing an example of the configuration of the output driver circuit according to Embodiment 3 of the present invention, and FIG. 8B is an example of the power supply voltage relationship of FIG. 8A. It is explanatory drawing shown. FIG. 9 is a waveform diagram showing an example of the operation of the output driver circuit of FIG.

  The output driver circuit TX_BK2 illustrated in FIG. 8 includes a voltage signal generation circuit block VSG_BK, current signal generation circuit blocks ISG_BKp2 and ISG_BKn2, and a positive output node TXP and a negative output node TXN. That is, TX_BK2 in FIG. 8 is different from the output driver circuit TX_BK1 in FIG. 2 in that the pulse signal generation circuits PGEN1 and PGEN2 in FIG. 2 are deleted, and the current signal generation circuit blocks ISG_BKp1 and ISG_BKn1 in FIG. , ISG_BKn2 is replaced. Similarly to the case of FIG. 2, VSG_BK includes resistors Rp1, Rp2, Rn1, and Rn2 each having an impedance Z0, and switch circuits SWp1, SWp2, SWn1, and SWn2, and a high-potential-side output power supply voltage at one end of Rp1 and Rp2. VOH is supplied, and the low-potential-side output power supply voltage VOL is supplied to one end of Rn1 and Rn2.

  The ISG_BKp2 includes a constant current source IS10 having one end connected to the power supply voltage VDD, and switch circuits SWp5 and SWp6 having one end commonly connected to the other end of the IS10. The other end of SWp5 is connected to TXP, and the other end of SWp6 is connected to TXN. Similarly, the ISG_BKn2 includes a constant current source IS20 having one end connected to the ground power supply voltage GND, and switch circuits SWn5 and SWn6 having one end commonly connected to the other end of the IS20. The other end of SWn5 is connected to TXN, and the other end of SWn6 is connected to TXP. IS10 and IS20 are set to the same current value I0. SWp5 and SWn5 are driven to ON when the positive data input signal DIN_P is at the “H” level (the negative data input signal DIN_N is at the “L” level), and SWp6 and SWn6 are DIN_P at the “L” level (DIN_N is “L”). H 'level).

  Here, the current value I0 of IS10 and IS20 is set to (VOH−VOL) / (2 × Z0). Then, when an external load resistor Rld having an impedance of 2 × Z0 is connected between TXP and TXN, it is possible to obtain a voltage amplitude of (VOH−VOL) between TXP and TXN as shown in FIG. Become. For example, when voltage driving by VSG_BK is used in a steady state, the voltage amplitude between TXP and TXN becomes (VOH−VOL) / 2 as described with reference to FIG. In this case, in order to increase the voltage amplitude and improve the transmission waveform quality (enlarge the eye of the eye pattern), it is necessary to increase the VOH and decrease the VOL. As a result, a high VOH is required. This means that a higher power supply voltage is required to generate.

  Therefore, when the configuration example as shown in FIG. 8A is used, the IS10 and IS20 perform current driving at the time of data transition and also generate a steady voltage level, so that the rising and falling speeds are maintained at high speed. However, the voltage amplitude with respect to the external load resistor Rld can be increased without using a high power supply voltage. When the voltage amplitude between TXP and TXN becomes (VOH-VOL), current is not input / output by VOH and VOL of VSG_BK, and VSG_BK functions only as an impedance matching circuit.

  Note that the voltage relationship between VDD and VOH, and GND and VOL, as shown in FIG. 8 (b), when IS10 and IS20 are realized by the saturation region operation of a MOS transistor, (VDD−VOH) ≧ ((2 × I0) / gm) and (VOL-GND) ≧ ((2 × I0) / gm). Here, gm is the mutual inductance of the MOS transistor. Therefore, in practice, there is an upper limit in the range of expansion of the voltage amplitude with respect to Rld even when current driving is used in a steady state, but it can be sufficiently expanded as compared with the case where voltage driving as described above is used. Become.

  Thus, for example, the following effects can be obtained by using the output driver circuit of FIG. First, the communication speed can be increased. That is, at the time of data transition, the current signal generation circuit blocks ISG_BKp2 and ISG_BKn2 can charge and discharge the capacitors Cp1 and Cp2 parasitic on the TXP and TXN at high speed, so that the influence of the capacitance can be reduced. The falling speed can be improved. Second, transmission waveform quality can be improved. That is, since the constant current sources IS10 and IS20 usually have high impedance, the voltage signal generation circuit block VSG_BK can be mainly impedance-matched and waveform reflection can be suppressed.

  Third, it is possible to achieve a reduction in power consumption and improvement in transmission waveform quality in a well-balanced manner while maintaining the above-described increase in communication speed. That is, as described in FIG. 2, there is an optimum amplitude of the data output signal in the steady state according to the applied communication system in consideration of the reduction in power consumption and the transmission waveform quality. At this time, the side of increasing the amplitude becomes a problem. As in the configuration example of FIG. 2, when the amplitude at the steady state is generated by the voltage signal generation circuit block VSG_BK, the amplitude cannot be increased unless the power supply voltage is increased as described above, but the configuration of FIG. If an example is used, the amplitude can be expanded with a lower power supply voltage.

  FIG. 10 is a circuit diagram showing a detailed configuration example of the output driver circuit of FIG. The output driver circuit TX_BK2a illustrated in FIG. 10 includes a voltage signal generation circuit block VSG_BK, current signal generation circuit blocks ISG_BK3 and ISG_BK4, power supply generation circuits VGEN_H and VGEN_L, and a plurality of inverter circuits IV3 to IV6. That is, TX_BK2a in FIG. 10 has the pulse signal generation circuits PGEN1a and PGEN2a deleted compared to the output driver circuit TX_BK1a in FIG. 3, and the current signal generation circuit blocks ISG_BK1 and ISG_BK2 in FIG. It has been replaced. Since the configuration other than this is the same as that in FIG.

  The ISG_BK3 includes PMOS transistors MPi5 and MPs5 and NMOS transistors MNs6 and MNi6. MPi5 has a source connected to power supply voltage VDD, a drain connected to the source of MPs5, and a reference voltage VBp applied to the gate. MPs5 has a drain connected to TXP and a negative data input signal DIN_N applied to the gate. In MNi6, the source is connected to the ground power supply voltage GND, the drain is connected to the source of MNs6, and the reference voltage VBn is applied to the gate. The drain of MNs6 is connected to TXP, and DIN_N is applied to the gate. MPi5, MPs5, MNs6, and MNi6 in FIG. 10 correspond to IS10, SWp5, SWn6, and IS20 in FIG. 8, respectively.

  The ISG_BK4 includes PMOS transistors MPi6 and MPs6 and NMOS transistors MNs5 and MNi5. In MPi6, the source is connected to VDD, the drain is connected to the source of MPs6, and VBp is applied to the gate. In MPs6, the drain is connected to TXN, and the positive data input signal DIN_P is applied to the gate. In MNi5, the source is connected to GND, the drain is connected to the source of MNs5, and VBn is applied to the gate. MNs5 has a drain connected to TXN and a gate to which DIN_P is applied. MPi6, MPs6, MNs5, and MNi5 in FIG. 10 correspond to IS10, SWp6, SWn5, and IS20 in FIG. 8, respectively.

  Using such a configuration example, when DIN_N is at the “L” level (DIN_P is at the “H” level), MPs5 and MNs5 are turned on, TXP is charged by the current determined by MPi5, and the current determined by MNi5 TXN is discharged. When DIN_P is at the ‘L’ level (DIN_N is at the ‘H’ level), MPs6 and MNs6 are turned on, TXN is charged by the current determined by MPi6, and TXP is discharged by the current determined by MNi6.

  FIGS. 11A and 11B are circuit diagrams showing a configuration example of a circuit for generating the reference voltages VBn and VBp in the output driver circuit TX_BK2a of FIG. The reference voltage generation circuit VBNGEN illustrated in FIG. 11A includes an amplifier circuit AMPn, an NMOS transistor MNb1, and a dummy resistor Rdm. In AMPn, the low potential side output power supply voltage VOL is applied to the negative input node, the output node is connected to the gate of MNb1, and the positive input node is connected to the drain of MNb1. The source of MNb1 is connected to GND. One end of Rdm is connected to the drain of MNb1, and the other end is applied with the high potential side output power supply voltage VOH. Here, MNb1 is current mirror connected (that is, the gate is commonly connected) to MNi6 and MNi5 in the above-described ISG_BK3 and ISG_BK4, and this common gate voltage becomes VBn.

  In FIG. 11A, Rdm is set to n times (2 × Z0) where the resistance value is the impedance of the external load resistance. Further, the transistor size of MNi6 and MNi5 described above is WN, and the transistor size of MNb1 is set to 1 / n times WN. Then, a current of (VOH−VOL) / (n × 2 × Z0) flows through Rdm, and this current is supplied to MNb1. As a result of current mirror connection, MNi6 and MNi5 have an n-fold current. Flowing. As a result, MNi6 and MNi5 are current sources having a current value I0 of (VOH−VOL) / (2 × Z0). Note that by setting Rdm to n times (2 × Z0), the magnitude of the through current flowing from the VOH can be suppressed, and the power consumption can be reduced.

  On the other hand, the reference voltage VBp is generated by one of the two reference voltage generation circuits VBPGEN1 and VBPGEN2 shown in FIG. VBPGEN1 includes a PMOS transistor MPb2 and an NMOS transistor MNb2. MPb2 has a source connected to VDD and a gate and a drain connected in common. The source of MNb2 is connected to GND, the drain is connected to the drain (gate) of MPb2, and VBn generated in FIG. 11A is applied to the gate. Here, MPb2 is connected to MPi5 and MPi6 in the aforementioned ISG_BK3 and ISG_BK4 in a current mirror connection (that is, the gate is commonly connected), and this common gate voltage becomes VBp.

  In such a configuration example, the transistor size of MNb2 is set to WN / n, for example, similarly to MNb1. Also, the transistor size of MPb2 is set to 1 / n times WP, where MPi5 and MPi6 have the transistor size WP. Then, a current of (VOH−VOL) / (n × 2 × Z0) flows to MNb2 similarly to MNb1, and this current is supplied to MPb2, and MPi5 and MPi6 have their n Double current flows. As a result, MPi5 and MPi6 become current sources having a current value I0 of (VOH−VOL) / (2 × Z0).

  Further, the reference voltage generation circuit VBPGEN2 shown in FIG. 11B includes an amplifier circuit AMPp, a PMOS transistor MPb1, and a dummy resistor Rdm. In AMPp, the high potential side output power supply voltage VOH is applied to the negative input node, the output node is connected to the gate of MPb1, and the positive input node is connected to the drain of MPb1. The source of MPb1 is connected to VDD. One end of Rdm is connected to the drain of MPb1, and the other end of the low potential side output power supply voltage VOL is applied. Here, MPb1 is current mirror connected (that is, the gate is commonly connected) to MPi5 and MPi6 in the above-described ISG_BK3 and ISG_BK4, and this common gate voltage becomes VBp. When such a configuration example is used, MPi5 and MPi6 become current sources having a current value I0 of (VOH−VOL) / (2 × Z0) based on the same principle as VBNGEN described in FIG. .

  FIG. 12A is a circuit diagram showing a modification of the power generation circuit in the output driver circuit TX_BK2a of FIG. 10, and FIG. 12B is a circuit diagram showing a comparative example thereof. In TX_BK2a of FIG. 10 described above, for example, as shown in FIG. 12B, a power supply regulator circuit VREG_H including an amplifier circuit AMPh is used as the power supply generation circuit VGEN_H. Here, it is desirable that the VOH generated from VGEN_H is designed so that the output impedance does not have frequency dependence in order to achieve impedance matching with the external load resistance (Rld). Therefore, normally, the output impedance is stabilized in the low frequency region by the negative feedback loop by AMPh, and in the high frequency region, the output impedance is stabilized by the capacitor Cr connected between the source and drain of the PMOS transistor MPh. . However, the loop band of AMPh cannot actually be widened because it is necessary to add a phase compensation capacitor Cc to the gate of MPh. As a result, it becomes necessary to increase the capacity value of Cr.

  Therefore, as shown in FIG. 12A, it is beneficial to use a method of supplying VOH and VOL by a source follower circuit. 12A, the power generation circuit VGEN_H2 includes an NMOS transistor MNh whose source is connected to VDD and VOH + Vth applied to the gate, and a capacitor Cr connected between the source and drain of MNh. Then, VOH is output from the source of MNh. In FIG. 12A, the power generation circuit VGEN_L2 includes a PMOS transistor MPl having a source connected to GND and VOL-Vth applied to the gate, and a capacitor Cr connected between the source and drain of MPl. Is done. Then, VOL is output from the source of MPl.

  Since such a source follower circuit has high frequency response, Cr can be reduced. In particular, in the configuration example of FIG. 8 and the like, since a small amount of current flows through VOH and VOL as described above, a sufficient current can be supplied even in the source follower circuit. However, if a source follower circuit is used, there is a concern that the output amplitude cannot be increased with a decrease in the upper limit of VOH and an increase in the lower limit of VOL. However, in the configuration example of FIG. In order to achieve this, the conditions of VOH ≦ VDD−Vth and VOL ≧ Vth are required, so there is no particular problem.

  As described above, by using the output driver circuit of the third embodiment, typically, in addition to increasing the communication speed, power consumption can be reduced. In addition to increasing the communication speed, transmission waveform quality can be improved.

(Embodiment 4)
In the fourth embodiment, a modification of the output driver circuit TX_BK2a of FIG. 10 described in the third embodiment will be described. FIG. 13 is a circuit diagram showing an example of the configuration of the output driver circuit according to the fourth embodiment of the present invention. The output driver circuit TX_BK2b illustrated in FIG. 13 corresponds to the output driver circuit TX_BK2 illustrated in FIG. 13 is replaced with the current signal generation circuit blocks ISG_BK5 and ISG_BK6 of FIG. 13 in comparison with the TX_BK2a of FIG. 10 described above, and further, the level shift circuits LSp1, LSp2, LSn1, and LSn2 are added. Since the configuration other than these is the same as that of FIG. 10, detailed description thereof is omitted.

  LSp1 receives the positive data input signal DIN_P and performs an inverting operation to output the power supply voltage VDD as the ‘H’ level and the reference voltage VBp as the ‘L’ level. LSp2 receives the negative data input signal DIN_N, performs an inverting operation, and outputs VDD as the ‘H’ level and VBp as the ‘L’ level. LSn1 receives DIN_N, performs an inverting operation, and outputs the reference voltage VBn as the ‘H’ level and the ground power supply voltage GND as the ‘L’ level. LSn2 receives DIN_P, performs an inverting operation, and outputs VBn as the ‘H’ level and GND as the ‘L’ level. These VBp and VBn are generated by a circuit as described in FIG.

  The ISG_BK5 includes a PMOS transistor MPis5 and an NMOS transistor MNis6. In MPis5, the source is connected to VDD, the drain is connected to TXP, and the gate is controlled by the output of LSp1. MNis6 has a source connected to GND, a drain connected to TXP, and a gate controlled by the output of LSn2. MPis5 corresponds to IS10 and SWp5 in FIG. 8, and MNis6 corresponds to IS20 and SWn6 in FIG.

  The ISG_BK6 includes a PMOS transistor MPis6 and an NMOS transistor MNis5. In MPis6, the source is connected to VDD, the drain is connected to TXN, and the gate is controlled by the output of LSp2. MNis5 has a source connected to GND, a drain connected to TXN, and a gate controlled by the output of LSn1. MPis6 corresponds to IS10 and SWp6 in FIG. 8, and MNis5 corresponds to IS20 and SWn5 in FIG.

  In FIG. 13, when DIN_N is at the “L” level (DIN_P is at the “H” level), LSp1 to VBp, LSn1 to VBn are output, LSp2 to VDD, and LSn2 to GND, respectively. As a result, MPis5 and MNis5 become constant current sources having a current value I0, charge TXP, and discharge TXN. On the other hand, when DIN_N is at the “H” level (DIN_P is at the “L” level), LSp2 to VBp, LSn2 to VBn are output, LSp1 to VDD, and LSn1 to GND, respectively. As a result, MPis6 and MNis6 become constant current sources having a current value I0, charge TXN, and discharge TXP.

  If such a configuration example is used, as described with reference to FIG. 3, the charge path and the discharge path in ISG_BK5 and ISG_BK6 can be configured by one-stage MOS transistors, respectively, so that the speed can be increased. However, in this case, it is necessary to sufficiently increase the drive capability of the level shift circuits LSp1, LSp2, LSn1, and LSn2.

  As described above, by using the output driver circuit of the fourth embodiment, typically, as in the case of the third embodiment, in addition to increasing the communication speed, the power consumption can be reduced. In addition to increasing the communication speed, transmission waveform quality can be improved.

(Embodiment 5)
In the fifth embodiment, a configuration example that combines the configuration example of FIG. 2 described in the first embodiment and the configuration example of FIG. 8 described in the third embodiment will be described. FIG. 14 is a schematic diagram showing an example of the configuration of the output driver circuit according to the fifth embodiment of the present invention. The output driver circuit TX_BK3 shown in FIG. 14 includes the voltage signal generation circuit block VSG_BK, the pulse signal generation circuits PGEN1 and PGEN2, and the current signal generation circuit blocks ISG_BKp1 and ISG_BKn1 described in FIG. 2, and the current signal generation described in FIG. The circuit block is provided with circuit blocks ISG_BKp2 and ISG_BKn2.

  In such a configuration, when the positive data input signal DIN_P and the negative data input signal DIN_N transition, a pulse signal is generated from PGEN1 and PGEN2 as described in FIG. Current driving of TXP and TXN is performed by IS1 and IS2. In parallel with this, as described in FIG. 8, current driving of TXP and TXN is performed by IS10 and IS20, and voltage driving of TXP and TXN is performed by VSG_BK. In this data transition period, pre-emphasis is performed mainly by adding current drive by IS1 and IS2 to current drive by IS10 and IS20. During this time, VSG_BK functions as a circuit for impedance matching.

  Thereafter, when the pulse signals from PGEN1 and PGEN2 are deactivated, the data output signals at TXP and TXN shift to a steady period. At this time, as described in FIG. 8, current driving of TXP and TXN is performed by IS10 and IS20, and voltage driving of TXP and TXN is performed by VSG_BK. In this steady period, the output amplitudes at TXP and TXN are set mainly by current driving by IS10 and IS20, and during this time, VSG_BK functions as an impedance matching circuit.

  As described above, by using the output driver circuit of the fifth embodiment, typically, the various effects described in the first embodiment and the various effects described in the third embodiment are synergistically obtained. In addition to further increasing the communication speed, power consumption can be reduced. In addition to further increasing the communication speed, transmission waveform quality can be further improved. In more detail, TX_BK3 shown in FIG. 14 can be realized by appropriately combining various circuits described in FIG. 3, FIG. 6, FIG. 10, FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The output driver circuit according to the present embodiment is particularly useful when applied as a laser diode drive driver in an optical communication system, and is not limited to this, and can be widely applied as a differential output driver for high-speed communication. .

AD AND operation circuit AMP amplifier circuit C capacity CDR signal regeneration circuit CLK clock signal CSW CMOS switch circuit DAMP differential amplifier circuit DAT parallel data signal DI, DIN data input signal DO, DOUT data output signal DV driver circuit EMP pre-emphasis circuit EOC electricity・ Optical conversion circuit GND Ground power supply voltage IF_I Input circuit IF_O Output circuit IN Input signal IN_OP Optical input data signal IS Constant current source ISG_BK Current signal generation circuit block IV Inverter circuit IVSEL Inversion selector circuit LS Level shift circuit MN NMOS transistor MP PMOS transistor OEC Optical / electrical conversion circuit OFE_BLK Optical / electrical conversion block OR OR operation circuit OUT Output signal OUT_OP Optical output data signal GEN Pulse signal generation circuit PSC Parallel / serial conversion circuit PU Upper layer logic block R Resistance SD_BLK Serial / parallel conversion block SLC Slice circuit SPC Serial / parallel conversion circuit SW Switch circuit Sdsel Delay amount selection signal TX_BK Output driver circuit TXN Negative output node TXP Positive output node VB Reference voltage VDD Power supply voltage VDLY Variable delay circuit VGEN Power supply generation circuit VOH, VOL Output power supply voltage VREG Power supply regulator circuit VSG_BK Voltage signal generation circuit block

Claims (15)

A first circuit for controlling conduction / non-conduction between the positive differential output node and the first power supply;
A second circuit for controlling conduction / non-conduction between a negative differential output node and a second power supply having a lower voltage than the first power supply;
A third circuit for controlling conduction / non-conduction between the negative differential output node and the first power source;
A fourth circuit for controlling conduction / non-conduction between the positive differential output node and the second power source;
A first pulse generation circuit that generates a first pulse signal when a differential input node transitions from a first logic level to a second logic level;
A second pulse generation circuit for generating a second pulse signal when the differential input node transitions from the second logic level to the first logic level;
A first current circuit for flowing a charging current to the positive differential output node;
A second current circuit for flowing a discharge current to the negative differential output node;
A third current circuit for flowing a charging current to the negative differential output node;
A fourth current circuit for flowing a discharge current to the positive differential output node;
The first and second circuits are controlled to be in a conductive state and a first impedance when the differential input node is at the second logic level, and are controlled to be in a non-conductive state when the differential input node is at the first logic level;
The third and fourth circuits are controlled to be in a conductive state and the first impedance when the differential input node is at the first logic level, and are controlled to be in a non-conductive state when the differential input node is at the second logic level;
The first and second current circuits pass current during a period of a pulse width of the first pulse signal,
The output driver circuit, wherein the third and fourth current circuits pass current during a period of a pulse width of the second pulse signal. The output driver circuit according to claim 1.
The output driver circuit characterized in that the pulse widths of the first and second pulse signals are smaller than one cycle of the data rate of the data signal output from the positive and negative differential output nodes. The output driver circuit according to claim 2 .
The first current circuit is realized by a first transistor having a one-stage configuration in which a current path is formed between the positive differential output node and a third power source, and the first pulse signal is input to a control input node;
The second current circuit has a one-stage configuration in which a current path is provided between the negative differential output node and a fourth power supply having a lower voltage than the third power supply, and the first pulse signal is input to a control input node. Realized by the second transistor of
The third current circuit is realized by a third transistor having a one-stage configuration in which a current path is formed between the negative differential output node and the third power source, and the second pulse signal is input to a control input node.
The fourth current circuit is realized by a fourth transistor having a one-stage configuration in which a current path is formed between the positive differential output node and the fourth power supply, and the second pulse signal is input to a control input node. An output driver circuit characterized by. The output driver circuit according to claim 2 .
An output driver circuit, wherein a pulse width of the first pulse signal and a pulse width of the second pulse signal are variably controlled according to settings. The output driver circuit according to claim 4 .
The first pulse signal includes third and fourth pulse signals,
The second pulse signal consists of fifth and sixth pulse signals,
The first current circuit allows the charging current to flow in a period of a pulse width of the third pulse signal,
The second current circuit allows the discharge current to flow in a period of a pulse width of the fourth pulse signal,
The third current circuit allows the charging current to flow in a period of a pulse width of the fifth pulse signal,
The fourth current circuit allows the discharge current to flow in a period of a pulse width of the sixth pulse signal,
The pulse width of the third pulse signal is determined by the delay setting amount of the first variable delay circuit,
The pulse width of the fourth pulse signal is determined by the delay setting amount of the second variable delay circuit,
The pulse width of the fifth pulse signal is determined by the delay setting amount of the third variable delay circuit,
The pulse width of the sixth pulse signal is determined by the delay setting amount of the fourth variable delay circuit. The output driver circuit according to claim 2 .
The first power supply is generated by a first power supply regulator circuit capable of setting a voltage value,
The output driver circuit, wherein the second power supply is generated by a second power supply regulator circuit capable of setting a voltage value. A first circuit for controlling conduction / non-conduction between a positive differential output node and a first power supply having a first voltage value;
A second circuit for controlling conduction / non-conduction between a negative differential output node and a second power supply having a second voltage value lower than the first voltage value;
A third circuit for controlling conduction / non-conduction between the negative differential output node and the first power source;
A fourth circuit for controlling conduction / non-conduction between the positive differential output node and the second power source;
A first current circuit for flowing a charging current having a first current value to the positive differential output node;
A second current circuit for causing the discharge current of the first current value to flow through the negative differential output node;
A third current circuit for flowing a charging current of the first current value to the negative differential output node;
A fourth current circuit for flowing a discharge current of the first current value to the positive differential output node;
The first and second circuits are controlled to be conductive and have a first impedance when the differential input node is at the second logic level, and are controlled to be non-conductive when the differential input node is at the first logic level;
The third and fourth circuits are controlled to be in a conductive state and the first impedance when the differential input node is at the first logic level, and are controlled to be in a non-conductive state when the differential input node is at the second logic level;
The first and second current circuits pass current when the differential input node is at the second logic level;
The third and fourth current circuits pass current when the differential input node is at the first logic level,
The output driver circuit, wherein the first current value is (first voltage value−second voltage value) / (2 × first impedance). The output driver circuit according to claim 7 .
The first power source is generated by a first source follower circuit;
The output driver circuit, wherein the second power source is generated by a second source follower circuit. The output driver circuit according to claim 7 .
The first current circuit is realized by first and second transistors in which current paths are connected in series between a third power source and the positive differential output node,
The second current circuit is realized by third and fourth transistors in which current paths are connected in series between a fourth power source having a lower voltage than the third power source and the negative differential output node,
The third current circuit is realized by fifth and sixth transistors in which current paths are connected in series between the third power source and the negative differential output node,
The fourth current circuit is realized by seventh and eighth transistors in which current paths are connected in series between the fourth power source and the positive differential output node,
The second and fourth transistors are controlled to be on when the differential input node is at the second logic level and off when the differential input node is at the first logic level;
The sixth and eighth transistors are controlled to be on when the differential input node is at the first logic level and off when the differential input node is at the second logic level,
Each of the first and fifth transistors receives a first control voltage at a control input node to generate the first current value,
Each of the third and seventh transistors receives the second control voltage at a control input node to generate the first current value. The output driver circuit according to claim 9 .
Either the first control voltage or the second control voltage is generated by a control voltage generation circuit,
The control voltage generation circuit includes:
A dummy resistor having one end connected to one of the first power source or the second power source;
A dummy transistor connected in series to the other end of the dummy resistor, the first and fifth transistors, or a dummy transistor connected to the third and seventh transistors in a current mirror;
An amplifier circuit that fixes the other end of the dummy resistor to the other of the first power supply or the second power supply and controls a control input node of the dummy transistor;
The dummy resistor has a resistance value of (2 × first impedance × N),
The output driver circuit, wherein the dummy transistor has a size 1 / N of the first and fifth transistors or 1 / N of the third and seventh transistors. The output driver circuit according to claim 7 .
The first current circuit is realized by a nine-stage ninth transistor having a current path between the positive differential output node and a fifth power source,
The second current circuit is realized by a tenth transistor having a one-stage configuration having a current path between the negative differential output node and a sixth power supply having a lower voltage than the fifth power supply,
The third current circuit is realized by an eleventh transistor having a one-stage configuration having a current path between the negative differential output node and the fifth power source,
The fourth current circuit is realized by a twelfth transistor having a one-stage configuration having a current path between the positive differential output node and the sixth power source,
The output driver circuit further includes:
A first level shift circuit that outputs a third control voltage corresponding to the first current value to a control input node of the ninth transistor when the differential input node is at the second logic level;
A second level shift circuit that outputs a fourth control voltage corresponding to the first current value to a control input node of the tenth transistor when the differential input node is at the second logic level;
A third level shift circuit that outputs the third control voltage to the control input node of the eleventh transistor when the differential input node is at the first logic level;
An output driver circuit comprising: a fourth level shift circuit that outputs the fourth control voltage to the control input node of the twelfth transistor when the differential input node is at the first logic level. A first circuit for controlling conduction / non-conduction between a positive differential output node and a first power supply having a first voltage value;
A second circuit for controlling conduction / non-conduction between a negative differential output node and a second power supply having a second voltage value lower than the first voltage value;
A third circuit for controlling conduction / non-conduction between the negative differential output node and the first power source;
A fourth circuit for controlling conduction / non-conduction between the positive differential output node and the second power source;
A first pulse generation circuit that generates a first pulse signal when a differential input node transitions from a first logic level to a second logic level;
A second pulse generation circuit for generating a second pulse signal when the differential input node transitions from the second logic level to the first logic level;
First and fifth current circuits for flowing a charging current to the positive differential output node;
Second and sixth current circuits for causing a discharge current to flow through the negative differential output node;
Third and seventh current circuits for flowing a charging current to the negative differential output node;
A fourth and an eighth current circuit for flowing a discharge current to the positive differential output node;
The first and second circuits are controlled to be in a conductive state and a first impedance when the differential input node is at the second logic level, and are controlled to be in a non-conductive state when the differential input node is at the first logic level;
The third and fourth circuits are controlled to be in a conductive state and the first impedance when the differential input node is at the first logic level, and are controlled to be in a non-conductive state when the differential input node is at the second logic level;
The first and second current circuits flow current in a period of a pulse width of the first pulse signal,
The third and fourth current circuits pass current in a period of a pulse width of the second pulse signal,
The fifth and sixth current circuits pass a current having a first current value when the differential input node is at the second logic level,
The seventh and eighth current circuits pass a current having the first current value when the differential input node is at the first logic level,
The output driver circuit, wherein the first current value is (first voltage value−second voltage value) / (2 × first impedance). The output driver circuit according to claim 12 ,
The first current circuit is realized by a first transistor having a one-stage configuration in which a current path is formed between the positive differential output node and a third power source, and the first pulse signal is input to a control input node;
The second current circuit has a one-stage configuration in which a current path is provided between the negative differential output node and a fourth power supply having a lower voltage than the third power supply, and the first pulse signal is input to a control input node. Realized by the second transistor of
The third current circuit is realized by a third transistor having a one-stage configuration in which a current path is formed between the negative differential output node and the third power source, and the second pulse signal is input to a control input node.
The fourth current circuit is realized by a fourth transistor having a one-stage configuration in which a current path is formed between the positive differential output node and the fourth power supply, and the second pulse signal is input to a control input node. An output driver circuit characterized by. The output driver circuit according to claim 13 .
An output driver circuit, wherein a pulse width of the first pulse signal and a pulse width of the second pulse signal are variably controlled according to settings. The output driver circuit according to claim 12 ,
The first power source is generated by a first source follower circuit;
The output driver circuit, wherein the second power source is generated by a second source follower circuit.

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