JP2005217999A - Digital data transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed data transmission circuit with a low voltage and low power operation. <P>SOLUTION: Two bridge type differential switching circuits are used as a base of a driver circuit, and one is used as a main driver and the other is used as a driver for preemphasis. The driver circuits sharing a differential output terminal, a transmission line and a terminating resistance matched to characteristic impedance of the transmission line constitute a data transmission circuit that has impedance matching to the transmission line and a preemphasis function. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a transmission circuit for serially transmitting digital data at high speed, and more particularly to an output driver having a pre-emphasis function for correcting high-frequency signal amplitude deterioration in a transmission line and a digital data transmission circuit including the output driver.

  In recent years, data transmission in a storage for storing data, a server, or a router for controlling the destination of data transmission requires a transmission rate of several gigabits per second (hereinafter abbreviated as several Gbps). Signal attenuation on the line becomes significant, and data cannot be restored on the receiving side.

  FIG. 10 is an example of a conventional output driver with a pre-emphasis function that attempts to solve this problem (see, for example, Non-Patent Document 1). It consists of a main driver 100 and a pre-emphasis driver 106, the outputs of which are connected at DoP and DoN points, and transmitted to a receiving end having a 50Ω termination resistor 105 via a transmission line 14 having a characteristic impedance of 50Ω, Amplified by the receiving amplifier 19. The main driver 100 includes a differential transistor 101, a load resistor 103, and a constant current source 102, and differential input data DiP and DiN are applied to the gate of the transistor. The load resistor 103 is 50Ω in order to match the characteristic impedance of the transmission line. The pre-emphasis driver 106 includes a differential transistor 107 and a constant current source 108.

  On the other hand, a circuit shown in FIG. 11 is conventionally known as a method capable of reducing power consumption (see, for example, Non-Patent Document 2). This transmission circuit system includes an output driver 110, a transmission line 14, a terminating resistor 115, and a receiving amplifier 19. The output driver 110 includes MOS switches 112a, 112b, 111a and 111b, and a constant current source 113. When 112a and 111b are on (112b and 111a are off), current flows from the DoN point to the DoP point via the load resistor 115, and when the opposite side is on, current flows in the reverse direction.

International Solid Circuit Society (ISSCC) 2002 Digest, Session 4, No.4.3

National Semiconductor, LVDS Owner's Manual, Second Edition, Spring 2000, P.1

  The circuit of FIG. 10 has the advantage of high speed and good matching with the transmission line and less signal distortion due to reflection, but on the other hand, the load resistance viewed from the output terminals DoP and DoN is 25Ω, so that it is about 500 mV, for example. In order to ensure the signal amplitude, 20 mA (= 500 mV / 25Ω) is required for the constant current source, and there is a problem that the power consumption becomes extremely large.

  In the circuit of FIG. 11, a voltage of +/− (R · Iout) is generated at both ends of the load resistor 115 when the constant current value is Iout and the load resistor is R. Now, assuming that the resistance value of the termination resistor 115 is 100Ω and the signal amplitude = 500 mV for matching with a transmission line having a characteristic impedance of 50Ω, Iout = 5 mA, and the power consumption is higher than that in the example of FIG. If the voltage is the same, 1/4 is sufficient. However, in this circuit, since impedance matching between the output impedance on the driver side and the transmission line cannot be achieved, there is a problem that distortion may occur in the transmission signal. Furthermore, considering a potential drop at the constant current source and the upper and lower two-stage switches and a signal amplitude at the load of 500 mV, the power supply voltage Vdd needs to be at least about 1.5 V. There was a problem that it could not be used. For example, in the 0.1 μm CMOS process, the allowable breakdown voltage of the transistor is about 1V.

  An object of the present invention is to realize high-speed transmission with low power supply voltage and low power consumption in order to solve the above problems. Another object of the present invention is to provide a transmission circuit that operates with a low power supply voltage and low power consumption and has impedance matching with a transmission line and a pre-emphasis function.

  In order to solve the above problems, in the present invention, a bridge-type differential switch circuit is used as a basic driver circuit, two of them are used, one as a main driver, the other as a pre-emphasis driver, and a differential output. A high-speed data transmission circuit with low voltage and low power operation is realized by a driver circuit that shares terminals, a transmission line, and a termination resistor that matches the characteristic impedance of the transmission line.

  Specifically, the digital data transmission circuit of the present invention is connected to an output driver circuit having a pair of digital data differential input terminals and a pair of differential output terminals, and the pair of differential output terminals. A pair of transmission lines, and a termination resistor provided between the ends of the pair of transmission lines, and the output driver circuit includes a P-type transistor having a source terminal connected to a positive power supply, A differential pair having two sets of circuits in which drains and gates are connected to an N-type transistor having a source terminal connected to a ground power supply, and two drain terminals of the differential pair. A pair of resistors, wherein the pair of digital data differential input terminals are connected to the gate terminals of the differential pair, and the pair of differential output terminals are the drain terminals of the pair of resistors. Connected to the opposite terminal And wherein the Rukoto.

  In the above configuration, it is more preferable if it further includes a sub-driver circuit having a circuit configuration similar to that of the output driver circuit and having a small driving capability. In this case, output terminals of the output driver circuit and the sub driver circuit may be connected to each other, and a delay signal of input data of the output driver circuit may be input to the differential input terminal of the sub driver circuit. . In addition, the output signals of the output driver circuit and the sub driver circuit may be added at least at the time of rising and falling of the input data.

  In the above configuration, it is more preferable that the impedance when the output driver circuit side is viewed from the output terminal of the output driver circuit is matched with the characteristic impedance of the transmission line.

In the above configuration, it is more preferable that the output resistance of the sub driver circuit is variable and the output signal amplitude of the digital data transmission circuit is variable.
In the above configuration, it is more preferable if a selection circuit is provided between the input terminal of the sub driver circuit and the input terminal of the output driver circuit. In this case, the input data from the input terminal of the output driver circuit is input to one input terminal of the selection circuit, and the data having the opposite polarity of the input data is input to the other input terminal of the selection circuit. The pre-emphasis function may be controlled on and off without changing the output impedance of the output driver circuit.

In the above configuration, the termination resistor is a voltage dividing type, and the input signal amplitude to the reception amplifier can be adjusted while matching the impedance when viewed from the transmission line side with the characteristic impedance of the transmission line. It is preferable.
In the above configuration, the termination resistor is connected in parallel between the first pair of resistors connected in parallel between the pair of transmission lines and the positive power source, and the pair of transmission lines and the ground power source. It is still preferred if it comprises a second pair of resistors. In this case, the input signal bias potential to the reception amplifier may be adjusted while matching the parallel value of the first and second pairs of resistors with the characteristic impedance of the transmission line.

  In the above configuration, the gates of the four transistors constituting the sub-driver circuit are connected to independent input terminals so that the transistors are turned on when the input data from the input terminal of the output driver circuit rises and falls. If constituted, it is more preferable.

  According to the present invention, a low power supply voltage operation of about 1 V is possible, and power consumption can be reduced. Further, according to the present invention, a high-speed CMOS fine process can be applied, and, for example, high-speed transmission exceeding several Gbps is possible.

  The present invention uses a bridge-type differential switch circuit as a basic driver circuit, uses two of them, one as a main driver, the other as a pre-emphasis driver, and a driver circuit that shares a differential output terminal and transmission A main configuration is a high-speed data transmission circuit including a line and a termination resistor matched to the characteristic impedance of the transmission line. Embodiments of the present invention will be described below with reference to the corresponding drawings.

  FIG. 3 shows a basic output driver circuit according to the first embodiment of the present invention. In the figure, an output driver 30 comprises P-type field effect transistors (hereinafter abbreviated as PMOS) 32a and 32b, N-type field effect transistors (hereinafter abbreviated as NMOS) 31a and 31b, and output resistors 33a and 33b. It is driven by input data DiP and DiN having the opposite polarity, and is output to differential outputs DoN and DoP. The output signal is transmitted through the transmission line 14, and the received signal is obtained at both ends of the terminating resistor 35 on the receiving side and is amplified by the amplifier 39. The operation of the output driver 30 is as follows. When DiP is “0” and DiN is “1”, 32a and 31b are on, 32b and 31a are off, and the current from the power supply Vdd is 32a⇒33a⇒14⇒35⇒14⇒ 33b⇒31b, and a positive voltage is output to both ends of the termination resistor 35. When DiP is “1” and DiN is “0”, the opposite is true, and 32b⇒33b⇒14⇒35⇒14⇒33a⇒31a flows, and a positive voltage is output at both ends of the termination resistor 35. Is done.

The respective values Rs and Ro of the resistors 33a, 33b, and 35, and the on-resistances of the PMOS and NMOS are, from the point of impedance matching, assuming that the transmission line characteristic impedance is Zo and the on-resistances of the PMOS and NMOS are Rp and Rn. The following relationship is established.
(Equation 1) Rp = Rn
(Expression 2) Rs + Rp = Zo
(Equation 3) Ro = 2 * Zo
For example, if Zo = 50Ω and Rp = Rn = 30Ω, then Rs = 20Ω and Ro = 100Ω. Of course, depending on the frequency of the data, the transmission distance, the transmission quality, etc., these relationships are not strict and a considerable deviation is allowed.

  According to the present embodiment, since an amplitude of 1/2 of the power supply voltage is obtained at both ends of Ro, a signal amplitude of 500 mV is obtained even when the power supply voltage is a low voltage of about 1V. In this way, since the power supply voltage can be reduced, a CMOS fine process can be used, so that the chip size of an IC (integrated circuit) can be reduced, and high-speed and low-power operation can be realized, thereby solving the problems of the prior art.

  Next, as another embodiment, a driver circuit to which a pre-emphasis function is added is shown in FIG. 1, and data input / output timing is shown in FIG. In FIG. 1, 10 is a main driver, 16 is a sub-driver for pre-emphasis, and each circuit configuration is the same as in the first embodiment (FIG. 3). However, since the drivers 10 and 16 are used instead of the driver 30 in comparison with the above embodiment, the transistor size of each driver may be small. In order to achieve impedance matching with the transmission line, the following relationship is necessary between the output resistance Rmo on the main driver side and the output resistances Rso and Zo on the sub driver side.

(Expression 4) Zo = (Rmo * Rso) / (Rmo + Rso)
here,
(Equation 5) Rmo = Rsm + Rpm
(Expression 6) Rpm = Rnm
(Equation 7) Rso = Rss + Rps
(Equation 8) Rps = Rns
However, Rsm, Rpm, and Rnm are the values of the output section resistor 13 of the main driver 10 and the on resistances of the PMOS 12 and the NMOS 11, and Rss, Rps, and Rns are the values of the output section resistance 19 of the sub driver 16, and the PMOS 18 and the NMOS 17 are on. Resistance.
Since the main and sub parallel resistors need only be matched to Zo in this way, the transistor size sum of each driver may be the same as that of the main driver alone as shown in FIG.

  The pre-emphasis operation of this circuit will be described with reference to the timing charts shown in FIGS. P and N of each signal name mean reverse polarity, and EmN is a signal delayed from DiP by time Δt. At t = t0, when DiP = EmN = “0” (DiN = EmP = “1”), 12a, 11b, 18b, and 17a are turned on, so that most of the current from 12a has a receiving end resistance 15 However, a part of the current flows from the DoN point to 17a in the sub driver 16. That is, a difference current between the current from the main driver and the current to the sub driver flows in the positive direction in the resistor 15, and as a result, the potential of DoN becomes V3. Next, when DiP is inverted from “0” to “1” at t = t1, 11a and 12b are turned on, so that current flows to the side of 12b contrary to the above, and the current from 18b is added to the resistance. 15, a negative current flows, and the potential of DoN becomes V1. Further, when t = t2 and EmN is inverted from “0” to “1”, 17b is turned on. Therefore, a part of the current from 12b flows to the 17b side at the DoP point, and the difference current between the main and sub is The resistance 15 flows in the negative direction, and the potential of DoN becomes V2. Thereafter, the DoN and DoP waveforms of FIG. 2 are obtained by a similar process. As can be seen from this waveform, the edge is emphasized (emphasized) at the rising and falling points of the DoN (or DoP) waveform.

Thus, the emphasizing period Δt is determined by the difference between DiP and EmN, that is, the delay amount from DiP. Also, the amplitude difference ΔV of the emphasize is determined by the current difference between the main and sub drivers.
According to the present embodiment, the pre-emphasis function can be achieved without impairing power consumption, transistor size, and impedance matching.

Next, an embodiment capable of controlling the amplitude difference ΔV of the emphasize will be described with reference to FIG. The circuit operation is the same as in FIG. However, the emphasize amount ΔV can be controlled by making the output resistors 43 and 49 variable (programmable). At this time, assuming that the resistance values of the resistors 43 and 49 are VRsm and VRss, respectively, Rsm and Rss in the above (Equation 4) to (Equation 8) are replaced with VRsm and VRss so that these equations are satisfied. Is preferred.
According to the present embodiment, since the resistance value can be easily changed in a programmable manner, it is possible to cope with various transmission line lengths.

FIG. 5 shows an example of a method for generating the input data EmP and EmN of the sub-driver in the embodiment of FIG. 1, and the delay circuit 51 and the selection circuit 52 of FIG. When the input control signal Ectl = “1”, DiP = EmP and DiN = EmN, and the emphasis function is inactive. However, when Ectl = “0”, the DiP signal passes through the delay circuit 51 and passes through the selection circuit. To become EmN. The delay amount Δt of the delay circuit 51 is an emphasis period.
According to the present embodiment, by appropriately turning on and off the pre-emphasis circuit with a simple circuit configuration, it is possible to appropriately have an effect of compensating for high-frequency loss in a transmission line that is a problem at high-speed transmission, and data transmission There is an effect that the reliability of the can be increased.

Another embodiment of the invention is shown in FIGS. Both figures are examples of the configuration of the termination resistor. In the transmission system, the signal amplitude at the receiving end may be defined within a predetermined range by a standard. FIG. 6 is a circuit that can cope with this, and is a voltage dividing circuit composed of resistors 65a and 65b. The signal amplitude at the transmitting end determined by the power supply voltage can be reduced by the voltage dividing ratio between the resistance values R1 and R2 / 2. For this reason, there is an advantage that it can cope with a case where the power supply voltage is large. Here, it is preferable to make impedance matching by making (R1 + R2 / 2) equal to Zo of the transmission line. The embodiment of FIG. 7 is a circuit in which the potential at the receiving end can be adjusted by adjusting the resistors 75a and 75b. Thereby, it is possible to match the input bias level of the amplifier 19 at the subsequent stage. Also in this case, in order to achieve matching with the transmission line 14, it is preferable to make the parallel resistance value of R3 and R4 equal to Zo.
According to the present embodiment, there is an effect that it is possible to cope with various conditions of the input amplifier with a simple configuration of the terminating resistor.

  FIG. 8 shows another embodiment, and FIG. 9 shows a timing diagram of signals. The configuration of the main driver 80 and the sub driver 86 of FIG. 8 is almost the same as that of the embodiment of FIG. 1, but the data input part of the sub driver is partially different. That is, four transistors in the sub-driver 86 are individually controlled. The control signals EmRN, EmRP, EmFN and EmFP are input, for example, at the timing shown in FIG. EmRP and EmRN turn on the controlled transistor when the data DiP rises, and turn it off otherwise. Further, EmFN and EmFP operate when DiP falls, contrary to the above. By this control, as the outputs DoN and DoP, a waveform in which rising and falling edges are emphasized as in the waveform of FIG. 9 is obtained.

  According to the present embodiment, the sub-driver operates at the moment when the rising and falling edges of the input data are short, and can be turned off at other times, so that the power consumption can be reduced.

  According to the present invention, a low-voltage and low-power operation by a fine CMOS is possible, and a high-speed data transmission circuit with simple circuit calibration can be realized. Therefore, the present invention is required to mount a large number of the above circuits in one integrated circuit and economically construct a data transmission system of several Gbps class. Industrial applicability to storage, servers, routers, etc.

The figure which shows the data transmission circuit with a pre-emphasis function of Example 2 of this invention. The figure which shows the signal waveform of each part of the data transmission circuit of FIG. The figure which shows the transmission circuit by the bridge type output driver of Example 1 of this invention. The figure which shows the data transmission circuit with a pre-emphasis function of Example 3 of this invention. The figure which shows the data transmission circuit with a pre-emphasis function of Example 4 of this invention. The figure which shows the 1st example of installation of the termination resistance of Example 5 of this invention. The figure which shows the 2nd example of installation of the termination resistance of Example 5 of this invention. The figure which shows the data transmission circuit with a pre-emphasis function of Example 6 of this invention. The figure which shows the signal waveform of each part of the data transmission circuit of FIG. The figure which shows the conventional data transmission circuit with a pre-emphasis function. The figure which shows the transmission circuit by the conventional bridge type output driver.

Explanation of symbols

10, 30, 40, 80, 100, 110: Main driver circuit 16, 46, 66, 106: Sub-driver circuit for pre-emphasis 14: Transmission line 15, 35, 65a, 65b, 75a, 75b, 105, 115: Termination Resistors 19, 39: Receiving amplifiers 11a, 11b, 12a, 12b, 17a, 17b, 18a, 18b, 31a, 31b, 32a, 32b, 41, 42, 47, 48, 81, 82, 87, 88: MOS Transistors 13, 19, 33a, 33b, 83, 89: Resistors 43, 49: Variable resistors 51: Delay circuit 52: Selection circuit 101, 107: Differential transistors 102, 108, 113: Constant current source 103: Load resistance of driver .

Claims (8)

An output driver circuit having a pair of digital data differential input terminals and a pair of differential output terminals;
A pair of transmission lines connected to the pair of differential output terminals;
A termination resistor provided between the terminations of the pair of transmission lines,
The output driver circuit is
A differential pair comprising two sets of circuits in which drains and gates of a P-type transistor having a source terminal connected to a positive power supply and an N-type transistor having a source terminal connected to a ground power supply are connected;
A pair of resistors connected to the two drain terminals of the differential pair,
The pair of digital data differential input terminals are connected to gate terminals of the differential pair, and the pair of differential output terminals are connected to terminals opposite to the drain terminals of the pair of resistors. A digital data transmission circuit characterized by comprising: In claim 1,
Further comprising a sub-driver circuit having a circuit configuration similar to that of the output driver circuit and having a small driving capability,
The output terminals of the output driver circuit and the sub driver circuit are connected to each other,
A delay signal of input data of the output driver circuit is input to the differential input terminal of the sub driver circuit,
A digital data transmission circuit configured to add output signals of the output driver circuit and the sub-driver circuit at least at the time of rising and falling of the input data. In either claim 1 or 2,
The digital data transmission circuit, wherein an impedance when the output driver circuit side is viewed from an output terminal of the output driver circuit is an impedance matched with a characteristic impedance of the transmission line. In claim 2,
An output resistance of the sub driver circuit is variable, and an output signal amplitude of the digital data transmission circuit is variable. In claim 2,
Comprising a selection circuit between the input terminal of the sub-driver circuit and the input terminal of the output driver circuit;
The input data from the input terminal of the output driver circuit is input to one input terminal of the selection circuit, and the data having the reverse polarity of the input data is input to the other input terminal of the selection circuit via the delay circuit. Entered,
A digital data transmission circuit configured to control on / off of a pre-emphasis function without changing an output impedance of the output driver circuit. In claim 1,
The termination resistor is a voltage dividing type, and is configured to adjust the amplitude of the input signal to the reception amplifier while matching the impedance when viewed from the transmission line side with the characteristic impedance of the transmission line. Digital data transmission circuit. In claim 1,
The termination resistor includes a first pair of resistors connected in parallel between the pair of transmission lines and the positive power source, and a second pair connected in parallel between the pair of transmission lines and the ground power source. A pair of resistors,
Digital data transmission characterized in that the input signal bias potential to the receiving amplifier can be adjusted while matching the parallel value of the first and second pair of resistors with the characteristic impedance of the transmission line. circuit. In claim 2,
The gates of the four transistors constituting the sub driver circuit are connected to independent input terminals, respectively, so that the transistors are turned on at the time of rising and falling of input data from the input terminal of the output driver circuit. A digital data transmission circuit characterized by that.

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