WO2016185847A1 - Input/output interface circuit - Google Patents

Abstract

[Problem] To provide an I/O circuit which is high speed and has low power consumption. [Solution] A differential-type I/O circuit is provided with: a driver 10 which outputs complementary signals corresponding to an input signal; a pair of transmission lines 20 which comprise a first line 21 and a second line 22, and which transmit the complementary signals outputted from the driver; and a receiver 30 into which the complementary signals transmitted through the pair of transmission lines are inputted. The driver includes: a positive-phase CMOS inverter 11 which supplies, to the first line, a positive-phase signal having the same phase as the input signal; and a reverse-phase CMOS inverter 12 which supplies, to the second line, a reverse-phase signal having the reverse phase to the input signal. The positive-phase CMOS inverter and the reverse-phase CMOS inverter are configured including nMOS transistors and pMOS transistors. The on resistance values of the nMOS transistors and the pMOS transistors respectively correspond to a specified value which is ½ of the characteristic impedance of the pair of transmission lines, or are matched within the range of ±30% of the specified value.

Description

I / O interface circuit

The present invention relates to an input / output interface circuit. The input / output interface circuit of the present invention transmits a digital signal output from a driver to a receiver via a transmission line. More specifically, the present invention relates to an interface circuit intended to significantly reduce power consumption by substantially opening the terminations of a driver and a receiver.

In recent years, it has become an era of cloud computing, and high performance communication between LSIs such as logic LSIs (Large Scale Integration) and memory LSIs and reduction of power consumption are regarded as urgent issues. In particular, at present, it is required to increase the speed of an input / output interface circuit (hereinafter also referred to as “I / O circuit”) included in an LSI and to increase the bandwidth. In other words, at present, there is a demand for speeding up data processing by an I / O circuit, processing for fetching data from a memory, and network function processing such as routers and switches.

However, it can be said that the processing speed of conventional Neumann computers and memory switches has reached its limit. This is because the I / O circuit used in the conventional Neumann computer is a circuit for performing communication between wirings that are somewhat long. In other words, if the I / O circuit includes a long wiring, signal delay due to the wiring and deterioration and attenuation of the signal waveform due to the characteristics of the wiring are likely to occur. Become. Also, in order to realize high-speed processing in such an I / O circuit, the driving power of the driver that is the output circuit is increased, and further, the signal waveform attenuated in the receiver that is the input circuit is recovered. There is a need to. In general, it is said that the power of the internal circuit of the LSI is consumed by 50% to 200% in the I / O circuit. Therefore, in order to compensate for the power consumed in the I / O circuit, a circuit for increasing the driving force is installed on the driver side, or a circuit for recovering the attenuated signal waveform is installed on the receiver side. Need to be done. However, if the driving force of the driver is increased or the signal waveform is restored on the receiver side, extra power is consumed.

As described above, in the conventional I / O circuit, if the processing speed is increased or the bandwidth is increased, the power consumption is increased. Conversely, if the power consumption is decreased, the processing speed is decreased or the bandwidth is reduced. It becomes. Therefore, in order to respond appropriately to recent cloud computing, it is necessary to simultaneously solve the two conflicting problems of reducing power consumption while increasing bandwidth and speeding up processing. .

Here, as an attempt to solve such a problem, a technique has been proposed in which a termination resistor that matches the characteristic impedance of the transmission line is provided on the termination side of the driver (Patent Document 1). In other words, in the prior art of this Patent Document 1, by attaching a termination resistor that matches the characteristic impedance to the transmission line immediately before the receiver, all the signal energy reaching the receiver end is converted into heat, and the signal energy is received at the receiver end. Prevents total reflection. For this reason, in the conventional I / O circuit, the signal energy is always transmitted in one direction from the driver to the receiver. In this way, by adjusting the resistance value of the termination resistor and eliminating the mismatch with the characteristic impedance of the transmission line, even a high-speed I / O circuit in the several hundred Mbps to Gbps band can be received from the driver. In the transmission line up to this point, it is possible to prevent multiple reflections of signal energy. As a result, the digital signal is not affected by the reflected wave in the transmission path from the driver to the receiver, so that the signal waveform can be prevented from deteriorating. Thereby, according to the prior art of patent document 1, it is supposed that the signal transmission in a transmission line can be sped up.

JP 2000-174505 A

However, as in the conventional I / O circuit disclosed in Patent Document 1, when a termination resistor is provided in the transmission path immediately before the receiver, the energy of the signal output from the driver is absorbed by this termination resistor. For this reason, in a conventional I / O circuit having a termination resistor, even if a signal is output at the maximum output from the driver side, the signal amplitude may deteriorate to 1/3 or less depending on the characteristics of the transmission path. there were. In addition, even when a termination resistor is provided in the transmission line immediately before the receiver as in the I / O circuit disclosed in Patent Document 1, the waveform of the transmission signal transmitted to the receiver is the same as the DC resistance and the length of the line. There is a problem that it is attenuated according to the height, and is accompanied by a dullness such as rising and falling gradients. Generally, when the waveform of this transmission signal is attenuated or becomes dull, it is necessary to add a recovery circuit for shaping the waveform on the receiver side. Thus, if a recovery circuit is provided on the receiver side, extra power is consumed in the signal transmission processing in the I / O circuit. In particular, when the device configuration becomes complicated and the number of I / O circuits increases, the power required for waveform recovery also increases, and as a result, the increase in power consumption in the entire device has become a very serious problem. .

Such a problem of the prior art is considered to be caused by a configuration in which a termination resistor is provided on the driver side or the receiver side, and reflection or re-reflection of signal energy is prevented by this termination resistor.

Therefore, the present invention provides a terminal and a receiving end that are substantially not provided with a terminating resistor on the driver side and the receiver side to prevent attenuation of signal energy transmitted through the transmission line, and An object is to prevent multiple reflection of signal energy generated in a transmission line. That is, the I / O circuit of the present invention first increases the speed of transmission processing and increases the bandwidth by preventing multiple reflections of signal energy in the transmission path. The I / O circuit of the present invention reduces power consumption in the entire circuit by preventing attenuation of signal energy output from the driver. Thus, the present invention aims to simultaneously solve two conflicting problems of reducing power consumption while realizing an increase in bandwidth and a high-speed processing.

Accordingly, the inventors of the present invention have intensively studied the means for solving the above-described conventional problems. As a result, in the differential input / output interface circuit (I / O circuit), termination resistors are provided on the driver side and the receiver side. Even if it is not provided, by making the on-resistance value of the nMOS transistor and pMOS transistor constituting the driver substantially equal to 1/2 of the characteristic impedance of the pair transmission line, unexpectedly, the signal energy in the transmission line is It was found that no multiple reflection occurs. That is, the power consumption can be greatly reduced by eliminating the termination resistors on the driver side and the receiver side and opening the terminations of the driver and the receiver. Furthermore, multiple reflections of signal energy in the transmission path can be avoided by making the on-resistance value of the driver substantially equal to 1/2 of the characteristic impedance of the pair transmission path. Therefore, for example, the bandwidth of the output signal from the driver can be expanded, or signal transmission in a high-speed band of 1 Gbps or more can be performed. Then, the present inventors have conceived that the problems of the prior art can be solved based on the above knowledge, and have completed the present invention. More specifically, the present invention has the following configuration.

A first aspect of the present invention relates to a differential input / output interface circuit.
The differential input / output interface circuit includes a driver 10, a pair transmission line 20, and a receiver 30. The driver 10 outputs a complementary signal corresponding to the input signal. The pair transmission line 20 includes a first line 21 and a second line 22 that transmit complementary signals output from the driver 10. The receiver 30 receives a complementary signal transmitted through the pair transmission path 20.
Here, the driver 10 includes a normal phase CMOS inverter 11 and a reverse phase CMOS inverter 12. The positive phase CMOS inverter 11 supplies a positive phase signal in phase with the input signal to the first line 21. The negative phase CMOS inverter 12 supplies a negative phase signal having a phase opposite to that of the input signal to the second line 22.
The positive phase CMOS inverter 11 and the negative phase CMOS inverter 12 include nMOS transistors 11a and 12a and pMOS transistors 11b and 12b, respectively.
The on-resistance values of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b are equal to a specified value that is 1/2 of the characteristic impedance of the pair transmission line 20, or ± 30% of the specified value. Consistent in scope.

As in the above configuration, in the differential input / output interface circuit, the on-resistance values of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b (hereinafter also simply referred to as “MOS transistors”) are used as the pair transmission line. It is made to substantially coincide with 1/2 of the characteristic impedance of 20. As a result, the signal energy reflected by the receiver 30 is absorbed by the driver 10. Therefore, it is possible to avoid re-reflection of the signal energy on the driver 10 side, and thus it is possible to prevent multiple reflection of the signal energy in the pair transmission path 20.

In the differential input / output interface circuit according to the present invention, it is preferable that the driver 10 side and the receiver 30 side are not provided with termination resistors having a resistance value of less than 500Ω for preventing reflection of signal energy. .

As described above, by eliminating the terminal resistance from the driver 10 side and the receiver 30 side, it is possible to prevent the signal energy output from the driver 10 from being attenuated. As a result, it is not necessary to increase the driving force of the driver 10 or to recover the signal waveform in the receiver 30, so that power consumption during signal transmission can be reduced. Further, as described above, according to the present invention, multiple reflection in the pair transmission line 20 can be prevented, so that it is not necessary to provide a termination resistor for preventing reflection. Further, by eliminating the termination resistor, the configuration of the input / output interface circuit can be simplified, and the manufacturing cost can be reduced.

In the differential input / output interface circuit according to the present invention, the receiver 30 is preferably configured to include a normal phase CMOS inverter 31 and a reverse phase CMOS inverter 32 as in the case of the driver 10. That is, the positive phase signal transmitted through the first line 21 is input to the positive phase CMOS inverter 31, and the negative phase signal transmitted through the second line 22 is input to the negative phase CMOS inverter 32.

As described above, by making the configuration on the driver 10 side and the receiver 30 side equivalent, the signal energy output from the driver 10 is almost totally reflected on the receiver 30 side. By this total reflection, the receiver 30 can feel an amplitude twice as large as the arrival amplitude, and provides a means capable of outputting the amplitude of the driver 10 by 1/2 of the conventional type. Then, by absorbing the totally reflected energy on the driver 10 side, it is possible to appropriately eliminate the deterioration and attenuation of the signal waveform.

In the differential input / output interface circuit according to the present invention, resistors 41, 42, 43, and 44 having a resistance value of 500Ω or more are connected to the power supply side and the ground side on the external connection side of the driver 10 and the receiver 30, respectively. It is good also as being done.

As described above, ESD (Electro-Static Discharge) can be avoided by providing resistors 41, 42, 43, and 44 having resistance values of 500Ω or more on the driver 10 side and the receiver 30 side, respectively. Can do. That is, in particular, in a high-speed input / output interface circuit such as a differential system, a clamp diode is generally inserted as an ESD countermeasure. However, since the clamp diode has a large capacitance component, it is difficult to perfectly match the termination resistance value. In addition, the capacity of the clamp diode is a major obstacle to high-speed operation. Therefore, in the present invention, by inserting the resistors 41, 42, 43, and 44 having relatively large resistance values, ESD can be appropriately eliminated while eliminating the clamp diode. The resistors 41, 42, 43, and 44 here have a relatively large resistance value for the purpose of eliminating ESD, and are termination resistors for the purpose of absorbing a reflected wave of signal energy. This is a different configuration.

In the differential input / output interface circuit according to the present invention, the on-resistance value of the MOS transistor may be set lower than a specified value (a value that is 1/2 of the characteristic impedance of the pair transmission line). In this case, the present invention further includes resistance adjusting means 50 that can match the on-resistance value of at least one of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b with the specified value. preferable.

As described above, by providing the resistance adjusting means 50, it is possible to finely adjust the on-resistance value of the MOS transistor so as to match the specified value. In particular, a state in which the on-resistance value of the MOS transistor exceeds a specified value is not a preferable state because of problems such as increased power consumption. For this reason, as described above, it is preferable that the on-resistance value of the MOS transistor is previously controlled to be lower than a specified value, and that the lower portion is adjusted by raising the resistance value by the resistance adjusting means 50.

The second aspect of the present invention relates to a single-ended input / output interface circuit. It is difficult to operate a single-ended input / output interface circuit at a higher speed than the differential interface circuit described above. For this reason, although the differential method is a preferred form, the structure for preventing multiple reflections in the line will be described below also for the single-ended method.

The single-ended input / output interface circuit includes a driver 110 that outputs a signal, a transmission path 120 that transmits a signal output from the driver 110, and a receiver 130 that receives a signal transmitted through the transmission path 120. .
The driver 110 includes a CMOS inverter 111 that supplies a signal to the transmission line 120. The CMOS inverter 111 includes an nMOS transistor 111a and a pMOS transistor 111b.
The on-resistance values of the nMOS transistor 111a and the pMOS transistor 111b are equal to a specified value equal to the characteristic impedance of the transmission line 20, or matched within a range of ± 30% of the specified value.
This makes it possible to prevent multiple reflections in the line even for the single-ended method.

The input / output interface circuit of the present invention can increase the speed of transmission processing and the bandwidth by preventing multiple reflection of signal energy in the transmission path. Further, the input / output interface circuit can reduce power consumption in the entire circuit by preventing attenuation of signal energy output from the driver. Therefore, according to the present invention, it is possible to reduce power consumption while realizing an increase in bandwidth and speeding up of processing.

That is, according to the present invention, I / O signals can be transmitted with low power consumption. In addition, the driver and receiver have a minimum circuit configuration, low power consumption, and can perform signal processing at high speed. For example, the I / O circuit of the present invention can suppress power consumption to 1/2 to 1/10 of the conventional one, and can realize high-speed signal transmission with a clock frequency of 10 Gbps or more.

FIG. 1 is a block diagram showing the basic concept of an I / O circuit according to the present invention. FIG. 2 is a block diagram illustrating a configuration example of a differential I / O circuit. FIG. 3 is a block diagram showing a configuration example in which a resistance for ESD countermeasure is inserted in a differential I / O circuit. FIG. 4 is a block diagram illustrating a configuration example in which a resistance adjusting unit is provided in a differential I / O circuit. FIG. 5 is a block diagram illustrating a configuration example of a single-ended I / O circuit. FIG. 6 is a block diagram illustrating a configuration example in which a resistance against ESD is inserted in a single-ended I / O circuit. FIG. 7 is a block diagram showing a configuration example in which resistance adjusting means is provided in a single-ended I / O circuit. FIG. 8 is a block diagram showing a modification of the single-ended I / O circuit. FIG. 9 shows a waveform of a complementary signal according to the embodiment. FIG. 10 shows the current of the driver according to the embodiment. FIG. 11 shows the configuration of the driver / receiver according to the embodiment. FIG. 12 shows an in-chip multilayer structure according to the embodiment. FIG. 13 shows the layer structure of the process according to the embodiment.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. The present invention is not limited to the embodiments described below, but includes those appropriately modified by those skilled in the art from the following embodiments.
In this specification, “A to B” means “A to B”.

[1. Overview of I / O Circuit According to the Present Invention]
The present invention relates to an input / output interface circuit (I / O circuit). The I / O circuit of the present invention includes a circuit responsible for input / output of signals to / from a global bus within a chip, a circuit responsible for input / output of signals between chips, an interposer wiring, and a board wiring. And various circuits used for digital signal input / output, such as those connected via connection terminals and connectors.

First, the basic concept of the I / O circuit according to the present invention will be described with reference to FIG. In FIG. 1, the configuration of the conventional I / O circuit and the configuration of the I / O circuit of the present invention are compared and drawn. 1A to 1C show a conventional I / O circuit, and FIG. 1D shows an I / O circuit of the present invention.

FIG. 1A shows a conventional I / O circuit. The I / O circuit of FIG. 1A sends a transmission signal from a driver with a large driving force through a driving force enhancement circuit, and the receiver receives the transmission signal with a normal small circuit. Further, as shown in FIG. 1A, a termination resistor is inserted immediately before the receiver. The resistance value of this termination resistor substantially matches the characteristic impedance of the transmission line. Thus, reflection of signal energy output from the driver is prevented on the receiver side.

FIG. 1B is a conventional I / O circuit obtained by improving the I / O circuit of FIG. In the I / O circuit of FIG. 1B, the attenuation of signal energy in the transmission line is large. For this reason, in order to recover the amplitude and waveform of the signal at the receiver, the receiver includes an amplitude recovery circuit. In order to prevent signal energy from being reflected on the receiver side, a terminating resistor is provided immediately before the receiver.

FIG. 1C shows a conventional I / O circuit in which a terminating resistor is inserted on the driver side. By inserting a termination resistor on the driver side, the signal energy reflected by the receiver can be absorbed on the driver side.

Here, especially in differential I / O circuits that operate at high speed, the output signal from the driver is reflected by the receiver, or the reflected wave returns to the driver and re-reflects. The problem is that multiple reflections occur and noise occurs. In addition, in a differential I / O circuit that operates at high speed, the output signal from the driver is easily affected by the noise caused by the reflected energy generated in the transmission line, so it is necessary to absorb this reflected energy. . Therefore, as shown in FIGS. 1A to 1C, in the conventional I / O circuit, a terminating resistor is inserted on either the driver side or the receiver side to absorb the reflected energy, and the output signal It is supposed to prevent deterioration and attenuation of the water. However, when a terminating resistor is inserted, the energy of the signal output from the driver is attenuated. Therefore, it is common to provide a driving force enhancing circuit on the driver side to amplify the output signal. In addition, when the transmission line has a long attenuation, such as when the transmission line has a large attenuation of energy, it is necessary to provide an amplitude recovery circuit on the receiver side in addition to the driving force enhancement circuit on the driver side. In this way, in a configuration that absorbs reflected energy using a termination resistor, the power consumption during signal transmission increases, such as the need to insert a driving force booster circuit in the driver or to provide a receiver amplitude recovery circuit. There was a problem to do.

Therefore, the present invention eliminates termination resistors on the driver side and the receiver side as shown in FIG. An object of the present invention is to prevent the occurrence of noise due to multiple reflection in the transmission line even in a configuration that eliminates the termination resistor. That is, as shown in FIG. 1D, in the I / O circuit of the present invention, the transmission signal is sent from the driver circuit, the signal energy is totally reflected at the receiver, and the reflected energy is absorbed by the driver itself. It is configured. According to such a configuration, as shown in FIG. 1D, it is possible to eliminate the termination resistor for preventing multiple reflections of reflected energy from the I / O circuit. According to such a configuration, an I / O circuit that can operate at high speed with low power consumption can be realized. A specific configuration of the present invention will be described in detail below.

[2. Differential I / O circuit]
[2-1. Basic form of differential I / O circuit]
FIG. 2 is a schematic configuration diagram illustrating an example of an input / output interface circuit (I / O circuit) 1 according to an embodiment of the present invention. In the present embodiment, the I / O circuit 1 is configured to operate in a differential manner. The differential system transmits two electrical signals (complementary electrical signals) that are in opposite phases to each other via a pair transmission line including two transmission lines, and calculates the potential difference between the two electrical signals. It is transmitted as a difference in signal level (L or H).

As shown in FIG. 2, the differential I / O circuit 1 includes a driver 10 that outputs a digital signal, a pair transmission path 20 that transmits the digital signal, and a receiver 30 that detects the digital signal. Specifically, the driver 10 is a CMOS differential driver, and the receiver is a CMOS differential receiver. The pair transmission line 20 is electrically connected so that signals can be transmitted and received between the driver 10 and the receiver 30.

A digital signal (S) and / or a digital signal (/ S) to be transmitted to the receiver 30 is input to the driver 10. For example, upon receiving the digital signal (S), the driver 10 complements the digital signal (S) and outputs a pair of complementary signals (Q, / Q). That is, as shown in FIG. 2, the CMOS differential driver 10 includes a normal phase CMOS inverter 11 and a negative phase CMOS inverter 12. The positive phase CMOS inverter 11 outputs a positive phase signal (Q) in phase with the digital signal (S) input to the driver 10. On the other hand, the negative-phase CMOS inverter 12 outputs a negative-phase signal (/ Q) that is opposite in phase to the digital signal (S) input to the driver 10. As a result, a normal phase signal (Q) and a negative phase signal (/ Q) which are complemented to each other are generated.

More specifically, the positive phase CMOS inverter 11 of the driver 10 includes an nMOS transistor 11a and a pMOS transistor 11b. In the positive phase CMOS inverter 11, the nMOS transistor 11a is inserted on the power supply side and becomes a pull-up element. In the positive phase CMOS inverter 11, the pMOS transistor 11b is inserted on the ground side and becomes a pull-down element. The nMOS transistor 11a and the pMOS transistor 11b are set to have the same on-resistance value. As a result, when the level of the input digital signal (S) transitions, one of the nMOS transistor 11a and the pMOS transistor 11b is turned on, and the other is turned off. As a result, the positive phase CMOS inverter 11 of the driver 10 outputs a positive phase signal (Q) in phase with the input digital signal (S).

Similarly, the anti-phase CMOS inverter 12 of the driver 10 includes an nMOS transistor 12a and a pMOS transistor 12b. In the reverse phase CMOS inverter 12, the pMOS transistor 12b is inserted on the power supply side and becomes a pull-up element. In the reverse phase CMOS inverter 12, an nMOS transistor 12a is inserted on the ground side to serve as a pull-down element. The nMOS transistor 12a and the pMOS transistor 12b are set to have the same on-resistance value. As a result, when the level of the input digital signal (S) transitions, one of the nMOS transistor 12a and the pMOS transistor 12b is turned on, and the other is turned off. As a result, the negative phase CMOS inverter 12 of the driver 10 outputs a negative phase signal (/ Q) that is opposite in phase to the input digital signal (S).

As shown in FIG. 2, the pair transmission line 20 is configured by a pair of a first line 21 and a second line 22. As shown in FIG. 2, the first line 21 is connected to the positive phase CMOS inverter 11 of the driver 10. For this reason, the positive phase signal (Q) output from the positive phase CMOS inverter 11 of the driver 10 propagates through the first line 21. On the other hand, the second line 22 is connected to the reverse phase CMOS inverter 12 of the driver 10. For this reason, the negative phase signal (/ Q) output from the negative phase CMOS inverter 12 of the driver 10 propagates through the second line 22.

Also, the pair transmission line 20 has a predetermined characteristic impedance. The characteristic impedance is an impedance not related to the length of the transmission line (ie, “characteristic”) when AC electric energy (digital signal) is transmitted using the transmission line. In the present specification, the “characteristic impedance of the pair transmission line” means the capacitance sensed by the voltage (or electric field) generated between the first line 21 and the second line 22, the first line 21 and the second line 22. This is the square root of the ratio (synthetic inductance / capacitance) of the combined inductance (the self-inductance of the first line 21 + the self-inductance of the second line 22−the mutual inductance) sensed by the current (or magnetic field) of each of the lines 22. Here, the dimension of the first line 21 and the dimension of the second line 22 are preferably set to be equal to each other so that there is no difference in design theory. Substantially, the dimension of the first line 21 is preferably within an error of ± 5% and particularly preferably within an error of ± 1% with respect to the dimension of the second line 22. Moreover, it is preferable that the first line 21 and the second line 22 are always set to be constant so that the characteristic impedance does not fluctuate from the start to the end in terms of design theory. A technique for suppressing the difference in characteristic impedance between the lines 21 and 22 and for suppressing fluctuation of the characteristic impedance on the line is well known. By utilizing such a known technique, the characteristic impedances of the first line 21 and the second line 22 can theoretically be made equal, and the characteristic impedance on the line can be made constant.

As shown in FIG. 2, a pair of complementary signals (Q, / Q) propagated through the pair transmission path 20 are input to the receiver 30. The receiver 30 detects a digital signal based on a pair of complementary signals (Q, / Q). That is, since the positive phase signal (Q) propagating through the first line 21 and the negative phase signal (/ Q) propagating through the second line 22 are always opposite in polarity, the receiver 30 A digital signal can be detected by recognizing the potential difference as a difference in signal level (L or H). As shown in FIG. 2, the receiver 30 is configured as a CMOS differential receiver equivalent to the driver 10. That is, the CMOS differential receiver 30 includes a normal phase CMOS inverter 31 and a reverse phase CMOS inverter 32. The positive phase CMOS inverter 31 is connected to the first line 21 and receives a positive phase signal (Q) propagated through the first line 21. On the other hand, the negative phase CMOS inverter 32 is connected to the second line 22 and receives the negative phase signal (/ Q) propagated through the second line 22.

More specifically, the positive phase CMOS inverter 31 of the receiver 30 includes an nMOS transistor 31a and a pMOS transistor 31b. In the positive phase CMOS inverter 31, the nMOS transistor 31a is inserted on the power supply side and becomes a pull-up element. In the positive phase CMOS inverter 31, the pMOS transistor 31 b is inserted on the ground side and becomes a pull-down element. As a result, the positive phase CMOS inverter 31 of the receiver 30 receives the positive phase signal (Q) propagated through the first line 21.

Similarly, the reverse phase CMOS inverter 32 of the receiver 30 includes an nMOS transistor 32a and a pMOS transistor 32b. In the reverse phase CMOS inverter 32, the pMOS transistor 32b is inserted on the power supply side to be a pull-up element. In the reverse phase CMOS inverter 32, an nMOS transistor 32a is inserted on the ground side to serve as a pull-down element. Thereby, the anti-phase CMOS inverter 32 of the receiver 30 receives the anti-phase signal (/ Q) propagated through the second line 22.

As shown in FIG. 2, in addition to the above configuration, a ground line 23 can be provided at a position separated from the pair transmission line 20 so as not to interfere. The ground line 23 connects the driver 10 and the ground side of the receiver 30. In the differential method, even if there are a plurality of drivers 10, it can be said that one common line is sufficient.

Next, the operation of the I / O circuit 1 having the above configuration will be described.
In the I / O circuit 1, when the digital signal (S) transitions from L level to H level, in the positive phase CMOS inverter 11 of the driver 10, the nMOS transistor 11a is switched from OFF to ON, and the pMOS transistor 11b is switched from ON to OFF. Switch. On the other hand, in the reverse phase CMOS inverter 12, the pMOS transistor 12b is switched from ON to OFF, and the nMOS transistor 12a is switched from OFF to ON. As a result, the charge for shifting the input terminal of the positive phase CMOS inverter 31 of the receiver 30 from the L level to the H level is supplied from the positive phase CMOS inverter 11 of the driver 10 to the first line 21. At the same time, the charge for transitioning the input terminal of the reverse phase CMOS inverter 32 of the receiver 30 from the H level to the L level is pulled from the second line 22 to the ground (ground) via the reverse phase CMOS inverter 12 of the driver 10. It is pulled out and becomes the ground potential, that is, the L level. Such a phenomenon is transmitted to the end of the receiver 30 in a transmission time corresponding to the length of the transmission line 20, and a positive signal for causing the input end of the positive phase CMOS inverter 31 of the receiver 30 to transition from the L level to the H level. Energy is supplied from the positive phase CMOS inverter 11 of the driver 10 to the first line 21 and, at the same time, negative signal energy for causing the input terminal of the negative phase CMOS inverter 32 of the receiver 30 to transition from H level to L level. Can be seen as being supplied from the reverse phase CMOS inverter 12 of the driver 10 to the second line 22. Thus, the electromagnetic field in which the positive phase and the reverse phase are integrated is recognized as an electromagnetic field pulse having the defined characteristic impedance at the moment when it flows through the transmission line 20 defined by the characteristic impedance. When an impedance part is encountered, partial reflection occurs at a ratio ((encountered impedance−transmission line characteristic impedance) / (encountered impedance + transmission line characteristic impedance)). An important point is that if the line 21 is connected to the power source with a 1/2 impedance and the line 22 is connected to the ground with an impedance of 1/2, the power source / ground pair line is 1/2 + 1/2. = 1 is a matching end and a condition that does not reflect.

Thus, on the receiver 30 side, the input terminal of the positive phase CMOS inverter 31 is switched from L level to H level, and the input terminal of the negative phase CMOS inverter 32 is switched from H level to L level. Then, after a time corresponding to the length of the transmission line 20, in the positive phase CMOS inverter 31 of the receiver 30, the nMOS transistor 31a is turned from OFF to ON, and the pMOS transistor 31b is turned from ON to OFF. In the reverse phase CMOS inverter 32 of the receiver 30, the pMOS transistor 32b is turned from OFF to ON, and the nMOS transistor 32a is turned from ON to OFF. As a result, in the receiver 30, the outputs of the normal phase CMOS inverter 31 and the negative phase CMOS inverter 32 are changed from L level to H level. As a result, the received digital signal output from the CMOS differential receiver 30 changes from L level to H level. Therefore, the CMOS differential receiver 30 has received a digital signal equal to the digital signal (S) input to the driver 10.

On the other hand, when the digital signal (S) input to the driver 10 transitions from the H level to the L level, an operation opposite to the above-described operation is performed. That is, when the digital signal (S) transitions from the H level to the L level, in the positive phase CMOS inverter 11 of the driver 10, the nMOS transistor 11a is switched from ON to OFF, and the pMOS transistor 11b is switched from OFF to ON. In the reverse phase CMOS inverter 12 of the driver 10, the pMOS transistor 12b is switched from OFF to ON, and the nMOS transistor 12a is switched from ON to OFF. As a result, after a time corresponding to the length of the transmission line 20, the charge for shifting the input terminal of the positive phase CMOS inverter 31 of the receiver 30 from the H level to the L level is transferred from the first line 21 to the driver 10. It is pulled out to the ground through the positive phase CMOS inverter 11. At the same time, the charge for shifting the input terminal of the negative phase CMOS inverter 32 of the receiver 30 from the L level to the H level is supplied from the negative phase CMOS inverter 12 of the driver 10 to the second line 22. In this phenomenon, negative signal energy for shifting the input terminal of the positive phase CMOS inverter 31 of the receiver 30 from the H level to the L level is supplied from the positive phase CMOS inverter 11 of the driver 10 to the first line 21. After a time corresponding to the length of the transmission line, the positive signal energy for causing the input terminal of the reverse phase CMOS inverter 32 of the receiver 30 to transition from the L level to the H level is supplied from the reverse phase CMOS inverter 12 of the driver 10 to the second level. It can be seen that it is supplied to the line 22.

Thus, after a time corresponding to the length of the transmission line 20, on the receiver 30 side, the input terminal of the normal phase CMOS inverter 31 is changed from H level to L level, and the input terminal of the negative phase CMOS inverter 32 is changed from L level to H level. Become a level. Thereby, in the positive phase CMOS inverter 31 of the receiver 30, the nMOS transistor 31a is switched from ON to OFF, and the pMOS transistor 31b is switched from OFF to ON. In the reverse phase CMOS inverter 32 of the receiver 30, the pMOS transistor 32b is switched from ON to OFF, and the nMOS transistor 32a is switched from OFF to ON. As a result, the outputs of the positive phase CMOS inverter 31 and the negative phase CMOS inverter 32 on the receiver 30 side are both changed from H level to L level. As a result, the received digital signal output from the CMOS differential receiver 30 changes from H level to L level. Therefore, the CMOS differential receiver 30 has received a digital signal equal to the digital signal (S) input to the driver 10.

As described above, in the differential I / O circuit 1, when the level of the digital signal (S) transitions, the complementary signal energy is supplied from the CMOS differential driver 10 to the pair transmission line 20. A pair of complementary signals (Q, / Q) obtained by complementing the digital signal (S) can be transmitted to the CMOS differential receiver 30 via the pair transmission line 20.

The above description is the basic configuration and operation of the differential I / O circuit 1 according to the present invention.
Here, in the conventional differential CMOS driver, the on-resistance values of the nMOS transistor and the pMOS transistor are generally set to about 1 to 5Ω. In the conventional CMOS driver, current control transistors are inserted on the power supply side and the ground side, respectively, in order to prevent a through current from being generated when an input digital signal transitions. However, since this current control transistor is a current control channel operating in an unsaturated state, the on-resistance value is in a high impedance state. Accordingly, the signal energy reflected and returned from the receiver through a round trip time corresponding to the length of the transmission line 20 is reflected again by the current control transistor and sent back to the pair transmission line, resulting in transmission. Multiple reflection noise occurs in the road. In order to prevent this, in the conventional I / O circuit, as described with reference to FIG. 1, a terminating resistor is inserted on the transmitting end side. However, as described above, the I / O circuit in which the termination resistor is inserted has a problem that power consumption increases.

On the other hand, the differential I / O circuit 1 according to the present invention can have a simple circuit configuration that does not require a termination resistor, as shown in FIG. Therefore, in the I / O circuit 1 of the present invention, the on-resistance values (Ron) of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b included in the driver 10 are set to the characteristic impedance (Z0) of the pair transmission line 20, respectively. Substantially equal to a specified value which is 1/2 of the above. In the present embodiment relating to the differential method, the “specified value” means a value that is ½ of the characteristic impedance of the pair transmission line 20. For example, in the differential type I / O circuit 1, the characteristic impedance of the pair transmission line 20 is often set to 100Ω. Therefore, when the characteristic impedance of the pair transmission line 20 is 100Ω, the on-resistance values of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b included in the driver 10 are set to 50Ω, respectively. That is, when the on-resistance value of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b (MOS transistors) is “Ron” and the characteristic impedance of the pair transmission line 20 is “Z0”, the relationship of 1/2 · Z0 = Ron It is ideal to satisfy.

However, it is only necessary that the on-resistance value (Ron) of the MOS transistor substantially coincides with the specified value (1/2 · Z0) that is ½ of the characteristic impedance (Z0) of the pair transmission line 20. For example, the on-resistance (Ron) of the MOS transistor may be matched within a range of ± 30% with respect to the specified value (1/2 · Z0). However, the on-resistance (Ron) of the MOS transistor is preferably within a range of ± 10% with respect to the specified value (1/2 · Z0), particularly preferably ± 5%, and ± 1% Ideally, it should be within the range.

As described above, by making the on-resistance values of the MOS transistors constituting the driver 10 coincide with the specified values that are ½ of the characteristic impedance of the pair transmission line 20, the signal energy reflected at the receiver 30 is It can be absorbed by the driver 10.

More specifically, as shown in FIG. 2, in the I / O circuit 1, when the digital signal (S) is at the H level, the nMOS transistor 11a is turned on in the positive phase CMOS inverter 11 of the driver 10, The pMOS transistor 11b is OFF. Similarly, in the I / O circuit 1, when the digital signal (/ S) is at the L level, in the reverse phase CMOS inverter 12 of the driver 10, the nMOS transistor 12a is turned off and the pMOS transistor 12b is turned on. Looking at this overall state, since the positive phase nMOS transistor 11a is ON and the negative phase pMOS transistor 12b is ON from the power supply Vdd, it functions as a matching end even if the reflected wave returns from the receiver 30 at this timing. To do. In addition, since it is differential, it is inconsistent with the above state, and is a matching end even when the positive phase pMOS transistor 11b is ON and the negative phase nMOS transistor 12a is ON. Accordingly, no re-reflection from the driver 10 toward the receiver 30 occurs at any timing, and the reflected wave from the receiver 30 is always absorbed by the driver 19. In addition, even if the length of the transmission line changes and the reflection timing changes, this state can be maintained universally.

Thereby, in the I / O circuit 1 of the present invention, the driver 10 itself absorbs the reflected energy, so that the signal energy reflected by the receiver 30 is re-reflected on the driver 10 side without inserting a termination resistor. Can be avoided. In addition, since the through current at the time of signal transition has an addition of 100Ω of on-resistance of pMOS and nMOS, it is almost negligible, so insertion of a constant current transistor can be eliminated. In the I / O circuit 1 of the present invention, the circuit configuration is simplified, and the on-resistance value (for example, 50Ω) of the MOS transistor is compared with the on-resistance value (for example, 1 to 5Ω) of the conventional circuit. One digit higher. As a result, according to the I / O circuit 1 of the present invention, the power consumption during signal transmission can be reduced to 1/2 or less in principle.

Furthermore, compared with the conventional circuit, in the I / O circuit 1 of the present invention, the amplitude of the signal propagating through the pair transmission line 20 is Vdd due to Ohm's law of the on-resistance of the characteristic impedance MOS transistor of the pair transmission line 20. However, when the signal is almost totally reflected on the receiver side, the amplitude of the signal propagating through the pair transmission line 20 becomes an amplitude close to Vdd. As a result, there is no need to provide a circuit for recovering the waveform of the signal propagating through the pair transmission line 20 on the receiver 30 side. Therefore, the receiver 30 can be configured with a small transistor, and as a result, power consumption is reduced.

In the above example, a preferred example in which the characteristic impedance of the pair transmission line 20 is 100Ω has been described, but the characteristic impedance of the pair transmission line 20 is not limited to this. The characteristic impedance of the pair transmission line 20 can be arbitrarily set within a range of 20Ω to 150Ω, for example. In particular, the characteristic impedance of the pair transmission line 20 is preferably 50Ω to 150Ω, 75Ω to 150Ω, or 100Ω to 150Ω. Specifically, the characteristic impedance of the pair transmission line 20 is preferably selected from 75Ω, 100Ω, 125Ω, or 150Ω.

Here, assuming that the rising time of the driver side pulse is tr, the transmission and reception electromagnetic wave traveling time tpd of the internal circuit or the inter-repeater circuit is, for example, a clock of 28 Gbps when the wiring length is such that tr ≦ 7 tpd. The period tc is 71 ps, and is in the vicinity of tr = 0.33 × tc = 23 ps. Therefore, tpd = 3.3 ps. When the relative dielectric constant k or εr of the peripheral insulator of the chip wiring is 4, the wiring length corresponding to 3.3 ps is 500 μm. Similarly, it becomes 1.4 mm at 10 Gbps. This range is a condition where the amplitude reaches Vdd while the signal repeats multiple reflections 3.5 times or more for reciprocation (to be regarded as arrival from the transmitting end to the receiving end). Designed in consideration of such conditions. That is, when designing a circuit with IP, the designer does not need to be aware of the line characteristics.

On the other hand, the present invention defines a line structure that connects the transmission side and the reception side of a long wiring with respect to the length of the line under the condition of tr ≧ 7 tpd, that is, between them. In other words, the present invention provides a means for preventing the multiple reflection when it becomes a noise having a time longer than the tr time in a state where the impedances of the transmission side and the reception side are mismatched. Specifically, the present invention provides a means for preventing multiple reflections in a state where a commonly used receiving end terminating resistor and transmitting end terminating resistor are not inserted as means for preventing noise. is there. As a result, the present invention exhibits the effect that the transistor size on the transmission side and the reception side can be reduced and the power consumption can be suppressed. According to the present invention, the length of the wiring can be applied up to a length in which the signal attenuation becomes 1/3 as an amplitude.

Note that the present invention does not exclude a form in which a waveform recovery function is added to the receiving end circuit. For example, when the signal amplitude deteriorates to 1/3 or less, the waveform recovery function can be added to the receiving end circuit in the present invention as well. However, such a configuration has a drawback of increasing the power of the waveform recovery circuit. For example, when an equalizer such as pre-emphasis or de-emphasis is inserted into the sending end circuit, this form has a great effect.

[2-2. ESD countermeasures for differential I / O circuit]
FIG. 3 is a schematic configuration diagram showing another example of the differential type I / O circuit according to the present invention. FIG. 3 shows an example in which resistors 41, 42, 43, and 44 for ESD countermeasures are inserted in the differential I / O circuit 1.

As shown in FIG. 3, the I / O circuit 1 has resistors 41 to 44 each having a resistance value of 500Ω or more on the external connection side of the driver 10 and the receiver 30. Specifically, the first resistor 41 is inserted on the external connection side of the driver 10 in the first line 21 and is connected to the power source and the ground. The second resistor 42 is inserted on the external connection side of the driver 10 in the second line 22 and is connected to the power source and the ground. On the other hand, the third resistor 43 is inserted on the external connection side of the receiver 30 in the first line 21 and connected to the power source and the ground. The fourth resistor 44 is inserted on the external connection side of the receiver 30 in the second line 22 and is connected to the power source and the ground.

As described above, ESD can be avoided by providing resistors 41 to 44 having large resistance values of 500Ω or more on the driver 10 side and the receiver 30 side, respectively. That is, particularly in a high-speed I / O circuit such as a differential method, a clamp diode is generally inserted as an ESD countermeasure. However, since the clamp diode has a large capacitance component, it is difficult to obtain a perfect matching termination resistance value. In addition, the capacity of the clamp diode is a major obstacle to high-speed operation. Therefore, in the I / O circuit of the present invention, by inserting the resistors 41 to 44 having relatively large resistance values on the power supply side and the ground side, ESD can be appropriately eliminated while eliminating the clamp diode. .

Here, the resistance values of the resistors 41 to 44 are defined as “Resd”. In this case, in the differential I / O circuit 1, the characteristic impedance (Z0) of the pair transmission line 20, the on-resistance values (Ron) of the nMOS transistors 11a and 12a and the pMOS transistors 11b and 12b, and the resistors 41 The resistance values (Resd) of .about.44 preferably satisfy the following relationship (1).
2 / Z0 = (1 / Ron) + (1 / Resd) (1)

However, the value of “(1 / Ron) + (1 / Resd)” may be within a range of ± 30% of the specified value of “2 / Z0”. In particular, the value of “(1 / Ron) + (1 / Resd)” is preferably within a range of ± 10% with respect to the specified value (2 / Z0), and particularly preferably ± 5%. Preferably, it is ideal to be within a range of ± 1%.

Here, an appropriate value of the resistance value (Resd) of each of the resistors 41 to 44 will be described in principle. The internal resistance of the human body is basically at a level of 500Ω, but varies depending on the dry state of the skin and is generally several kΩ to 100 kΩ when the contact resistance is included. However, when wearing ordinary shoes, the resistance value with respect to GND is 1 M to 10 MΩ. At the time of discharging the electric charge accumulated in the human body, the release of the opposite carrier becomes a shoe corresponding to insulation, but since the instantaneous surge (dv / dt) is large, it is released by a displacement current due to the capacity of the shoe sole and GND. Therefore, the equivalent contact human body impedance is at a level of 100 k to 1 MΩ. Accordingly, it is appropriate to set the resistance values (Resd) of the resistors 41 to 44 to 500Ω to 2 kΩ, which is about 1/200 to 1/50 of 100 kΩ, which is the lowest impedance of the human body. For example, when the resistance value (Resd) of each of the resistors 41 to 44 is 2 kΩ, the resistance is 40 times that of the MOS transistor on-resistance (Ron: 50Ω). As described above, the resistance value (Resd) of each of the resistors 41 to 44 has a large value compared to the on-resistance (Ron) of the MOS transistor, so that the signal waveform propagated through the pair transmission line 20 is almost affected. You do n’t have to. Accordingly, the resistance value (Resd) of each of the resistors 41 to 44 is preferably in the range of 500Ω to 2 kΩ, and particularly preferably in the range of 1 kΩ to 2 kΩ.

[2-3. On-resistance adjusting means of differential I / O circuit]
FIG. 4 is a schematic configuration diagram showing another example of the differential type I / O circuit according to the present invention. FIG. 4 shows an example in which a resistance adjustment means 50 for adjusting the on-resistance values (Ron) of the MOS transistors 11a, 11b, 12a, and 12b of the driver 10 is provided in the differential I / O circuit 1. Yes.

As described above, the differential CMOS driver 10 includes a normal phase CMOS inverter 11 and a reverse phase CMOS inverter 12. The positive phase CMOS inverter 11 includes an nMOS transistor 11a and a pMOS transistor 11b, and the negative phase CMOS inverter 12 includes an nMOS transistor 12a and a pMOS transistor 12b. In addition, the ON resistance values (Ron) of the MOS transistors 11a, 11b, 12a, and 12b are set to substantially equal values in principle. For example, if the characteristic impedance (Z0) of the pair transmission line 20 is 100Ω, the on-resistance value (Ron) of the MOS transistor is set to 50Ω for each of the pMOS and nMOS.

Here, in the embodiment shown in FIG. 4, resistance adjustment is performed on at least the nMOS transistor 11a and the pMOS transistor 12b, which are located on the power supply side and serve as pull-up elements, of the positive phase CMOS inverter 11 and the reverse phase CMOS inverter 12. Means 50 are provided. For example, as shown in FIG. 4, the resistance adjusting means 50 can be configured by a resistance adjusting transistor and a power supply system (Vadjust) for applying a voltage to the transistor. The power supply system (Vadjust) is preferably capable of freely adjusting the voltage applied to the transistor.

In this case, the nMOS transistor 11a and the pMOS transistor 12b located on the power supply side have an on-resistance value (Ron) that is a prescribed value (1/2 · Z0) that is ½ of the characteristic impedance (Z0) of the pair transmission line 20. Can be set lower. For example, if the characteristic impedance (Z0) of the pair transmission line 20 is 100Ω, the on-resistance value (Ron) of the nMOS transistor 11a and the pMOS transistor 12b located on the power source side of the driver 10 is set to about 35 to 45Ω. Keep it. That is, the on-resistance value (Ron) of the MOS transistor is set low to about 70% to 90% of the specified value (1/2 · Z0). The resistance adjustment means 50 compensates for the resistance value (Ron) of the nMOS transistor 11a and the pMOS transistor 12b that is lower than the specified value (1/2 · Z0) (eg, 5 to 15Ω). That is, the voltage applied to the transistor from the power supply system (Vadjust) may be finely adjusted so that the resistance values (Ron) of the nMOS transistor 11a and the pMOS transistor 12b coincide with the specified value (1/2 · Z0). As a result, even if it is difficult to adjust the on-resistance of the MOS transistor of the driver 10, the on-resistance value can be matched with the specified value.

Further, as shown in FIG. 4, the resistance adjusting means 50 is provided in the pMOS transistor 11b and the nMOS transistor 12a which are located on the ground side and serve as pull-down elements, out of the positive phase CMOS inverter 11 and the negative phase CMOS inverter 12. It is good. The resistance adjusting means 50 here can be constituted by a resistance adjusting transistor and a power supply system (Vadjust) for applying a voltage to the transistor, as described above.

In this case, the pMOS transistor 11b and the nMOS transistor 12a located on the ground side have an on-resistance value (Ron) of a specified value (1/2 · Z0) that is ½ of the characteristic impedance (Z0) of the pair transmission line 20. Can be set lower. For example, if the characteristic impedance (Z0) of the pair transmission line 20 is 100Ω, the on-resistance value (Ron) of the pMOS transistor 11b and the nMOS transistor 12a located on the ground side of the driver 10 is set to about 35 to 45Ω. Keep it. That is, the on-resistance value (Ron) of the MOS transistor is set low to about 70% to 90% of the specified value (1/2 · Z0). The resistance adjusting means 50 compensates for the resistance value (Ron) of the pMOS transistor 11b and the nMOS transistor 12a that is lower than the specified value (1/2 · Z0) (for example, 5 to 15Ω). That is, the voltage applied to the transistor from the power supply system (Vadjust) may be finely adjusted so that the resistance value (Ron) of the pMOS transistor 11b and the nMOS transistor 12a matches the specified value (1/2 · Z0).

Although not shown, as an improved version of the I / O circuit 1 shown in FIG. 4, it may further include characteristic impedance measuring means, on-resistance measuring means, and voltage control means.
The characteristic impedance measuring means is connected to the pair transmission line 20 and measures the characteristic impedance (Z0) of the pair transmission line 20. That is, the characteristic impedance measuring means is connected to each of the first line 21 and the second line 22 of the pair transmission line 20. The characteristic impedance measuring means may measure the characteristic impedance periodically or may constantly measure the characteristic impedance. The characteristic impedance measured by the characteristic impedance measuring means is sent to the voltage control means.
The on-resistance measuring means measures the on-resistance values (Ron) of the MOS transistors 11a, 11b, 12a, and 12b constituting the differential CMOS driver 10. The on-resistance measuring means may periodically measure the on-resistance value or may constantly measure the on-resistance value. The on-resistance value measured by the on-resistance measuring means is sent to the voltage control means.
Based on the characteristic impedance (Z0) received from the characteristic impedance measuring means and the on-resistance value (Ron) received from the on-resistance measuring means, the voltage control means has an on-resistance value (Ron) of a specified value (1/2 · It is determined whether or not it matches Z0). When the voltage control means determines that the on-resistance value (Ron) is lower than the specified value (1/2 · Z0), the resistance value (Ron) matches the specified value (1/2 · Z0) The power supply system (Vadjust) of the resistance adjusting means 50 is controlled. That is, the voltage control means receives the feedback from the characteristic impedance measurement means and the on-resistance measurement means, and controls the voltage applied to the transistor by the power supply system (Vadjust) of the resistance adjustment means 50. As a result, the on-resistance value (Ron) of each MOS transistor can be appropriately matched to the specified value (1/2 · Z0).

[3. Single-ended I / O circuit]
[3-1. Basic form of single-ended I / O circuit]
Next, an example in which the knowledge based on the differential I / O circuit 1 is applied to a single-ended I / O circuit will be described.
FIG. 5 is a schematic configuration diagram illustrating an example of an input / output interface circuit (I / O circuit) 1 according to another embodiment. In this embodiment, the I / O circuit 100 is configured to operate in a single-ended manner. In the single-ended method, a transmission line as a signal line and a ground line are paired, and information on whether the level of a signal propagating through the transmission line is higher or lower than a certain threshold is transmitted based on the potential of the ground line. To do.

As shown in FIG. 5, a single-ended I / O circuit 100 includes a driver 110 that outputs a digital signal, a transmission line 120 that transmits the digital signal, a ground line 123 that forms a pair with the transmission line 120, And a receiver 130 for detecting a digital signal. Specifically, the driver 110 is a CMOS type driver, and the receiver is a CMOS type receiver. Further, the transmission path 120 is electrically connected so that signals can be transmitted and received between the driver 110 and the receiver 130. The ground line 123 is connected to the ground side of the driver 110 and the receiver 130.

A digital signal (S) to be transmitted to the receiver 130 is input to the driver 110. Upon receiving the digital signal (S), the driver 110 outputs it as an output signal (Q) having a level higher or lower than a predetermined threshold. The receiver 130 receives the output signal (Q) via the transmission path 120 and compares the output signal (Q) with the ground level of the ground line 123 to detect a received signal corresponding to the digital signal (S). As shown in FIG. 5, the driver 110 includes an nMOS transistor 111a and a pMOS transistor 111b. The receiver 130 includes an nMOS transistor 131a and a pMOS transistor 131b corresponding to the driver 110. Further, the transmission line 120 has a predetermined characteristic impedance.

Here, the single-ended I / O circuit 100 according to the present embodiment can have a simple circuit configuration that does not require a termination resistor, as shown in FIG. Therefore, in the I / O circuit 100 of the present embodiment, the on-resistance values (Ron) of the nMOS transistor 111a and the pMOS transistor 111b included in the driver 110 are defined to be equal to the characteristic impedance (Z0) of the transmission line 120, respectively. Match the value substantially. In the present embodiment relating to the single end system, the “specified value” means a value equal to the characteristic impedance of the transmission line 120. For example, in the single-ended I / O circuit 100, the characteristic impedance of the transmission line 120 is often set to 50Ω. Therefore, when the characteristic impedance of the transmission line 120 is 50Ω, the on-resistance values of the nMOS transistor 111a and the pMOS transistor 111b included in the driver 110 are set to 50Ω, respectively. In other words, when the on-resistance value of the nMOS transistor 111a and the pMOS transistor 111b (MOS transistor) is “Ron” and the characteristic impedance of the transmission line 120 is “Z0”, it is ideal that the relationship of Z0 = Ron is satisfied.

However, it is sufficient that the on-resistance value (Ron) of the MOS transistor substantially matches the specified value equal to the characteristic impedance (Z0) of the transmission line 120. For example, the on-resistance (Ron) of the MOS transistor may be matched within a range of ± 30% with respect to the specified value (Z0). However, the on-resistance (Ron) of the MOS transistor is preferably within a range of ± 10% with respect to the specified value (Z0), particularly preferably ± 5%, and within a range of ± 1%. It is ideal to be.

As described above, the signal energy reflected by the receiver 130 can be absorbed by the driver 110 by matching the on-resistance values of the MOS transistors constituting the driver 110 with the characteristic impedance of the transmission line 120.

[3-2. ESD measures for single-ended I / O circuit]
FIG. 6 is a schematic configuration diagram illustrating another example of a single-ended I / O circuit. FIG. 6 shows an example in which resistors 141 and 143 for ESD countermeasures are inserted into the single-ended I / O circuit 100.

As shown in FIG. 6, the I / O circuit 100 has resistors 141 and 143 having resistance values of 500Ω or more on the external connection side of the driver 110 and the receiver 130, respectively. More specifically, the driver-side resistor 141 is inserted in the transmission line 120 on the external connection side of the driver 110, and is connected to the power source and the ground. The resistor 143 on the receiver side is inserted in the transmission line 120 on the external connection side of the receiver 130, and is connected to the power source and the ground. In this way, ESD can be avoided by providing the resistors 141 and 143 having large resistance values of 500Ω or more on the driver 110 side and the receiver 130 side, respectively.

Here, the resistance values of the resistors 141 and 143 are defined as “Resd”. In this case, in the single-ended I / O circuit 100, the characteristic impedance (Z0) of the transmission line 120, the on-resistance value (Ron) of the nMOS transistor 111a and the pMOS transistor 111b, and the resistance values of the resistors 141 and 143 (Resd) preferably satisfies the following relationship (2).
1 / Z0 = (1 / Ron) + (1 / Resd) (2)

However, the value of “(1 / Ron) + (1 / Resd)” may be within a range of ± 30% of the specified value of “1 / Z0”. In particular, the value of “(1 / Ron) + (1 / Resd)” is preferably within a range of ± 10% with respect to the specified value (1 / Z0), and particularly preferably ± 5%. Preferably, it is ideal to be within a range of ± 1%.

[3-3. On-resistance adjustment means for single-ended I / O circuit]
FIG. 7 is a schematic configuration diagram showing another example of a single-ended I / O circuit. FIG. 7 shows an example in which the single-end I / O circuit 100 is provided with resistance adjusting means 150 for adjusting the on-resistance values (Ron) of the MOS transistors 111a and 111b of the driver 10.

Here, in the embodiment shown in FIG. 7, the resistance adjusting means 150 is provided at least in the nMOS transistor 111a located on the power supply side and forming a pull-up element. The resistance adjusting means 150 can be constituted by a resistance adjusting transistor and a power supply system (Vadjust) for applying a voltage to the transistor. The power supply system (Vadjust) is preferably capable of freely adjusting the voltage applied to the transistor. In this case, the on-resistance value (Ron) of the nMOS transistor 111a located on the power supply side can be set lower than a specified value equal to the characteristic impedance (Z0) of the transmission line 120. For example, if the characteristic impedance (Z0) of the transmission line 120 is 50Ω, the on-resistance value (Ron) of the nMOS transistor 111a is set to about 35 to 45Ω. The resistance adjustment means 150 compensates for the resistance value (Ron) of the nMOS transistor 111a that is lower than the specified value (Z0) (eg, 5 to 15Ω). That is, the voltage applied to the transistor from the power supply system (Vadjust) may be finely adjusted so that the resistance value (Ron) of the nMOS transistor 111a matches the specified value (Z0). As a result, even if it is difficult to adjust the on-resistance of the nMOS transistor 111a of the driver 110, the on-resistance value can be matched with the specified value.

Also, the same resistance adjusting means 150 can be provided in the pMOS transistor 111b which is located on the ground side and forms a pull-down element.

Although not shown, as an improved version of the I / O circuit 100 shown in FIG. 7, it may further include characteristic impedance measurement means, on-resistance measurement means, and voltage control means. The characteristic impedance measuring means is connected to the transmission line 120 and measures the characteristic impedance (Z0) of the transmission line 120. The on-resistance measuring unit measures the on-resistance values (Ron) of the MOS transistors 111a and 111b constituting the driver 110. Based on the characteristic impedance (Z0) received from the characteristic impedance measuring means and the on-resistance value (Ron) received from the on-resistance measuring means, the voltage control means sets the on-resistance value (Ron) to the specified value (Z0). Determine whether you are doing it. When it is determined that the on-resistance value (Ron) is lower than the specified value (Z0), the voltage control unit determines that the resistance value (Ron) matches the specified value (Z0). Vadjust).

[3-4. Modification of single-ended I / O circuit]
FIG. 8 shows a modification of the single-ended I / O circuit. FIG. 8A is a schematic configuration diagram of a single-ended I / O circuit 100, and FIG. 8B shows a waveform of an output signal propagating through the transmission line 120. FIG.

In the modification shown in FIG. 8A, the single-ended I / O circuit 100 is provided with a differentiation circuit for performing pre-emphasis. Reference numerals Q1, Q2, Q3, and Q4 denote transistors. The transistors Q1, Q2, Q3, and Q4 all have an on-resistance (Ron) that is twice the characteristic impedance (Z0) of the transmission line 120. Here, the transistor Q3 and the transistor Q4 constitute a differentiation circuit. In the I / O circuit 100 of FIG. 8, when the transistor Q1 is ON, it is ON only for the transition time of the transistor Q3, resulting in a parallel resistance, resulting in an effective on-resistance of 100Ω. Also for the transistor Q2, the transistor Q4 functions in the same way, and either the transistor Q3 or the transistor Q4 constituting the differentiation circuit is ON, so that the matching absorption is performed even if the reflected wave returns. On the other hand, when the differentiation circuit (Q3, Q4) is not ON (when it is OFF), it can be said that the signal waveform is flat. There is no.

FIG. 8 (b) shows a typical output signal waveform of the I / O circuit 100 shown in FIG. 8 (a). As shown in FIG. 8B, the reflected wave is absorbed near the peak value, and the initial waveform of the driver is protected. On the other hand, in the flat portion of the signal, both the transistor Q3 and the transistor Q4 constituting the differentiation circuit are OFF. Therefore, in the flat time of the signal, a half of the amplitude of the reflected wave is re-reflected and superimposed on the signal (a quarter amplitude in view of the transmission signal). However, when both the transistor Q3 and the transistor Q4 are OFF, as shown by the dotted line in FIG. 8B, the signal level only changes gently, and the reception sensitivity on the receiver side should not be affected much. I can say that.

Example 1 relates to the differential type I / O circuit 1 shown in FIG. First, the I / O circuit 1 was configured based on the design shown in FIG. The characteristic impedance of the pair transmission line 20 is set to 100Ω in terms of design theory. The characteristics of the driver 10 and the receiver 30 are as shown in [Table 1] below.

The differential I / O circuit 1 constructed based on the above design was operated. In this I / O circuit 1, the waveforms of the complementary signals detected by the receiver 30 are shown for each operation speed of the driver 10 as shown in FIG. As shown in FIG. 9, even when the driver 10 was operated at 25 Gbps, it was confirmed that the waveform of the complementary signal was not distorted and the eye pattern was firmly opened. Therefore, even when the driver 10 is operated at 25 Gbps, it can be said that the complementary signal can be properly detected by the receiver 30. Thus, in Example 1, it was confirmed that the operation was possible up to 25 Gbps. This is a performance that exceeds the simulation limit of 15 Gbps. As described above, according to the differential type I / O circuit 1 of the present invention, a high-speed signal having a clock frequency of 15 Gbps or more can be transmitted.

In addition, the current of the CR type driver (CR-DRV, carrier reuse color: literature USP 6,731,153 and USP 7,280.385) and the REF type driver (REF-DVR, CMOS with a normal layout) As a result of examination, it was as shown in FIG. As shown in FIG. 10, the current values of two structurally different drivers are both smaller than the designed value of 8 mA. Although the receiver has not been measured with the three-stage inverter specification, it is estimated that it is at the design value level because the predicted design value of the driver matches the actual measurement.

The second embodiment relates to the differential type I / O circuit 1 in which the resistance against ESD shown in FIG. 3 is inserted.
FIG. 11 is a drawing which serves as both a differential CMOS driver and a differential CMOS receiver. As shown in FIG. 11, an input signal is input from a pair transmission line matched with a characteristic impedance of 100Ω, and a Resd diffused resistor 2 kΩ is connected to the ground for each signal. The pair transmission lines are input to the gates of the respective nMOSs arranged in two differential upper and lower rows while maintaining the parallel shape. For example, in a 0.18 μm process, each source is connected to the ground of a 20 μm wide power source / ground pair line descending vertically while being aligned with a total width of 40 μm with a gate width of 5 μm. The line is directly connected to the gates of 80 μm wide pMOS arranged in two upper and lower rows, and the end of the line is open. The source of each pMOS is connected to the power supply line that has come down vertically. The output is connected laterally from the drains of the respective nMOS and pMOS, that is, is pulled out to the right side while maintaining the line structure, and becomes a transmission line having a characteristic impedance of 100Ω from the position away from the pMOS. Similarly, this transmission line is connected to an ESD diffusion resistor and then led out of the LSI chip. Thus, FIG. 11 shows the concept of the receiver viewed from the input side and the driver viewed from the output side, corresponding to the configuration diagram of the I / O circuit shown in FIG. As the gate width of the receiver, drivability corresponding to the level of the next circuit (generally an internal circuit) only needs to be secured, so 5 μm is sufficient, and a small receiver may be used. Further, when driving a global wiring such as a 3D chip component module, it may be appropriately adjusted according to the purpose. The above dimensions are merely examples, and the on-resistance of the nMOS transistor and the pMOS transistor can be set to 100Ω, for example.

In the example shown in FIG. 11, the nMOS and the pMOS are arranged in a horizontal line, but the nMOS and the pMOS may be arranged vertically. The nMOS and the pMOS itself can be arranged in two upper and lower stages or three upper and lower stages. With such a short distance, the delay time of the line can be ignored with respect to the clock. Therefore, by arranging the nMOS and pMOS in upper and lower rows, there is an advantage that the DC resistance is lowered for two reasons: the wiring branches and the wiring becomes shorter.

Example 3 relates to a multi-layer structure in a chip of a differential I / O circuit.
As shown in FIG. 12, the I / O circuit of the third embodiment has a line configuration in which the metal layers of the multi-layer structure in the chip are formed in a multi-layer structure with the same pattern and appropriately connected in columns in order to reduce the wiring resistance. It is characterized by that. In addition, as long as the power supply / ground is allowed to have a layer structure, the power supply / ground can have a multilayer structure in which power supplies and grounds are alternately stacked.

Fig. 13 shows an example of the layer structure of the 45 nm process regarding the wiring in the chip. FIG. 13 shows an example of the IBM Power 7 processor top. M1 to M3 are used for forming an internal circuit, and M4 to M5 are used for somewhat longer wiring among them (such as memory LAS and CAS, and logic inter-cache wiring). Also, M4 to M8 are used for the I / O differential signal of the present invention, and M7 to M11 are used for power distribution and clock distribution.

Since the I / O circuit is near the chip pad and the occupied area of the I / O wiring is small, the internal circuit wiring area can be secured. The most important wiring is the power wiring. Wide wiring is recommended to reduce the characteristic impedance. The power supply wiring can be made thinner by alternately layering the power supply and the ground.

The transmission path from the driver to the receiver may be within the chip, between the chips via the interposer, or the distance that can connect the package and the substrate wiring, and the signal attenuation is ensured to a level of -10 dB (1/3). Any transmission line having a characteristic impedance of the above may be used. The signal amplitude at this time is 2/3 because it is totally reflected by the receiver, and sufficiently exceeds Vth of 1/2.

As mentioned above, in this specification, in order to express the content of the present invention, the embodiment of the present invention was described with reference to the drawings. However, the present invention is not limited to the above-described embodiments, but includes modifications and improvements obvious to those skilled in the art based on the matters described in the present specification.

The present invention relates to an input / output interface circuit. Therefore, the present invention can be widely used in computer related industries.

1 ... I / O circuit (differential system)
DESCRIPTION OF SYMBOLS 10 ... Driver 11 ... Positive phase CMOS inverter 12 ... Reverse phase CMOS inverter 11a ... nMOS transistor 12a ... nMOS transistor 11b ... pMOS transistor 12b ... pMOS transistor 20 ... Pair transmission line 21 ... First line 22 ... Second line 23 ... Ground line 30 ... Receiver 31 ... Positive phase CMOS inverter 32 ... Reverse phase CMOS inverter 31a ... nMOS transistor 32a ... nMOS transistor 31b ... pMOS transistor 32b ... pMOS transistor 41-44 ... 1st-4th resistance 50 ... Resistance adjustment means 100 ... I / O circuit (single-ended system)
DESCRIPTION OF SYMBOLS 110 ... Driver 111 ... CMOS inverter 111a ... nMOS transistor 111b ... pMOS transistor 120 ... Transmission path 123 ... Ground line 130 ... Receiver 131 ... CMOS inverter 131a ... nMOS transistor 131b ... pMOS transistor 141, 143 ... Resistance 150 ... Resistance adjustment means

Claims (6)

1. A driver (10) for outputting a complementary signal corresponding to the input signal;
   A pair transmission line (20) having a first line (21) and a second line (22) for transmitting the complementary signal output from the driver (10);
   A differential input / output interface circuit comprising: a receiver (30) to which the complementary signal transmitted through the pair transmission line (20) is input;
   The driver (10)
   A positive phase CMOS inverter (11) for supplying a positive phase signal in phase with the input signal to the first line (21);
   A negative phase CMOS inverter (12) for supplying a negative phase signal opposite to the input signal to the second line (22), the positive phase CMOS inverter (11) and the negative phase CMOS inverter (12) Are configured to include nMOS transistors (11a, 12a) and pMOS transistors (11b, 12b), respectively.
   The on-resistance values of the nMOS transistors (11a, 12a) and the pMOS transistors (11b, 12b) are equal to a prescribed value that is 1/2 of the characteristic impedance of the pair transmission line (20) or the prescribed value. I / O interface circuit that is matched within ± 30% of the range.
2. 2. The input / output interface circuit according to claim 1, wherein a termination resistor having a resistance value of less than 500Ω for preventing reflection of signal energy is not provided on the driver (10) side and the receiver (30) side.
3. The receiver (30)
   A positive phase CMOS inverter (31) to which the positive phase signal transmitted through the first line (21) is input;
   The input / output interface circuit according to claim 1, further comprising: a reverse phase CMOS inverter (32) to which the reverse phase signal transmitted through the second line (22) is input.
4. The resistors (41, 42, 43, 44) having a resistance value of 500Ω or more are connected to the power supply side and the ground side on the external connection side of the driver (10) and the receiver (30), respectively. The input / output interface circuit according to claim 3.
5. The on-resistance value is set lower than the specified value,
   The resistance adjusting means (50) capable of making at least one ON resistance value of the nMOS transistor (11a, 12a) and the pMOS transistor (11b, 12b) coincide with the specified value. The input / output interface circuit according to claim 4.
6. A driver (110) for outputting a signal;
   A transmission line (120) for transmitting the signal output from the driver (110);
   A single-ended input / output interface circuit comprising a receiver (130) to which the signal transmitted through the transmission path (120) is input;
   The driver (110) includes a CMOS inverter (111) that supplies the signal to the transmission line (120). The CMOS inverter (111) includes an nMOS transistor (111a) and a pMOS transistor (111b). ,
   The on-resistance values of the nMOS transistor (111a) and the pMOS transistor (111b) are equal to a specified value equal to the characteristic impedance of the transmission line (120) or matched within a range of ± 30% of the specified value. I / O interface circuit.

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