JPH10242835A - Output circuit, semiconductor integrated circuit and electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip area of the output circuit having a slew rate control function and an impedance matching function. SOLUTION: An impedance matching circuit is configured by including a series connection of a 1st transistor(TR) 11 (13, 15) and a 2nd TR 12 (14, 16), a 1st conduction type 3rd TR 19 placed between the series connection circuits and an external terminal 24-1 and a 2nd conduction type 4th TR 20 connected in parallel with the 3rd TR 19. The impedance with a transmission line matches by a parallel combined impedance by the 1st conduction type 3rd TR and the 2nd conduction type 4th TR, the layout area is reduced by reducing a gate width of each TR being a component of the impedance matching circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an impedance matching circuit technology for matching an impedance with a transmission line and a semiconductor integrated circuit including such an impedance matching circuit, for example, a plurality of LSIs (semiconductor integrated circuits). The present invention relates to a technology that is effective when applied to an electronic circuit device that is coupled to each other via a transmission line having a predetermined characteristic impedance and that performs data transfer via the transmission line.

[0002]

2. Description of the Related Art In an electronic circuit device, for example, an electronic circuit device in which a plurality of LSIs are mounted on a printed circuit board, when data transfer between the plurality of LSIs is performed at high speed,
In order to suppress signal reflection, impedance matching of a data transmission system becomes important. For example, if the characteristic impedance of a transmission line for exchanging data between a plurality of LSIs is set to 50Ω, a 50Ω termination resistor is added to such a transmission line to suppress signal reflection.

[0003] In addition to the case where a predetermined terminating resistor such as 50Ω is added, the on-resistance of a transistor may be used for impedance matching. If impedance matching can be achieved using the on-resistance of the transistor, the terminating resistor is not required. The output impedance is
It can be changed by adjusting the gate width of the transistor.

As an example of a document describing impedance matching, a “Digitally Adjustable Resistor” is disclosed.
s in CMOS for High-Performance Applications, ”IEEE
J. Solid-State Circuits, vol. 27, no. 8, pp. 1176-1185, A
ug.1992.

[0005]

In an internal circuit of an LSI, in particular, in an output circuit for outputting a signal to a transmission line based on a signal to be output, a sudden change in the amount of current causes a change in power supply voltage. It becomes power supply noise and hinders circuit operation. In order to reduce power supply noise, it is only necessary to mitigate a sudden change in the amount of current.In an output circuit for outputting a signal to a transmission line, a slew rate control function to mitigate a sudden change in the amount of current is provided. Will be installed. The slew rate control function is realized by, for example, connecting a plurality of transistors forming an output circuit in parallel and slightly shifting the timing at which the plurality of transistors are turned on. This is because such a slight shift in the timing at which the plurality of transistors are turned on can alleviate a sudden change in the current flowing through the output circuit.

However, since it is not possible to achieve impedance matching with a transmission line using such a transistor for slew rate control, it is necessary to realize a slew rate function in order to realize both a slew rate function and impedance matching. It is necessary to provide a transistor for impedance matching separately from the transistor for the impedance. For example, by connecting a MOS transistor for controlling the slew rate and a transistor for adjusting the impedance in series, it is possible to realize both the slew rate function and the impedance matching function. Thus, since it is necessary to separately provide a transistor for impedance matching and a transistor for slew rate control, an output circuit having both a slew rate control function and an impedance matching function has an impedance matching function. Causes an increase in the area occupied by the chip as compared with a circuit having no circuit.

An object of the present invention is to reduce the chip occupation area of an output circuit having a slew rate control function and an impedance matching function. Another object of the present invention is to provide a semiconductor integrated circuit including such an output circuit and an electronic circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the first transistor (11, 1
3, 15) and a second transistor (12, 14, 16) connected in series thereto, and a current flowing through a path including the external terminal (24-1) is stepwise changed by a logical change of data to be output. Slew rate circuit (3
5) and an impedance matching circuit (3) for matching the output impedance with the characteristic impedance of the transmission line.
4), the third transistor of the first conductivity type provided between the serial connection point of the first transistor and the second transistor and the external terminal when the output circuit (33) is formed. (19) and a fourth transistor (20) of the second conductivity type connected in parallel to the impedance matching circuit.

According to the above-mentioned means, since the impedance matching with the transmission line is achieved by the parallel connection circuit of the third transistor and the fourth transistor connected in parallel to the third transistor, the high-level output and the low-level output In both cases, both the third transistor and the fourth transistor are simultaneously involved in impedance matching. Since the output impedance is matched by the parallel combined impedance of the third transistor and the fourth transistor, when a transistor for impedance matching at the time of high-level output and a transistor for impedance matching at the time of low-level output are separately provided. The gate width can be reduced as compared with the above, which achieves a reduction in the chip occupation area of the output circuit having the slew rate control function and the impedance matching function.

Further, the impedance matching circuit is a p-channel MOS transistor (19) provided between the serial connection point of the first transistor and the second transistor and the external terminal, and is connected in parallel to the p-channel MOS transistor (19). In this case, the gate electrode of the p-channel MOS transistor is set to the ground potential level, and the gate electrode of the n-channel MOS transistor is set to a high level. It is set to the potential side power supply voltage level.

Further, the output circuit (33) having the above configuration,
A semiconductor integrated circuit (21) including an input circuit (32) for receiving external input data;
An electronic circuit device can be configured to include such a semiconductor integrated circuit.

[0014]

FIG. 3 shows an example of an electronic circuit device according to the present invention.

Although the electronic circuit device shown in FIG. 3 is not particularly limited, the LSI 2 mounted on one printed board
1 and 22 which are connected to each other via transmission lines 25-1 to 25-n so that signals can be exchanged with each other.
The transmission paths 25-1 to 25-n are set to a predetermined characteristic impedance.

Although not particularly limited, the LSI 21 is a central processing unit, and the LSI 22 is a semiconductor memory device accessed by the central processing unit. In order to enable high-speed data transfer between the central processing unit and the semiconductor storage device, impedance matching of a data transmission system is performed.

The LSI 21 has input / output buffers 23-1 to 23-1.
23-n, and the input / output buffers 23-1 to 23-
n are external terminals 24-1 for data input / output, respectively.
To the other ends of the transmission lines 25-1 to 25-n. The LSI 22 includes an input / output buffer 27
-1 to 27-n.
27-n are external terminals 2 for data input / output, respectively.
They are coupled to the other ends of the transmission lines 25-1 to 25-n via 6-1 to 26-n.

The input / output buffers 23-1 to 23-n,
Although 27-1 to 27-n are not particularly limited, they have basically the same configuration. Therefore, in the following description, only the input / output buffer 23-1 will be described in detail.

FIG. 1 representatively shows a configuration example of the input / output buffer 23-1.

As shown in FIG. 1, the input / output buffer 23-1 is connected to an output circuit 33 for outputting a signal to a transmission line via an external terminal 24-1 and transmitted to the output circuit 33 via the transmission line. And an input circuit 32 for receiving the input signal.

The output circuit 33 includes a slew rate control circuit 23 for preventing a sudden change in the amount of current, and a transfer gate 34 for matching impedance with the characteristic impedance of the transmission line.

The slew rate control circuit 23
Is a first inverter INV1 formed by connecting a p-channel MOS transistor 11 and an n-channel MOS transistor 12 in series, and a second inverter formed by connecting a p-channel MOS transistor 13 and an n-channel MOS transistor 14 in series. INV2, p-channel MOS transistor 15 and n-channel MO
The third transistor INV3 includes an S transistor 16 connected in series.

Each output terminal of the first inverter INV1, the second inverter INV2, and the third inverter INV3 is coupled to a transfer gate 34 at a subsequent stage.
The input data DATA to the output circuit 33 is input as it is to the first inverter INV1, but to the second inverter INV2 via the delay circuit 17 and to the subsequent third inverter INV3 via the delay circuit 18 further. Is entered. With the delay circuits 17 and 18 interposed in such a manner, the operations of the first inverter INV1, the second inverter INV2, and the third inverter INV3 are controlled by I
It is delayed in the order of NV1, INV2, INV3. Due to such an operation delay, the current flowing through the circuit at the time of logic switching in the output circuit 33 is increased stepwise as shown in FIG. 2, thereby suppressing a rapid change in the current.

The transfer gate 34 is provided to match the output impedance of the output circuit 33 with the characteristic impedance of the transmission line 25-1, and the p-channel MOS transistor 19 and the n-channel MOS transistor 20 are connected in parallel. Consisting of The gate electrode of the p-channel MOS transistor 19 is connected to the ground line, and the n-channel MOS transistor 2
The zero gate electrode is coupled to the high potential side power supply Vdd. p
By adjusting the gate width of the channel type MOS transistor 19 and the gate width of the n-channel type MOS transistor 20, the output impedance of the output circuit 33 is matched with the characteristic impedance of the transmission line.

Here, MOS transistors 15, 16, 19, and 20, which are main parts of the output circuit 33 shown in FIG.
And its layout will be compared with the output circuit shown in FIG.

The output circuit shown in FIG. 4 has a structure in which a transistor for controlling a slew rate and a transistor for adjusting impedance are vertically stacked, and includes p-channel MOS transistors 41 and 42 and an n-channel MOS transistor. Type MOS transistors 43 and 44 are connected in series. p-channel type MOS transistor 4
The 1 and n-channel MOS transistors 44 form a slew rate circuit 35 and correspond to the p-channel MOS transistor 15 and the n-channel MOS transistor 16 in FIG. 1, respectively. The p-channel type MOS transistors 42 and 43 have an impedance matching function, and the p-channel type MOS transistors 42 and 43 shown in FIG.
It corresponds to the transistor 19 and the n-channel MOS transistor 20, respectively. p-channel MOS transistor 42 and n-channel MOS transistor 4
3 is connected to a transmission line via an external terminal for external output of a signal. The output impedance is p
It can be adjusted by the gate width of the channel type MOS transistor 42 and the gate width of the n-channel type MOS transistor 43.

Now, in the circuit shown in FIG. 4, when the gate widths of the p-channel MOS transistors 41 and 42 are both set to 100 μm and the gate widths of the n-channel MOS transistors 43 and 44 are both set to 50 μm. It is assumed that a predetermined output impedance matching the characteristic impedance of the transmission path is realized.

The layout in that case is as shown in FIG. That is, p of a gate width of 100 μm
The channel type MOS transistor 41 has a gate width 20
The p-channel MOS transistor 42 having a gate width of 100 μm is formed by connecting five unit MOS transistors Q2 having a gate width of 20 μm in parallel. N-channel type M with a gate width of 50 μm
The OS transistor 43 has a unit MO having a gate width of 10 μm.
The n-channel MOS transistor 44 having a gate width of 50 μm is formed by connecting five unit MOS transistors Q4 having a gate width of 10 μm in parallel. Therefore, the length L1 of the layout area in that case is
It is about 60 μm.

On the other hand, the MOS transistors 15, 16, 19 and 20 in the circuit shown in FIG.
The gate width is set as shown in FIG. That is, the p-channel MOS transistor 15 and the n-channel MOS transistor 16 both have a gate width of 100 μm, and are equal to the p-channel MOS transistor 41 and the n-channel MOS transistor 44 shown in FIG. 4, respectively. , P-channel MOS transistor 19 and n-channel MOS
The transistor 20 has a gate width of 50
μm and 25 μm, respectively, the p-channel MOS transistor 42 and the n-channel
Impedance matching with the transmission path can be achieved with a gate width of of the OS transistor 43. It is for the following reasons.

In the circuit shown in FIG. 4, the impedance matching at the time of high level output is matched by the p-channel MOS transistor 42, and the impedance matching at the time of low level output is n-channel type M transistor.
The impedance is matched by the OS transistor 43. In other words, the p-channel type MOS transistor 42 and the n-channel type MOS transistor 43 are provided for separately performing impedance matching at the time of high-level output and at the time of low-level output.

On the other hand, in the circuit shown in FIG.
Since a parallel connection circuit of the p-channel MOS transistor 19 and the n-channel MOS transistor 20 is provided between the output terminals of the inverters INV1, INV2, and INV3 and the external terminal 24-1, a high-level output and a low-level output are provided. In each case, the p-channel type M
Both the OS transistor 19 and the n-channel MOS transistor 20 are involved in impedance matching at the same time. Therefore, in the circuit shown in FIG.
If a p-channel MOS transistor 42 of μm is required and an n-channel MOS transistor 43 with a gate width of 50 μm is required for impedance matching at the time of low level output, the circuit shown in FIGS. , P-channel MOS transistor 19 and n-channel MOS transistor 20 in a parallel circuit, the p-channel MOS transistor 19 and n-channel MOS transistor 2
Since the parallel combined impedance of 0 participates in impedance matching with the transmission line, the p-channel MOS transistor 19 and the n-channel MOS transistor 2
For 0, a gate width of ｐ of the p-channel MOS transistor 42 and the n-channel MOS transistor 43 in FIG. 4 is sufficient, and in this case, impedance matching with the transmission line can be achieved.

Therefore, in the output circuit 33 shown in FIG. 1, the layout of the MOS transistors 15, 16, 19 and 20 is as shown in FIG.
Assuming that the transistors are formed by connecting five unit MOS transistors in parallel, the result is as shown in FIG. That is, the p-channel MOS transistor 15 having a gate width of 100 μm has a gate width of 20 μm.
Is formed by connecting five unit MOS transistors Q5 in parallel. A p-channel type MOS transistor 19 having a gate width of 50 μm has a unit M having a gate width of 10 μm.
The n-channel MOS transistor 20 having a gate width of 25 μm is formed by connecting five unit MOS transistors Q7 having a gate width of 5 μm in parallel.
The n-channel MOS transistor 16 having a gate width of 50 μm is a unit MOS transistor Q having a gate width of 10 μm.
8 are formed by connecting five in parallel. Since the length L2 of the layout region in that case is approximately 45 μm, the length L1 of the layout region in the case of FIG.
= 15μm shorter than 60μm,
The chip occupation area of the layout area can be reduced.

FIGS. 7 and 8 show simulation results of impedance characteristics with respect to the output voltage of the output circuit.

In FIG. 7, a characteristic curve 71 is an impedance characteristic on the p-channel MOS transistor side of the circuit shown in FIG. 4, and a characteristic curve 72 is an impedance characteristic on the p-channel MOS transistor side of the circuit shown in FIG. It is. In FIG. 8, the characteristic curve 81
Is the impedance characteristic of the circuit shown in FIG. 4 on the n-channel MOS transistor side, and the characteristic curve 72 is the impedance characteristic of the circuit shown in FIG. 5 on the n-channel MOS transistor side. It is better that the variation in impedance is smaller than the variation in the level of the output voltage. The circuit shown in FIG. 5 has a smaller variation in impedance than the circuit shown in FIG. 4, and a good result is obtained.

According to the above example, the following functions and effects can be obtained.

(1) The location of the serial connection of the p-channel type MOS transistors 11, 13, 15 and the n-channel type MOS transistors 12, 14, 16 and the external terminal 24-1
, And an n-channel MOS transistor 20 connected in parallel with the p-channel MOS transistor 19 so as to achieve impedance matching with the transmission line. In any case, both the p-channel MOS transistor 19 and the n-channel MOS transistor 20 are simultaneously involved in impedance matching.
Therefore, the output impedance of the output circuit 33 is the p-channel type MOS transistor 19 and the n-channel type M transistor.
The p-channel MOS transistor 19 and the n-channel MOS transistor 20 are matched by the parallel combined impedance of the OS transistor 20, and the p-channel MOS transistor 19 and the n-channel MOS transistor 20 in FIG.
In addition, the gate width can be reduced to half of that of the n-channel MOS transistor 43, and the layout area can be reduced accordingly.

(2) In a semiconductor integrated circuit including the output circuit 33 having the operation and effect of the above (1), the output circuit 33
By reducing the layout area, the layout area of the input / output buffer can be reduced, and the chip size can be reduced. Further, by reducing the layout area of the output circuit 33, the number of input / output circuits can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, as in an endless GTL circuit, n
Even when only the channel type MOS transistor is used, the impedance can be matched by the parallel connection circuit of the p-channel type MOS transistor 19 and the n-channel type MOS transistor 20.

In the impedance matching, when it is desired to make the output impedance value different between the high level output and the low level output, a correction circuit for changing the output impedance based on the input data DATA can be provided. For example, the correction circuit is configured to input data DA
A MOS transistor that is turned on when TA is at a high level (or a low level) can be realized by connecting in parallel to the transfer gate 34 shown in FIG.

In the above description, the case where the invention made by the present inventor is mainly applied to the input / output buffer of a semiconductor integrated circuit, which is the background of the application, has been described. However, the present invention is not limited to this. And can be widely applied to various electronic circuit devices.

The present invention can be applied on the condition that it includes at least a first transistor and a second transistor connected in series to the first transistor.

[0043]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a third transistor of the first conductivity type provided between an external terminal and a serially connected portion of the first and second transistors, and a fourth transistor of the second conductivity type connected in parallel to the third transistor. , The impedance matching circuit is configured to include the third output signal in both the high-level output and the low-level output.
Both the transistor and the fourth transistor are involved in impedance matching at the same time. Since the output impedance is matched by the parallel combined impedance of the third transistor and the fourth transistor, when a transistor for impedance matching at the time of high-level output and a transistor for impedance matching at the time of low-level output are separately provided. The gate width can be reduced as compared with the above, whereby the chip occupied area of the output circuit having the slew rate control function and the impedance matching function can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of an input / output buffer included in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a characteristic diagram of a circuit current change by a slew rate control function included in the input / output buffer.

FIG. 3 is an explanatory diagram of a main part in an electronic circuit device including the semiconductor integrated circuit.

FIG. 4 is a configuration circuit diagram of an output circuit to be compared with an output circuit included in the input / output buffer.

FIG. 5 is a circuit diagram illustrating a configuration example of an output circuit included in the input / output buffer;

FIG. 6 is an explanatory diagram of a layout example of the output circuit.

FIG. 7 is an impedance characteristic diagram on the p-channel MOS transistor side in the output circuit.

FIG. 8 is an impedance characteristic diagram on the side of an n-channel MOS transistor in the output circuit.

[Explanation of symbols]

21, 22 Semiconductor integrated circuit 25-1 to 25-n Transmission line 23-1 to 23-n, 27-1 to 27-n Input / output buffer 11, 13, 15, 19 P-channel MOS transistor 12, 14, 16 , 20 n-channel MOS transistor 32 input circuit 33 output circuit 35 slew rate circuit

Claims (4)

[Claims] A slew rate circuit including a first transistor and a second transistor connected in series therewith for changing a current flowing through an external terminal in a stepwise manner according to a logical change of data to be output; An output circuit including an impedance matching circuit for matching an output impedance to a characteristic impedance of a transmission line, wherein the impedance matching circuit is provided between a serial connection point of the first transistor and the second transistor and the external terminal. An output circuit comprising: a third transistor of the first conductivity type provided in the first transistor; and a fourth transistor of the second conductivity type connected in parallel to the third transistor. 2. A slew rate circuit including a first transistor and a second transistor connected in series therewith for changing a current flowing through an external terminal in a stepwise manner according to a logical change of data to be output, An output circuit including an impedance matching circuit for matching an output impedance to a characteristic impedance of a transmission line, wherein the impedance matching circuit is provided between a serial connection point of the first transistor and the second transistor and the external terminal. , And a p-channel MOS transistor connected in parallel with the n-channel MOS transistor. The gate electrode of the p-channel MOS transistor is set to the ground potential level.
An output circuit wherein a gate electrode of a channel type MOS transistor is set to a high potential side power supply voltage level. 3. An integrated circuit comprising the output circuit according to claim 1 and an input circuit for taking in external input data, wherein the output circuit and the input circuit share the external terminal. Semiconductor integrated circuit. 4. An electronic circuit device, comprising: a plurality of semiconductor integrated circuits including the semiconductor integrated circuit according to claim 3 which are capable of exchanging signals with each other via a transmission line having a predetermined characteristic impedance characteristic.