JP2006340266A - Differential signal transmitting circuit and differential signal transmitting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a capacitance value of a phase compensation capacitor by suppressing variations of a common-mode voltage in LVDS signal transmission. <P>SOLUTION: The disclosed circuit includes: differential buffers M1-M4 each for switching directions of currents flowing to a pair of transmission lines OT1, OT2 in accordance with inputted differential signals IN, INB; first current source circuits (M6, M7 and 12) connected to one-side current supply nodes of the differential buffers; second current source circuits (AMP and M5) connected to other-side current supply nodes ND0 of the differential buffers; and current paths (M8, M9), different from the differential buffers, for causing to flow currents corresponding to the currents flowing to the differential buffers. Each of the second current source circuits comprises a differential amplifier AMP for regulating a common-mode voltage that becomes a reference of a voltage OUT to appear in the pair of transmission lines OT1, OT2, into a predetermined reference voltage Vref, and a phase compensation capacitor CC of the differential amplifier is provided in a current path (transistors M8, M9 are elaborates). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a differential signal transmission circuit and a differential signal transmission device including a differential buffer that switches the direction of a current flowing in a pair of transmission paths in accordance with an input differential signal.

  LVDS (Low Voltage Differential Signaling) is known as an interface for high-speed transmission of small amplitude signals (see, for example, Patent Document 1). LVDS is a differential small-amplitude interface standard that has been standardized in P1596.3, one of the IEEE standardization subcommittees.

FIG. 7 shows a circuit example of the LVDS driver.
The LVDS driver 100 includes transistors M1, M2, and M5 that are pMOSFETs, transistors M3, M4, M6, and M7 that are nMOSFETs, a differential amplifier AMP, a phase compensation capacitor CC, and internal resistors R1 and R2.
Transistors M1 and M3 are cascaded to form an inverter, and a differential signal IN is input to the common gate. Similarly, transistors M2 and M4 are cascaded to form an inverter, and a differential signal INB having a phase opposite to that of the differential signal IN is input to the common gate. The output of the inverter composed of the transistors M1 and M3 is connected to the first transmission line OT1, and the output of the inverter composed of the transistors M2 and M4 is connected to the second transmission line OT2. Internal resistors R1 and R2 are cascaded between one end of the first and second transmission lines OT1 and OT2, that is, between the outputs of the two inverters. These internal resistors R1, R2 and the four transistors M1-M4 form a differential buffer.
On the other hand, the other ends of the first and second transmission lines OT1 and OT2 are short-circuited via a termination resistor RT on the LVDS receiver 101 side. The first and second transmission lines OT1, OT2 have load capacities CL1, CL2, respectively.

  A first current supply transistor M6 is connected between one current supply node of the differential buffer and the ground voltage. A current source 12 and a transistor M7 are cascaded between the power supply line 11 and the ground voltage. The gate and drain of the transistor M7 and the gate of the first current supply transistor M6 are connected to each other, thereby forming a current mirror circuit. The two transistors M6 and M7 and the current source 12 form a first current source circuit that allows the reference current Iref to flow to the differential buffer.

  A second current supply transistor M5 is connected between the other current supply node ND0 of the differential buffer and the power supply line 10, and its gate is connected to the output of the differential amplifier AMP. A reference voltage Vref is applied to the inverting input “−” of the differential amplifier AMP from a voltage generation circuit (not shown), and the non-inverting input “+” of the differential amplifier AMP is connected to the connection node ND2 between the internal resistors R1 and R2. ing. A second current for adjusting the voltage (common mode voltage) of the connection node internal resistors R1 and R2 between the internal resistors R1 and R2 to the reference voltage Vref by the differential amplifier AMP and the second current supply transistor M5. A source circuit is formed.

  The LVDS driver 100 formed in this way has transistors M1 and M4 and transistors M2 and M3 as a pair in accordance with differential signals IN and INB input at the time of signal transmission, and one transistor pair is turned off. Then, the other transistor pair is turned off. When the transistors M1 and M4 are on and the transistors M2 and M3 are off, a current flows from the LVDS driver 100 to the termination resistor RT. If the second transmission line OT2 side is used as a potential reference, then a positive voltage having a value that is the product of the resistance value of the termination resistor RT and the flowing current is generated at both ends of the termination resistor RT. On the other hand, when the transistors M1 and M4 are off and the transistors M2 and M3 are on, a current flows in the opposite direction, so that a negative voltage is generated across the termination resistor RT.

  In the LVDS, the first and second transmission lines OT1 and OT2 form so-called balanced transmission lines having the same electrical characteristics, and one binary signal is transmitted through these two transmission lines. That is, when the resistance values of the internal resistors R1 and R2 are the same according to the differential signals IN and INB, the termination received by the LVDS receiver 101 centering on the voltage (common mode voltage) of the connection node ND2 of the internal resistors R1 and R2. The polarity of the voltage across the resistor RT (output voltage OUT) is inverted. By making the polarity of the output voltage OUT correspond to “1” and “0”, the differential signals IN and INB input to the LVDS driver 100 can be restored on the LVDS receiver 101 side.

Since the signal currents flowing through the first and second transmission lines OT1 and OT2 have substantially the same magnitude and opposite directions, the current of the entire balanced transmission line becomes “0”, so that there is almost no current fluctuation. On the other hand, if the LVDS receiver 101 also uses a current switching type comparator, it may be considered that there is almost no current fluctuation in the entire transmission system.
This means that noise generated by current fluctuations in the transmission system is small, and interference due to simultaneous switching is small on the transmission side and the reception side. In addition, since the influence of common-mode noise superimposed on the transmission path can be eliminated, LVDS is suitable for high-speed signal transmission of 200 MHz or higher.
In LVDS, the signal current is about 3 mA, and the voltage across the termination resistor RT, that is, the signal amplitude is about 300 mV.

In such a small signal transmission, it is important that the variation of the common mode voltage serving as a reference for determining the signal is small. In the circuit example shown in FIG. 7, the transistors M1, M2, and M5 are compared with the differential amplifier AMP. In addition, each element such as the internal resistances R1 and R2 forms common mode feedback (CMFB). Therefore, the node ND2 at which the common mode voltage appears is virtually short-circuited with the inverting input terminal “−” of the differential amplifier AMP, and is adjusted to the reference voltage Vref.
Since a phase difference is likely to occur in a feedback loop such as CMFB, phase compensation must be performed. Therefore, in the circuit example shown in FIG. 5, the phase compensation capacitor CC is connected between the output of the differential amplifier AMP and the current supply node ND0.
JP-A-11-330947

However, at the time of signal transmission, changes in the sources of the transistors M1, M2, M3, and M4 propagate to the reference voltage Vref through the phase compensation capacitor CC, thereby changing the common mode voltage. The fluctuation of the common mode voltage changes the gain because the bias points of the transistors M1 to M4 are changed. In some cases, the amplitude of the output voltage OUT is limited. In LVDS, ± 50 [mV] is defined as a standard as a common voltage fluctuation.
Further, in order to ensure the phase margin, it is necessary to increase the capacitance value of the phase compensation capacitor CC, and the layout area increases.

FIG. 8 is a waveform example of the common mode voltage in the circuit shown in FIG.
It can be seen that, in addition to switching noise having a high frequency and removable, the common mode voltage fluctuates greatly (in this example, about 300 [mV]).

  The problem to be solved by the present invention is to suppress the variation of the common mode voltage during signal transmission and reduce the capacitance value of the phase compensation capacitor.

  A differential signal transmission circuit according to the present invention is connected to a differential buffer that switches a direction of a current flowing in a pair of transmission paths according to an input differential signal, and one current supply node of the differential buffer. The first current source circuit, the second current source circuit connected to the other current supply node of the differential buffer, and the differential buffer for flowing a current corresponding to the current flowing through the differential buffer Another current path, and the second current source circuit includes a differential amplifier that adjusts a common mode voltage serving as a reference of a voltage appearing in the pair of transmission lines to a predetermined reference voltage, A phase compensation capacitor of the differential amplifier is provided in the current path.

In the present invention, preferably, the differential buffer is cascade-connected between two inverters to which the differential signal is input and the pair of transmission lines are connected to outputs, and between the outputs of the two inverters. Two internal resistors, wherein the second current source circuit compares the common mode voltage appearing between the two internal resistors with the reference voltage, and one of the differential buffers A current supply transistor connected between the current supply point and the power supply voltage supply line and controlled by the output of the differential amplifier, wherein the phase compensation capacitor includes the output of the differential amplifier and the current path Connected between and.
More preferably, the first current source circuit includes a current mirror circuit for supplying a predetermined current to a current supply transistor connected to the other current supply point of the differential buffer, and the current mirror circuit includes the current mirror circuit. A first transistor having a common control node with a current supply transistor, and a second transistor having a common control node with the current supply transistor of the second current source circuit are cascaded between a power supply voltage and a reference voltage; The phase compensation capacitor is connected between a connection point of the first and second transistors and a control node of the second transistor.

  A differential signal transmission device according to the present invention is connected between a transmission circuit including a differential buffer that switches a direction of a current flowing in a pair of transmission lines according to an input differential signal, and the pair of transmission lines. A differential signal transmission device including a reception circuit that generates a voltage having a polarity different depending on a direction of a current flowing through the termination resistor by the termination resistor, wherein the transmission circuit supplies one current of the differential buffer A first current source circuit connected to the node; a second current source circuit connected to the other current supply node of the differential buffer; and a current corresponding to a current flowing through the differential buffer. A current path different from the differential buffer, and the second current source circuit adjusts a common mode voltage serving as a reference of a voltage appearing in the pair of transmission lines to a predetermined reference voltage. Differential amplifier For example, the current path, a phase compensation capacitor of the differential amplifier is provided.

According to the present invention, when a differential signal having an opposite phase is input to the input pair of the differential buffer, one output of the differential buffer is a high level voltage and the other output is in response to the differential signal. Low level voltage. A pair of transmission lines are connected to the two outputs, and according to a more detailed configuration, two resistors are connected between the outputs. Therefore, part of the current supplied from the first and second current source circuits to the differential buffer flows through the pair of transmission lines, and the rest flows through the two resistors. The voltage between the two resistors (common mode voltage) is compared with the reference voltage by the differential amplifier, and the second current source circuit operates so that the common mode voltage is adjusted to the reference voltage. At this time, the first current source circuit tries to keep a predetermined current flowing in the differential buffer, and the load capacity of the pair of transmission lines is charged / discharged by the current difference. For this reason, the common mode voltage is adjusted so as to approach the reference voltage applied to the differential amplifier.
When the differential signal input to the differential buffer is switched, the voltage level of the output of the differential buffer is inverted, and a current flows in the opposite direction to the pair of transmission lines. Also in this case, the common mode voltage is adjusted to the reference voltage by the second current source circuit in the same manner.
The differential buffer is inverted by switching the differential signal, and the potential fluctuation at the time of switching is transmitted to the second current source circuit. However, in the present invention, the phase compensation capacitor of the differential amplifier is provided separately from the differential buffer, and is formed in a current path through which a current corresponding to the current flowing through the differential buffer flows. Therefore, this potential fluctuation does not reach the output of the differential amplifier. In addition, the capacitance value of the phase compensation capacitor is relatively small due to the Miller effect and produces the same effect as compared with the case where it is connected between the current supply node of the differential buffer and the output of the differential amplifier.

  According to the present invention, there is an advantage that the fluctuation of the common mode voltage during signal transmission can be suppressed and the capacitance value of the phase compensation capacitor can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which the differential signal transmission device according to the present embodiment is used for LVDS communication between two semiconductor chips.
In the illustrated differential signal transmission device, its transmission circuit (LVDS driver) is formed on a chip A, and a reception circuit (LVDS receiver) is formed on a chip B, and these are connected by a balanced transmission line OT. A predetermined number of LVDS drivers 1 are arranged in the chip A, and differential signals IN and INB are input to each LVDS driver 1 from an internal circuit (not shown). The differential output of the LVDS driver 1 is connected to the balanced transmission line OT via an ESD (Electrostatic Discharge) unit 3. The end of the balanced transmission line OT on the chip B side is short-circuited via a termination resistor RT and then connected to the LVDS receiver 2. Each output of the LVDS receiver 2 is connected to an internal circuit (not shown).
The differential signals IN and INB may be two signals having opposite phases transmitted from the chip A to the chip B. Specific examples of the differential signals IN and INB include an output signal (data signal) of an internal circuit of the chip A or a clock signal taken over from the chip A to the chip B.

  For example, as shown in FIG. 2, the ESD unit 3 includes two protection diodes D31 and D32 provided in each of the first transmission path OT1 and the second transmission path OT2 that are balanced transmission paths. In this example, the anode of the protection diode 31 is connected to the first transmission line OT1, the cathode is connected to the power supply line 33, the anode of the protection diode 32 is grounded, and the cathode is connected to the second transmission line OT2. ing. The protection diode 31 is turned on when a positive surge voltage (for example, electrostatic noise) exceeding the power supply voltage is applied to the transmission line, and the protection diode 32 is turned on when a negative surge voltage is applied to the transmission line. These surge voltages are supplied to the power supply line 33 and the ground voltage. The SED unit 3 is not an essential configuration and can be omitted. However, from the viewpoint of protecting the differential signal transmission device and the chip internal circuit, it is desirable to provide, for example, the ESD unit 3 having the configuration shown in FIG. 2 in the balanced transmission path.

FIG. 3 shows a circuit example of the LVDS driver 1.
The LVDS driver 1 includes transistors M1, M2 and M5 which are pMOSFETs, transistors M3, M4, M6, M7, M8 and M9 which are nMOSFETs, a differential amplifier AMP, a phase compensation capacitor CC, and internal resistors R1 and R2. And have.
Transistors M1 and M3 are cascaded to form an inverter, and a signal IN is input to the common gate. Similarly, transistors M2 and M4 are cascaded to form an inverter, and a signal INB having a phase opposite to that of the signal IN is input to the common gate. The output of the inverter composed of the transistors M1 and M3 is connected to the first transmission line OT1, and the output of the inverter composed of the transistors M2 and M4 is connected to the second transmission line OT2. Internal resistors R1 and R2 are cascaded between one end of the first and second transmission lines OT1 and OT2, that is, between the outputs of the two inverters. These internal resistors R1, R2 and the four transistors M1-M4 form a differential buffer.
On the other hand, the other ends of the first and second transmission lines OT1 and OT2 are short-circuited via a termination resistor RT on the LVDS receiver 2 side. The first and second transmission lines OT1, OT2 have load capacities CL1, CL2, respectively.

  A first current supply transistor M6 is connected between one current supply node of the differential buffer and the ground voltage. A current source 12 and a transistor M7 are cascaded between the power supply line 11 and the ground voltage. The gate and drain of the transistor M7 and the gate of the first current supply transistor M6 are connected to each other, thereby forming a current mirror circuit. The two transistors M6 and M7 and the current source 12 form a first current source circuit that allows the reference current Iref to flow to the differential buffer.

  A second current supply transistor M5 is connected between the other current supply node ND0 of the differential buffer and the power supply line 10, and its gate is connected to the output of the differential amplifier AMP. A reference voltage Vref is applied to the inverting input “−” of the differential amplifier AMP from a voltage generation circuit (not shown), and the non-inverting input “+” of the differential amplifier AMP is connected to the connection node ND2 between the internal resistors R1 and R2. ing. The differential amplifier AMP and the second current supply transistor M5 form a second current source circuit for adjusting the voltage (common mode voltage) of the connection node ND2 between the internal resistors R1 and R2 to the reference voltage Vref. Has been.

In the present embodiment, a common source amplifier circuit having a current source (second current source circuit) as a load is added. The source-grounded amplifier circuit is formed by cascading a transistor M8 that is a pMOSFET and a transistor M9 that is an nMOSFET between a power supply line 13 and a ground voltage. Transistor M9 forms a current mirror circuit together with transistor M7 and current source 12. Therefore, it is possible to flow the current flowing through the differential buffer by the first current supply transistor M6 to the transistor M9. Further, the transistor M8 can flow the same current as the current that flows to the differential buffer by the second current supply transistor M5 if the size and the supply power supply voltage are the same as those of the second current supply transistor M5.
The grounded source amplifier circuit configured in this manner corresponds to the “current path of the current corresponding to the current flowing through the differential buffer” of the present invention. In this example, the phase compensation capacitor CC is included in the grounded source amplifier circuit. Is provided. That is, the phase compensation capacitor CC is connected between the drain and gate of the transistor M8. Therefore, the phase compensation capacitor CC is insulated from the current supply node ND0 of the differential buffer.

  The LVDS driver 1 thus formed has transistors M1 and M4 and transistors M2 and M3 as a pair in accordance with differential signals IN and INB input at the time of signal transmission, and one transistor pair is turned off. Then, the other transistor pair is turned off. When the transistors M1 and M4 are on and the transistors M2 and M3 are off, a current flows from the LVDS driver 1 to the termination resistor RT. If the second transmission line OT2 side is used as a potential reference, then a positive voltage having a value that is the product of the resistance value of the termination resistor RT and the flowing current is generated at both ends of the termination resistor RT. On the other hand, when the transistors M1 and M4 are off and the transistors M2 and M3 are on, a current flows in the opposite direction, so that a negative voltage is generated across the termination resistor RT.

  In the LVDS, the first and second transmission lines OT1 and OT2 form so-called balanced transmission lines having the same electrical characteristics, and one binary signal is transmitted through these two transmission lines. That is, when the resistance values of the internal resistors R1 and R2 are the same according to the differential signals IN and INB, the termination received by the LVDS receiver 2 centering on the voltage (common mode voltage) of the connection node ND2 of the internal resistors R1 and R2. The polarity of the voltage across the resistor RT (output voltage OUT) is inverted. By making the polarity of the output voltage OUT correspond to “1” and “0”, the differential signals IN and INB input to the LVDS driver 1 can be restored on the LVDS receiver 2 side.

Since the signal currents flowing through the first and second transmission lines OT1 and OT2 have substantially the same magnitude and opposite directions, the current of the entire balanced transmission line becomes “0”, so that there is almost no current fluctuation. On the other hand, if the LVDS receiver 2 also uses a current switching type comparator, it may be considered that there is almost no current fluctuation in the entire transmission system.
This means that noise generated by current fluctuations in the transmission system is small, and interference due to simultaneous switching is small on the transmission side and the reception side. In addition, since the influence of common-mode noise superimposed on the transmission path can be eliminated, LVDS is suitable for high-speed signal transmission of 200 MHz or higher.

FIG. 4 shows waveform diagrams of the input signal and output signal of the LVDS driver.
When the differential signals IN and INB shown in FIG. 4A are given as input signals, as shown in FIG. 4B, the common mode voltage controlled to approximately the reference voltage Vref is obtained by the above-described operation. Output signals that switch to each other are obtained as intersections. In LVDS, the signal current is usually about 3 mA, and at this time, the voltage across the termination resistor RT, that is, the voltage amplitude W of the output signal is about 300 mV.

In the present embodiment, such small signal transmission suppresses fluctuations in the common mode voltage, which is a reference for discriminating signals. This will be described below.
In the circuit example shown in FIG. 3, each element such as transistors M1, M2, and M5 and internal resistors R1, R2 forms a common mode feedback (CMFB) with respect to the differential amplifier AMP. Therefore, the node ND2 at which the common mode voltage appears is virtually short-circuited with the inverting input terminal “−” of the differential amplifier AMP, and is adjusted to the reference voltage Vref.
Regarding the CMFB phase compensation, in the circuit example shown in FIG. 3, a phase compensation capacitor CC is connected between the gate (output of the differential amplifier AMP) and the drain of the transistor M8. Even in this case, the CMFB has a voltage margin corresponding to the transistors M1, M2, M3, and M4 and the termination resistor RT in the feedback loop. Therefore, the addition of the transistors M8 and M9 is performed by each transistor of the differential buffer. There is no effect on the operating point.
In this circuit, since the phase compensation capacitor CC is provided in the common-source amplifier circuit, the potential fluctuation of the current supply node ND0 that occurs when the differential buffer performs a switching operation is blocked by the second current supply transistor M5, and the differential amplifier Influencing the output of AMP is prevented or suppressed.

FIG. 5 is a waveform example of the common mode voltage in the circuit shown in FIG.
In addition to switching noise with a high frequency that can be removed, the common mode voltage fluctuates, but its range is within a few [mV]. Therefore, the fluctuation range of the common mode voltage is improved by about one digit compared with the case of FIG. Specifically, the common mode voltage can be suppressed from 37 [mV] to 7.3 [mV] in a certain required time width.

  Further, the phase compensation capacitor CC is amplified by the mirror effect, and can have a smaller capacity than the case of FIG. For example, the capacitance value of the phase compensation capacitor CC, which was 20 [pF] in the case of FIG. 5, is greatly reduced to 4 [pF] by using the circuit of FIG.

FIG. 6 shows an arrangement example of the LVDS driver 1.
In the arrangement example shown in FIG. 6, six LVDS drivers 1 are arranged in succession, a supply block 20 for the power supply voltage Vdd and a supply block 21 for the reference voltage Vss are arranged, and this arrangement is arranged on the chip A (see FIG. 1). It repeats along one side. The length H of the LVDS driver 1 in the direction orthogonal to the side of the chip A is shortened by greatly reducing the capacity of the phase compensation capacitor CC. As a result, the cell area of the LVDS driver 1 is about 30%, It is reduced by about 150 [μm ² ].

  Although the case where the LVDS driver is configured by a CMOS circuit has been described, it may be formed by other transistor elements, or the phase compensation capacitor CC may be provided in a current path other than the differential buffer. Such a circuit is not limited to FIG. When the LVDS driver is composed of a CMOS circuit, a CMOS level signal having a small voltage amplitude can be transmitted at high speed while avoiding the influence of noise. Therefore, the differential signal transmission device (transmission circuit and reception circuit) can be suitably implemented as a signal transmission device between the chip of the CMOS sensor and another chip.

It is a figure which shows the example which used the differential signal transmission apparatus in embodiment of this invention for LVDS communication between two semiconductor chips. It is a circuit diagram of an ESD unit. It is a circuit diagram of an LVDS driver. (A) and (B) are waveform diagrams of the input signal and output signal of the LVDS driver. FIG. 4 is a measurement waveform diagram of a common mode voltage in the circuit shown in FIG. 3. It is a figure which shows the example of arrangement | positioning of an LVDS driver. It is a circuit diagram of the LVDS driver of background art. FIG. 8 is a measurement waveform diagram of a common mode voltage in the circuit shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... LVDS driver, 2 ... LVDS receiver, 3 ... ESD part 10,13 ... Power supply line, 12 ... Current source, 20 ... Supply block of power supply voltage Vdd, 21 ... Supply block of reference voltage Vss, 31,32 ... Protection diode, M1, etc .... transistor, R1, R2 ... internal resistance, RT ... termination resistor, AMP ... differential amplifier, CC ... phase compensation capacitor, CL1, CL2 ... load capacitance, OT1 ... first transmission line, OT2 ... second Transmission line

Claims (4)

A differential buffer that switches the direction of the current flowing in the pair of transmission paths according to the differential signal to be input;
A first current source circuit connected to one current supply node of the differential buffer;
A second current source circuit connected to the other current supply node of the differential buffer;
A current path different from the differential buffer for flowing a current corresponding to a current flowing through the differential buffer;
The second current source circuit includes a differential amplifier that adjusts a common mode voltage serving as a reference of a voltage appearing in the pair of transmission lines to a predetermined reference voltage;
A differential signal transmission circuit, wherein a phase compensation capacitor of the differential amplifier is provided in the current path. The differential buffer is
Two inverters to which the differential signal is input and the pair of transmission lines are connected to outputs;
Two internal resistors connected in cascade between the outputs of the two inverters,
The second current source circuit comprises:
A differential amplifier for comparing the common mode voltage appearing between the two internal resistors with the reference voltage;
A current supply transistor connected between one current supply point of the differential buffer and a power supply voltage supply line and controlled by the output of the differential amplifier; and
The differential signal transmission circuit according to claim 1, wherein the phase compensation capacitor is connected between an output of the differential amplifier and the current path. The first current source circuit includes a current mirror circuit for supplying a predetermined current to a current supply transistor connected to the other current supply point of the differential buffer;
A first transistor having a common control node with the current supply transistor of the current mirror circuit, and a second transistor having a common control node with the current supply transistor of the second current source circuit have a power supply voltage and a reference voltage. Cascaded between and
The differential signal transmission circuit according to claim 2, wherein the phase compensation capacitor is connected between a connection point of the first and second transistors and a control node of the second transistor. A transmission circuit including a differential buffer that switches the direction of the current flowing in the pair of transmission paths according to the input differential signal, and a termination resistance connected between the pair of transmission paths, the current flowing in the termination resistance A differential signal transmission device comprising a receiving circuit for generating a voltage having a different polarity according to a direction,
The transmission circuit is
A first current source circuit connected to one current supply node of the differential buffer;
A second current source circuit connected to the other current supply node of the differential buffer;
A current path different from the differential buffer for flowing a current corresponding to a current flowing through the differential buffer;
The second current source circuit includes a differential amplifier that adjusts a common mode voltage serving as a reference of a voltage appearing in the pair of transmission lines to a predetermined reference voltage;
The differential signal transmission device, wherein a phase compensation capacitor of the differential amplifier is provided in the current path.

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