JPH09321555A - Differential amplifier for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an output bias voltage stable. SOLUTION: Load resistors 5, 6 have the same resistance, the resistance of resistors 11, 12 used to output a mean voltage Vom (in this embodiment, Vom =Vout1=Vout2) of output bias voltages Vout1, Vout2 of output terminals out1, out2 to a detection terminal dtc is sufficiently larger than that of the load resistors and is equal to each other. A voltage comparator 8 is an operational amplifier, a designed output bias voltage VrQ is given to its inverting input terminal (-). In the case of Vom >VrQ, an output voltage of the voltage comparator 8 rises to raise a gate voltage of a current source FET 3, resulting that an operating current Is of the current source FET 3 is increased, the bias current flowing to the load resistors is increased, the Vom is decreased and controlled to be the same as the voltage VrQ. Furthermore, in the case of Vom <VrQ, since the output voltage of the voltage comparator 8 is decreased to decrease the Is, the bias current flowing to the load resistors is decreased and the Vom is controlled to be the same as the voltage VrQ.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier constructed by using field effect transistors (hereinafter referred to as FETs) in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, in a differential amplifier using an FET as a transistor, a bias voltage (hereinafter referred to as an output bias) at a differential output terminal is caused by a change in the characteristics of the FET and the load resistance due to a temperature change, a level change of a power supply, and the like. (Referred to as voltage) may deviate from the designed value, and desired characteristics as a differential amplifier may not be obtained. Therefore, it is necessary to provide means for stabilizing the output bias voltage.

In a conventional semiconductor integrated circuit, for example, a differential amplifier as described in JP-A-07-106875 is adopted. FIG. 3 is a circuit diagram showing an example of such a conventional differential amplifier. The differential amplifier shown in FIG. 3 comprises a differential amplifier circuit composed of the differential FETs 1 and 2, the load resistors 5 and 6, and the current source FET 3 and, in addition to these, is connected in series to connect the power supply VDD and the ground potential. A resistor 7 and a FET 4, which are inserted between the resistors and constitute a bias detection circuit, and a voltage comparator 8 including an operational amplifier are provided. Resistors 5 and 6 and resistor 7, and current source FET3 and FE
Each T4 has the same characteristics. Resistor 7 and FET
The connection point of 4 is connected to the non-inverting input terminal (+) of the voltage comparator 8, and the inverting input terminal (-) of the voltage comparator 8 is connected to the comparison reference voltage. The output terminal of the voltage comparator 8 is the current source F
It is connected to the gate electrodes of ET3 and FET4.

Bias detection voltage (FE
When the drain voltage of T4) becomes smaller than the comparison reference voltage, the output voltage of the voltage comparator 8 drops, so that the FET4
The current flowing in the transistor decreases, and the bias detection voltage becomes equal to the comparison reference voltage. When the bias detection voltage becomes higher than the comparison reference voltage, the output voltage of the voltage comparator 8 rises, so that the current flowing through the FET 4 increases and the bias detection voltage becomes equal to the comparison reference voltage. In this way, the bias detection voltage is controlled to be equal to the comparison reference voltage,
By applying the output voltage of the voltage comparator 8 to the gate electrode of the FET 3 as well, the differential output terminals out1, out
The fluctuation of the bias voltage of 2 can be suppressed similarly to the above bias detection voltage.

[0005]

However, in the differential amplifier shown in FIG. 3, when the characteristics of the resistors 5, 6 and 7 or the current source FET 3 and FET 4 differ due to manufacturing variations, the output bias voltage There was a problem that was not stabilized.

The present invention solves such a problem, and an object thereof is to improve the stability of the output bias voltage.

[0007]

In order to achieve the above object, in the differential amplifier of the present invention, each first electrode is connected to the first power source through each load resistor, and the second electrode is commonly connected. And a pair of transistors having each control electrode as a differential input terminal and each of the first electrodes as a differential output terminal, and a current source transistor connected between a second electrode of the differential transistor and a second power supply. A bias detecting means for detecting a weighted average voltage of the bias voltages of the differential output terminals, and a control electrode of the current source transistor according to a difference voltage between the weighted average voltage and a preset reference voltage. Bias control means for controlling the weighted average voltage to be equal to the reference voltage by changing the applied voltage is provided.

According to a second aspect of the present invention, in the differential amplifier, the bias detecting means is connected in series and two resistors are inserted between the differential output terminals, a connection point of the two resistors and the first resistor. It consists of a capacitor inserted between one power supply or between this connection point and a second power supply, and the connection point of the two resistors is the detection terminal of the weighted average voltage, and the resistance values of the two resistors are these. The maximum value of the current flowing through the resistor is sufficiently smaller than the minimum value of the current flowing through the load resistor, the bias control means, the weighted average voltage is input to the non-inverting input terminal, The reference voltage is input to an inverting input terminal, and the output terminal is composed of an operational amplifier connected to the control electrode of the current source transistor.

A differential amplifier according to a third aspect is the first amplifier.
This is characterized in that the power supply is set to the ground potential.

Therefore, according to the present invention, the bias detection means detects the weighted average voltage of the bias voltage (output bias voltage) of each differential output terminal, and the bias control means presets the weighted average voltage. By changing the voltage applied to the control electrode of the current source transistor according to the voltage difference from the reference voltage to change the current flowing through the current source transistor, and controlling the weighted average voltage to be equal to the reference voltage. The fluctuation of the output bias voltage can be suppressed.

According to the differential amplifier of the third aspect, by setting the first power supply to the ground potential, it is possible to eliminate the fluctuation of the output bias voltage due to the fluctuation of the power supply, so that the output bias voltage is further stabilized. Can be transformed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a circuit diagram of a differential amplifier according to a first embodiment of the present invention. This differential amplifier includes N-type differential FETs 1 and 2 serving as a pair of differential transistors, a load resistance 5 of the differential FET 1, a load resistance 6 of the differential FET 2, and an N-type current serving as a constant current source. It has a source FET 3, resistors 11 and 12 for detecting the average value of the output bias voltage, a voltage comparator 8 using an operational amplifier, and a capacitor 13.

In the differential amplifier of FIG. 1, the gate electrode (control electrode) of the differential FET1 is used as the differential input terminal in1, the drain electrode (first electrode) is used as the differential output terminal out1, and the gate of the differential FET2 is used. The electrode (control electrode) is the differential input terminal in2, and the drain electrode (first electrode) is the differential output terminal out2. The drain electrode of the differential FET 1 is connected to the positive power supply VDD through the load resistor 5, and the differential FET
The drain electrode of 2 is connected to the positive power supply VDD through the load resistor 6. The source electrodes (second electrodes) of the differential FETs 1 and 2 are commonly connected and connected to the drain electrode (first electrode) of the current source FET3, and the source electrode (second electrode) of the current source FET3 is grounded. There is. Here, the differential FETs 1 and 2 have the same characteristics, and the load resistors 5 and 6 have the same characteristics.
Have the same resistance value.

Furthermore, the other end of the resistor 11 whose one end is connected to the drain electrode of the differential FET 1 and one end of the differential FET 2
Is connected to the other end of the resistor 12 connected to the drain electrode of the resistor 11, and the connection point of the resistors 11 and 12 is used as the detection terminal dtc of the average voltage Vom of the output bias voltage Vout1 of out1 and the bias voltage Vout2 of out2. It is assumed that the resistance values of 12 and 12 are the same. Here load resistances 5 and 6
Have the same resistance value, Vom = Vout1 = Vout2. This configuration can eliminate the influence of the differential signal component as compared with the case of simply detecting the bias voltage of the output terminal on one side. Note that the resistance values of the resistors 11 and 12 are set so as not to affect the characteristics of the differential amplifier, that is, compared with the minimum value of the instantaneous current flowing through the resistors 5 or 6, the resistance values of the resistors 11 and 12 flow. It is preferable to set the value such that the maximum value of the instantaneous current becomes small enough to be ignored.

The capacitor 13 constitutes bias detecting means together with the resistors 11 and 12, one end of which is connected to the detection terminal dtc and the other end of which is grounded. The in-phase signal component mixed in the voltage Vom is removed.

The voltage comparator 8 corresponds to bias control means, has an inverting input terminal (-), a non-inverting input terminal (+) and an output terminal, and has a virtual ground between the two input terminals. Is an operational amplifier having a large gain A. The design value VrQ of the output bias voltages Vout1 and Vout2 is input to the inverting input terminal (−) as a comparison reference voltage, the non-inverting input terminal (+) is connected to the detection terminal dtc, and the output terminal is the gate electrode of the current source FET3. Connected to. V from dtc
When om is equal to VrQ, the designed value VgQ of the gate bias voltage of the current source FET3 is output, and when Vd and VrQ are different, the output voltage is changed from VgQ by A × (Vd−VrQ) and the current source FET3. Vom is controlled to be equal to VrQ.

When the load resistors 5 and 6 are designed to have different values, the capacitor 13 simultaneously removes the differential signal component mixed in Vom. Further, at this time, in order to avoid mixing the differential signal component into Vom, the resistance 1
The resistance ratio of 1 and 12 may be set according to the resistance ratio of the load resistors 5 and 6, and the weighted average value of the output bias voltage may be detected. For example, the resistance ratio of the load resistors 5 and 6 is 1: 2.
In case of, the resistance ratio of the resistors 11 and 12 is set to 1: 2,
Weighted average voltage (2Vout1 + Vout2) from the detection terminal dtc
/ 3 may be detected.

Next, the operation of the differential amplifier shown in FIG. 1 will be described. If the characteristics of the current source FET 3 and the load resistors 5 and 6 are equal to the design values, the output bias voltages Vout1 and Vout
Both out2 are design value output bias voltage (comparison reference voltage)
Equal to VrQ, and thus Vom equal to VrQ, the output voltage of the voltage comparator 8 becomes the design gate bias voltage VgQ,
At this time, the current Is flowing through the current source FET3 becomes the design value IsQ of the operating current.

First, the operation when the characteristics of the current source FET 3 change due to temperature change or when the characteristics of the current source FET 3 deviate from the design values due to manufacturing variations will be described. In the case of temperature fluctuation, the characteristics of the differential FETs 1 and 2 also change at the same time, but the characteristic change of the differential FETs 1 and 2 does not affect the fluctuation of the output bias voltage (the common source electrode of the differential FETs 1 and 2 is It only changes the potential). Further, in the case of temperature fluctuation, the characteristics of the load resistors 5 and 6 also change at the same time, which will be described later.

At this time, even if the design value gate bias voltage VgQ is applied to the gate electrode of the current source FET3, the current Is does not become the design value operating current IsQ, whereby Vout1 and Vout2 are designed value output bias. It does not become the voltage VrQ.

When a temperature variation or manufacturing error such that Vom> VrQ occurs, the output voltage of the voltage comparator 8 increases and the gate-source voltage of the current source FET 3 becomes higher than VgQ. As a result, the current Is increases and the bias current flowing through the load resistors 5 and 6 increases, so that Vom drops. Since the input terminals of the voltage comparator 8 can be regarded as virtual ground, the negative feedback loop formed by the voltage comparator 8 causes Vom, that is, the output bias voltage Vout1.
And Vout2 are controlled to a value equal to the comparison reference voltage VrQ. At this time, the current Is is controlled to a value equal to the design value operating current IsQ of the current source FET3.

When a temperature variation or manufacturing error such that Vom <VrQ occurs, the output voltage of the voltage comparator 8 becomes VgQ.
And the current Is decreases, the bias current flowing through the load resistors 5 and 6 decreases, and Vout1 and Vout2 drop and are controlled to a value equal to VrQ.
s is controlled to a value equal to IsQ.

Next, the load resistances 5 and 6 are changed due to temperature fluctuations.
The operation will be described when the resistance value of No. 1 changes, or when the resistance values of the load resistors 5 and 6 deviate from the designed values due to manufacturing variations. At this time, if current Is is IsQ
, Vout1 and Vout2 will not be equal to VrQ.

When a manufacturing error of Vom> VrQ occurs, the output voltage of the voltage comparator 8 increases more than VgQ and the current Is increases more than IsQ. Therefore, the bias current flowing through the load resistors 5 and 6 is increased. Is increased and Vom, that is, Vout1 and Vout2, is decreased and controlled to a value equal to VrQ.

When a manufacturing error of Vom <VrQ occurs, the output voltage of the voltage comparator 8 becomes lower than VgQ,
Since the current Is is lower than IsQ, the bias current flowing through the load resistors 5 and 6 is reduced, and Vom, that is, Vout1.
And Vout2 are raised and controlled to a value equal to VrQ.

The current source FET 3 and the load resistors 5 and 6
It is needless to say that Vout1 and Vout2 are controlled to a value equal to VrQ even when the characteristics of 1 change at the same time or deviate from the designed values.

As described above, according to the first embodiment,
The resistors 11 and 12 directly detect the average voltage Vom of the output bias voltage, and the voltage comparator 8 changes the gate bias of the current source FET 3 according to the difference voltage between Vom and the design value output bias voltage (reference voltage) VrQ. Let the current source F
By changing the operating current of ET3 and controlling Vom to be equal to VrQ, fluctuations in the output bias voltages Vout1 and Vout2 due to manufacturing variations in the characteristics of the load resistors 5 and 6 and the current source FET3 and temperature changes. Can be suppressed.

In the first embodiment, the differential FETs 1 and 2 and the current source FET3 are N type, but the present invention is not limited to this, and the FET is P type.
A negative power source may be used instead of the positive power source VDD. Further, the above transistor is not limited to the FET, and a bipolar transistor may be used.

Second Embodiment FIG. 2 is a circuit diagram of a differential amplifier showing a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals.

The differential amplifier shown in FIG.
The connection point of the load resistors 5 and 6 is grounded without being connected to the positive power supply VDD, and the source electrode of the current source FET3 is not grounded but the negative power supply V
It is connected to EE.

Therefore, the output bias voltage of the output terminals out1 and out2 becomes a negative voltage, the polarity of the capacitor 13 is inverted, and the comparison reference voltage input to the inverting input terminal (-) of the voltage comparator becomes a negative voltage. The operation is similar to that of the differential amplifier shown in FIG.

In the differential amplifier shown in FIG. 1, the output bias voltage also fluctuates due to the level fluctuation of the positive power supply VDD, and this fluctuation was also controlled by the negative feedback loop by the voltage comparator 8. According to the embodiment of the present invention, by setting the ground potential without using the positive power supply VDD, the fluctuation of the output bias voltage due to the fluctuation of the level of the power supply is eliminated, so that the output bias voltage can be further stabilized.

The differential FE according to the second embodiment described above.
T1 and 2, current source FET3 are P type, negative power source VEE
Alternatively, a positive power source may be used. Further, the above transistor is not limited to the FET, and a bipolar transistor may be used.

[0034]

As described above, according to the present invention, the weighted average voltage of the bias voltage of each differential output terminal is detected,
By changing the voltage applied to the control electrode of the current source transistor according to the difference voltage between the weighted average voltage and the preset reference voltage, and controlling the weighted average voltage to be equal to the reference voltage. This has the effect of suppressing fluctuations in the output bias voltage.

Further, according to the third aspect of the present invention, the output bias voltage does not fluctuate due to the fluctuation of the power supply by setting the first power supply to the ground potential, so that the output bias voltage can be further stabilized. It has the effect that

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a differential amplifier showing the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional differential amplifier.

[Explanation of symbols]

 1, 2 Differential FET 3 Current source FET 5, 6 Load resistance 8 Voltage comparator 11, 12 Resistance 13 Capacitor in1, in2 Differential input terminal out1, out2 Differential output terminal dtc Detection terminal

Claims (3)

[Claims] 1. Each of the first electrodes is connected to a first power source through a respective load resistor, the second electrodes are commonly connected, each control electrode serves as a differential input terminal, and each first electrode is differential. A pair of transistors serving as output terminals, a current source transistor connected between a second electrode of the differential transistor and a second power supply, and a bias detection for detecting a weighted average voltage of bias voltages of the differential output terminals. Means to change the voltage applied to the control electrode of the current source transistor according to a difference voltage between the weighted average voltage and a preset reference voltage, thereby making the weighted average voltage equal to the reference voltage. A differential amplifier for a semiconductor integrated circuit, comprising: 2. The bias detecting means includes two resistors connected in series and inserted between the differential output terminals, and a connection point between the two resistors and the first power supply.
Alternatively, it is composed of a capacitor inserted between this connection point and the second power supply, and the connection point of the two resistors is used as the detection terminal of the weighted average voltage, and the resistance value of the two resistors is set to the value of the current flowing through these resistors. The maximum value is set to a value that is sufficiently smaller than the minimum value of the current flowing through the load resistor, and the bias control means inputs the weighted average voltage to a non-inverting input terminal and inverts the reference voltage. 2. The differential amplifier for a semiconductor integrated circuit according to claim 1, wherein the differential amplifier is input to an input terminal and comprises an operational amplifier whose output terminal is connected to the control electrode of the current source transistor. 3. The differential amplifier for a semiconductor integrated circuit according to claim 1, wherein the first power supply is at ground potential.