JPH1117470A - Electronic volume - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic volume of a wide output dynamic range normally operated even by a low voltage. SOLUTION: Feedback resistors R2-R4 are provided in the feedback resistor FR of a negative feedback amplifier circuit NFA in this electronic volume. Also, switch circuits SW1 and SW2 provided with N type and P type MOS transistors NM and PM for selectively using the feedback resistors R2-R4 are provided. Then, gain is switched by selectively using the feedback resistors R2-R4. At the time, when the switch circuit is in an ON state like the switch circuit SW1, a reference potential Vref is applied to the back gates BG of the N type and P type MOS transistors NM and PM so as to reduce ON impedance. On the other hand, when the switch circuit is in an OFF state like the switch circuit SW2, a ground potential is applied to the back gate BG of the N type MOS transistor NM and the potential Vcc of a supply power source is applied to the back gate BG of the P type MOS transistor PM so as to widen the output dynamic range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic volume, and more particularly to an electronic volume operable at a low voltage which can be formed on an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, there has been an electronic volume that uses a CMOS analog switch as a switch circuit to perform gain switching in a software manner. This electronic volume has a power supply voltage of a MOS in a CMOS analog switch.
When the voltage is sufficiently higher than the threshold voltage Vth of the transistor, the transistor operates normally. However, when the supply power becomes low, the device does not operate normally. That is, when the voltage of the power supply decreases and becomes close to the threshold voltage Vth, there is a problem that the on-impedance of the MOS transistor of the CMOS analog switch rapidly increases. In particular, when a battery such as a dry battery is used as a power source, a voltage drop is an unavoidable problem. For this reason, in order to secure sufficient gain accuracy even at a low voltage as an electronic volume, it is necessary to make the on-impedance of the MOS transistor of the CMOS analog switch for switching the gain sufficiently small even at a low voltage. .

[0003]

As can be seen from the above description, in an electronic volume, the on-impedance of a CMOS analog switch as a switch circuit needs to be sufficiently low even at a low voltage. For this purpose, the gate width of the MOS transistor in the CMOS analog switch must be increased or the threshold voltage Vth must be reduced. However, when the gate width is increased, there is a problem that the area of the IC increases. When the threshold voltage Vth is lowered,
There is a problem that the leak current in other circuits on the IC increases. That is, when the threshold voltage Vth of the MOS transistor is lowered, a current flows between the source and the drain, and the current leaks, although the gate is not normally in the ON state.

The present invention has been made in view of the above problems, and has as its object to provide an electronic volume that can operate normally even when the power supply becomes low. That is, an object of the present invention is to provide an electronic volume in which the on-impedance of a MOS analog switch constituting a switch circuit does not increase even when the supply power becomes low. Another object of the present invention is to provide an electronic volume with a wide output dynamic range despite normal operation at such a low voltage.

[0005]

In order to solve the above problems, an electronic volume according to the present invention comprises an operational amplifier, an input resistor connected between an input terminal and a negative terminal of the operational amplifier, and A feedback resistor connected between the output terminal of the operational amplifier and the negative terminal of the operational amplifier,
A reference potential is applied to a positive terminal of the operational amplifier, and a gain from the input terminal to an output terminal of the operational amplifier is determined by a ratio of a value of the input resistor to a value of the feedback resistor. A feedback amplifier circuit, at least one of the input resistor and the feedback resistor is configured with a plurality of resistors, and a switch circuit that short-circuits the plurality of resistors is provided.
In an electronic volume in which the value of the input resistor and the value of the feedback resistor are switched by turning on and off the switch circuit, and the gain of the negative feedback amplifier circuit is switched, the switch circuits are connected in parallel with each other. A gate of the N-type MOS transistor and a gate of the P-type MOS transistor are connected via an inverter. When the switch circuit is turned on, Applying the supply potential to the gate of the N-type MOS transistor, applying the reference potential to the back gate, applying the ground potential to the gate of the P-type MOS transistor, and applying the reference potential to the back gate. When the switch circuit is turned off, the gate of the N-type MOS transistor is turned off. , A ground potential is also applied to the back gate, a potential of the power supply is applied to the gate of the P-type MOS transistor, and a potential of the power supply is also applied to the back gate. is there.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention relates to a switch having a plurality of resistors provided in a feedback resistor of a negative feedback amplifier circuit and having N-type and P-type MOS transistors for bypassing the resistors. By providing a circuit, in an electronic volume in which the gain is switched by selectively using these resistors, when the switch circuit is on, the N-type and the P-type are used to reduce the on-impedance of the switch circuit.
Potential Vr is applied to the back gate of the
When ef is applied and the switch circuit is off,
N-type MOS to widen output dynamic range
The ground potential is applied to the back gate of the transistor, and the potential of the power supply is applied to the back gate of the P-type MOS transistor. Hereinafter, FIGS. 1 to 3
This will be described in more detail based on

FIG. 1 is a diagram showing an example of a circuit of an electronic volume according to a first embodiment of the present invention, FIG. 2 is a diagram showing an equivalent circuit of a switch circuit portion in an on state, and FIG. FIG. 4 is a diagram showing an equivalent circuit in an off state of a switch circuit portion, which is opposite to FIG.

As can be seen from FIG. 1, the electronic volume of the first embodiment includes a negative feedback amplifier circuit NFA, a first switch circuit SW1, and a second switch circuit SW2.

The negative feedback amplifier circuit NFA has an input terminal a,
When input signal V1 is input from a ′, output terminal b,
This is an inverting amplifier circuit that outputs an output signal V2 obtained by inverting and amplifying the input signal V1 from b ′. This negative feedback amplifier N
FA denotes an operational amplifier OP, an input resistor R1, and a feedback resistor R2.
To R4 and a power supply Vref. More specifically, the lower left input terminal a and the operational amplifier OP
, An input resistor R1 is provided between the negative terminals.
The input resistor R1 forms an input resistor IR. Feedback resistors R2 to R4 are provided in series between the negative terminal of the operational amplifier OP and the output terminal of the operational amplifier OP. These feedback resistors R2 to R4 form a feedback resistor FR. A power supply Vref is connected to the positive terminal of the operational amplifier OP, and the power supply Vref causes the reference potential Vref to be applied to the positive terminal of the operational amplifier OP.
ref is given. Further, an input terminal a ′ and an output terminal b ′ are commonly connected to the power supply Vref. The gain of the negative feedback amplifier circuit NFA is V2 / V1
= − (R2 + R3 + R4) / R1. That is, by the ratio of the values of the input resistor IR and the feedback resistor FR,
The gain is determined.

The first switch circuit SW1 and the second switch circuit SW2 function as a switch for switching between a conductive state and a non-conductive state of a signal line.
This is an S analog switch circuit. First switch circuit S
W1 is provided in parallel with the feedback resistor R2. That is, the connection terminal X1 on the input side of the first switch circuit SW1
Is connected to the negative terminal of the operational amplifier OP, and the output connection terminal Y1 is connected to the middle point between the feedback resistors R2 and R3. The second switch circuit SW2 is provided in parallel with the feedback resistors R2 and R3. That is, the second
The connection terminal X2 on the input side of the switch circuit SW2 is connected to the negative terminal of the operational amplifier OP, and the connection terminal Y2 on the output side.
Is connected to the middle point between the feedback resistors R3 and R4. By connecting the first switch circuit SW1 and the second switch circuit SW2 in this way, these connection terminals X1 and X2 on the input side are commonly connected to the negative terminal of the operational amplifier OP. Thus, the potentials of the connection terminals X1 and X2 of the switch circuits SW1 and SW2 are equal to the reference potential Vref regardless of the on / off state of the switch circuits SW1 and SW2.
Since these switch circuits SW1 and SW2 have the same configuration, here, the configuration will be described focusing on the first switch circuit SW1.

The first switch circuit SW1 includes an N-type MOS transistor NM and a P-type MOS transistor PM connected in parallel with each other.
This is a MOS analog switch. MOS transistor N
The drain D of M and the source S of MOS transistor PM
Is connected to the connection terminal X1 on the input side. The midpoint between the source S of the MOS transistor NM and the drain D of the MOS transistor PM is connected to the output-side connection terminal Y1. MOS transistor NM
Is connected to a signal line from the switch control terminal Z1. The gate G of the MOS transistor PM is connected to a switch control terminal Z1 via an inverter INV.
Are connected. That is, the gates G, G of the MOS transistors NM, PM are connected to each other by the inverter I.
Connected via NV. A switch control signal for switching the first switch circuit SW1 between the ON state and the OFF state is input from the switch control terminal Z1.

The switch control terminal Z1 is connected to an interlock switch LK.
It is also connected to SW1. Thus, the interlocking switch LKSW1 is controlled to be switched by the switch control signal. This interlock switch LKSW1 is for switching the potential applied to the back gate BG of the first MOS transistor NM. On the other hand, the switch control terminal Z1 is also connected to the interlock switch LKSW2 via the inverter INV. Thus, the interlocking switch LKSW2 is also controlled to be switched by the switch control signal. The interlock switch LKSW2 is for switching the potential applied to the back gate BG of the second MOS transistor PM. A power supply of the potential Vref is connected to one terminal of these interlocking switches LKSW1 and LKSW2. That is, the reference potential V
ref is applied. On the contrary,
The other terminal of the interlock switch LKSW1 is connected to the ground. The other terminal of the interlock switch LKSW2 is connected to a power supply of the potential Vcc. Thus, the N-type MOS transistor NM and the P-type MOS transistor
Each of the transistors PM is formed of an integrated circuit using a process capable of independently applying the potential of the back gate BG.

Next, the operation of the above-described electronic volume will be described. As can be seen from the above description, FIG.
The electronic volume switches the gain by switching the switch circuits SW1 and SW2. That is, when both the first switch circuit SW1 and the second switch circuit SW2 are off, the gain G of the electronic volume becomes-(R2 + R3 + R4) / R1. The first switch circuit SW1 is turned on, and the second switch circuit S
When W2 is off, the gain G of the electronic volume is-(R3 + R4) / R1. The electronic volume in FIG. 1 indicates this state. When both the first switch circuit SW1 and the second switch circuit SW2 are on, the gain G of the electronic volume is −
R4 / R1. Note that the switch circuits SW1, SW2
There are four on / off combinations in total.
When the switch circuit SW1 is in the off state and the second switch circuit is in the on state, the gain G of the electronic volume is -R4 / R1, and the first switch circuit SW1
It is the same as the gain G when both and the second switch circuit SW2 are on. Therefore, it can be seen that the gain G of the electronic volume is three in total.

The operation of the entire electronic volume is as described above. Next, the operation of the first switch circuit SW1 and the second switch circuit SW2 will be described. Here, the first switch circuit SW1 in FIG. 1 indicates the ON state, and the second switch circuit SW2 indicates the OFF state. Therefore, the operation will be described focusing on these.

These switch circuits SW1 and SW2 are:
A CMOS analog switch has its basic configuration. Therefore, the basic operation is the same as that of the CMOS analog switch. That is, as can be seen from the switch circuit SW1, when the switch control signal which is the input signal from the switch control terminal Z1 is high, that is, when the potential is the power supply potential Vcc, the N-type MOS transistor N
The M and P-type MOS transistors PM are both turned on. That is, the potential Vcc of the power supply is applied to the gate G of the N-type MOS transistor NM, and the ground potential G is applied to the gate G of the P-type MOS transistor PM.
ND is applied. Therefore, this switch circuit SW1
Is connected between the input-side connection terminal X1 and the output-side connection terminal Y1, and the feedback resistor R2 is bypassed. On the other hand, as can be seen from the switch circuit SW2, when the switch control signal is low, that is, when the switch control signal is at the ground potential, the N-type
The S transistor NM and the P-type MOS transistor PM are both turned off. That is, the ground potential is applied to the gate G of the N-type MOS transistor NM, and the potential Vcc of the power supply is applied to the gate G of the P-type MOS transistor PM. Therefore, the connection between the connection terminal X2 on the input side and the connection terminal Y2 on the output side of the switch circuit SW2 becomes non-conductive, and the feedback resistor R3 is not bypassed.

In such a CMOS analog switch, the interlocking switches LKSW1 and LKSW2 operate in conjunction. That is, as can be seen from the first switch circuit SW1, when the switch control signal is high, both the interlocking switches LKSW1 and LKSW2 are connected to the power supply Vref. Therefore, the MOS transistors NM, PM
The same potential as the reference potential Vref of the operational amplifier OP is applied to the back gates BG, BG. That is, CMO
When the S analog switch is conductive, the MOS
The reference potential Vref is applied to the back gates BG, BG of the transistors NM, PM.

On the other hand, as can be seen from the second switch circuit SW2, when the switch control signal is low, the interlock switch LKSW1 is connected to the ground side,
KSW2 is connected to Vcc side. Therefore, the ground potential is applied to the back gate BG of the MOS transistor NM. The potential Vcc of the power supply is applied to the back gate BG of the MOS transistor PM.

As described above, in the first embodiment of the present invention, when the switch circuits SW1 and SW2 are on, the reference potential Vref is applied to the back gates BG and BG of the MOS transistors NM and PM. When the switch circuits SW1 and SW2 are off, the ground potential is applied to the back gate BG of the MOS transistor NM, and the potential Vcc of the power supply is applied to the back gate BG of the MOS transistor PM. Therefore, the output dynamic range can be widened while the on-impedance of the MOS transistors NM and PM is kept low. That is, the MOS transistor N
By lowering the on-impedance of M and PM, normal operation can be performed even at a low voltage, and clipping due to current flowing to the back gate BG can be prevented.

More specifically, the first switch circuit SW1
When the switch circuit is in the ON state as in the above, the back gates BG, BG of the MOS transistors NM, PM are
The reference potential Vref is applied. Here, back gate B
Applying the reference potential Vref to G and BG means that
This means that it is equivalent to the switch circuit SW1 shown in FIG. That is, the potential of the negative terminal of the operational amplifier OP in FIG. 1 is substantially equal to Vref. Therefore, the potential of the connection terminal X1 on the input side of the switch circuit SW1 also becomes substantially Vref. As a result, as can be seen from FIG. 2, the back gate BG of the MOS transistor NM is equivalent to being connected to the drain D, and the back gate BG of the MOS transistor PM is equivalent to being connected to the source S. Therefore, the on-impedance of the MOS transistors NM and PM can be suppressed low by the substrate bias effect. However, as can be seen from FIG. 1, the switch circuit SW1 is maintained while the reference potential Vref is applied to the back gates BG.
Is turned off, there is a problem that the output signal V2 is clipped when the amplitude is large.

That is, the output signal V2 may have a large amplitude and the potential at the connection terminal Y1 may increase.
In this case, the potential at the connection terminal Y1 and
When the potential difference from the potential at the back gate BG of the P-type MOS transistor PM becomes larger than the voltage determined by the PN junction in the structure of the MOS transistor, the P-type MOS transistor PM
Current flows to the back gate BG of the transistor PM. That is, current flows from the drain D of the P-type MOS transistor PM to the back gate BG. Therefore, the high voltage side of the output signal V2 is clipped, that is, limited. On the other hand, the output signal V2 may have a large amplitude and the potential at the connection terminal Y1 may decrease.
In this case, the potential at the connection terminal Y1 and
When the potential difference from the potential at the back gate BG of the N-type MOS transistor NM becomes larger than the voltage determined by the PN junction on the structure of the MOS transistor, the N-type MOS
A current flows through the back gate BG of the transistor NM. That is, current flows from the back gate BG to the source S of the N-type MOS transistor NM. Therefore, the low voltage side of the output signal V2 is also clipped.
As described above, when the output signal V2 has a large amplitude, clipping occurs, and there is a problem that the output dynamic range cannot be widened.

Therefore, in this embodiment, when the switch circuit SW1 is turned off, the switch circuit S1 is turned off.
By switching the interlocking switches LKSW1 and LKSW2 as in W2, the back gate B of the MOS transistor NM is changed.
A ground potential is applied to G, and the MOS transistor PM
Of the power supply is applied to the back gate BG. Therefore, the switch circuit SW2 becomes equivalent to the switch circuit SW2 shown in FIG. Thereby, as can be seen from FIG. 1, the output signal V2 can be prevented from being clipped. That is, even if the output signal V2 has a large amplitude and the potential of the connection terminal Y2 changes greatly,
No current flows between the back gate BG of the N-type MOS transistor NM and the back gate BG of the P-type MOS transistor PM between Vcc and GND. Therefore, the output signal V2 is not clipped, and the output dynamic range can be increased. That is,
The voltage amplitude that can be handled by this electronic volume can be increased. However, M of the switch circuit SW2
Each of the OS transistors NM and PM is in a reverse bias state and has a large on-impedance. That is, N
In the type MOS transistor NM, the potential of the drain D is in a reverse bias state higher than that of the back gate BG. Also, in the P-type MOS transistor PM, the potential of the source S is in a reverse bias state lower than that of the back gate BG. For this reason, the on-impedance of the MOS transistors NM and PM is high, especially when the supply power becomes low and the reference potential Vref decreases. Therefore, the switch circuit S
When W2 is turned on, the interlocking switches LKSW1 and LKSW2 are also switched like the switch circuit SW1, and the reference potential Vref is applied to the back gates BG and BG of these MOS transistors NM and PM.

As can be seen from the above description, according to the switch circuits SW1 and SW2 of the first embodiment of the present invention, an operation having only the advantages of the CMOS analog switch shown in FIGS. 2 and 3 becomes possible. An electronic volume with high gain accuracy can be provided without increasing the circuit area. By configuring the switch circuits SW1 and SW2 for switching the gain of the electronic volume as described above, a great effect can be obtained.

(Second Embodiment) In the second embodiment, the input resistor in the negative feedback amplifier circuit of the electronic volume of the first embodiment is also provided with a plurality of resistors, and the plurality of resistors of the input resistor are also switched. By selectively using in the circuit,
The number of kinds of gains that can be switched with the electronic volume is increased. This will be described in more detail below with reference to FIG.

As can be seen from FIG. 4, the negative feedback amplifier circuit N
The input resistor IR of the FA has a plurality of input resistors R1, R
5, R6 are provided. Of these input resistances,
A switch circuit SW3 is provided in parallel with the input resistor R1. Further, a switch circuit SW4 is provided in parallel with the input resistors R1 and R5. That is, the switch circuit SW
3, the connection terminal on the input side of SW4 is commonly connected to the negative terminal of the operational amplifier OP, and the connection terminal Y3 on the output side of the switch circuit SW3 is connected to the midpoint between the input resistance R1 and the input resistance R5; Connection terminal Y on the output side of switch circuit SW4
Reference numeral 4 is connected to a middle point between the input resistors R5 and R6. That is, the electronic volume of the second embodiment shown in FIG.
And an electronic volume of the first embodiment shown in FIG. In other respects, the electronic volume according to the second embodiment is the same as the electronic volume according to the first embodiment, and a detailed description thereof will be omitted. In FIG. 4, the switch circuits SW1, SW2, SW3,
Although the specific configuration of SW4 is omitted, the specific circuit configuration is the same as the switch circuits SW1 and SW2 in FIG.

As described above, in the electronic volume of the second embodiment, the input resistor I of the negative feedback amplifier circuit NFA is used.
R also has a plurality of input resistors R1, R5, R6, and switch circuits SW3, SW4 for selectively using these input resistors R1, R5, R6. For this reason, the types of gain that can be handled can be increased. That is, it is possible to switch to nine types of gains in all of 3 × 3. Specifically, as described in the first embodiment, the feedback resistors R2 to R4 provided in the feedback resistor FR are provided.
And three types of gains can be switched by switch circuits SW1 and SW2 for selectively using these feedback resistors R2 to R4. Further, three types of gains are provided by input resistors R1, R5, R6 provided in the input resistor IR and switch circuits SW3, SW4 for selectively switching and using these input resistors R1, R5, R6. Can switch. Note that the switch circuit SW
3. The combination of ON / OFF of SW4 is 4 in total.
It is on the street. However, as in the case of the switch circuits SW1 and SW2, the gain when the switch circuit SW3 is off and the switch circuit SW4 is on is the same as the gain when the changeover switches SW3 and SW4 are both on. It is. Therefore, the gain of the input resistor IR can be switched in three ways.

(Third Embodiment) A third embodiment of the present invention is a modification of the electronic volume of the first embodiment, in which a plurality of resistors provided in a feedback resistor are connected in parallel one by one. A switch circuit is provided. This will be described in more detail below with reference to FIG.

As can be seen from FIG. 5, the feedback resistor FR of the electronic volume is provided with feedback resistors R2 to R4 as in the first embodiment. These feedback resistors R2
Of the R4, the switch circuit SW1 is connected in parallel with the feedback resistor R2.
Is provided. Further, a switch circuit SW2 is provided in parallel with the resistor R3. That is, a switch circuit is individually provided in parallel with the resistors R2 and R3 provided in the feedback resistor FR. As described above, the third embodiment is different from the first embodiment in that switch circuits are individually provided in parallel with the respective resistors. That is, as can be seen from FIG. 1, in the first embodiment,
By turning on the switch circuit SW2, the plurality of resistors R3 and R4 can be bypassed. That is, the gain can be switched only by turning on one switch circuit. On the other hand, as can be seen from FIG. 5, in the third embodiment, by turning on the plurality of switch circuits SW1 and SW2, the plurality of feedback resistors R2 and R3 are turned on.
Can be bypassed. That is, by turning on one switch circuit,
One resistor can be bypassed. Except for this point, the electronic volume of the third embodiment has the same configuration as the electronic volume of the first embodiment, and a detailed description thereof will be omitted.

As described above, the third embodiment of the present invention can provide the same effects as those of the first embodiment. However, in order to operate the electronic volume normally in the third embodiment, it is necessary to turn on the switch circuits in order from the one closer to the negative terminal of the operational amplifier OP. For example, when the switch circuit SW2 is on, the switch circuit SW1 must also be on. That is, an arbitrary switch circuit cannot be individually turned on / off as in the first embodiment. Because
This is because when an arbitrary switch circuit is turned on / off, the potential of the connection terminal X on the input side of the switch circuit does not become Vref. For example, when the switch circuit SW1 is off and the switch circuit SW2 is on, the potential of the connection terminal X2 on the input side of the switch circuit SW2 does not become Vref. That is, the connection terminal X of the switch circuit
If the potential on the side does not become Vref, the on-impedance cannot be sufficiently reduced even if the reference potential Vref is applied to the back gate BG of the MOS transistor.

(Fourth Embodiment) In the fourth embodiment, a plurality of resistors are provided also for the input resistor in the negative feedback amplifier circuit of the electronic volume of the third embodiment, and the plurality of resistors of the input resistor are also switched. By selectively using in the circuit,
The number of kinds of gains that can be switched with the electronic volume is increased. This will be described in more detail below with reference to FIG.

As can be seen from FIG. 6, the negative feedback amplifier N
The input resistor IR of the FA has a plurality of input resistors R1, R
5, R6 are provided. Among these resistors, a switch circuit SW3 is provided in parallel with the input resistor R1. Further, a switch circuit SW4 is provided in parallel with the resistor R5. That is, the electronic volume according to the fourth embodiment shown in FIG. 4 includes a resistance value R5 on the input side of the operational amplifier OP,
R6 and changeover switches SW3 and SW4 for switching the R6
Is different from the electronic volume of the third embodiment shown in FIG. That is, the relationship between the fourth embodiment and the third embodiment is the same as the relationship between the above-described second embodiment and the first embodiment. In other respects, the electronic volume according to the fourth embodiment is the same as the electronic volume according to the third embodiment, and a detailed description thereof will be omitted.

As described above, in the electronic volume of the fourth embodiment, the input resistor I of the negative feedback amplifier NFA is
R also has a plurality of input resistors R1, R5, R6, and switch circuits SW3, SW4 for selectively switching and using these input resistors R1, R5, R6. For this reason, the types of gain that can be handled can be increased. That is, it is possible to switch to nine types of gains in all of 3 × 3. However, also in the fourth embodiment,
As in the third embodiment, in order to operate the electronic volume normally, it is necessary to turn on the switch circuits sequentially from the side closer to the negative terminal of the operational amplifier OP. For example, when the switch circuit SW4 is on, the switch circuit SW3 must be on. This is because when the switch circuit SW3 is off and the switch circuit SW4 is on, the potential of the input terminal X4 on the input side of the switch circuit SW4 does not become Vref. As described above, if the potential of the connection terminal X side of the switch circuit does not become Vref, the on-impedance does not become sufficiently low even if the reference potential Vref is applied to the back gate BG of the MOS transistor.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the number and arrangement of the switch circuits are not limited to those described above. That is, by increasing the number of switch circuits, the types of gains that can be handled by the electronic volume can be increased. As shown in FIGS. 7 and 8, a switch circuit is not provided in the feedback resistor FR, and the switch circuit SW is provided only in the input resistor IR.
3, SW4 can also be provided.

[0033]

As described above, according to the electronic volume of the present invention, an appropriate potential is applied to the back gate of the MOS transistor of the switch circuit.
The output dynamic range can be widened while keeping the on-impedance of the CMOS analog switch in the switch circuit low. That is, by lowering the on-impedance of the CMOS analog switch for switching the gain of the electronic volume, it is possible to operate normally even at a low voltage, and it is possible to prevent clipping due to current flowing through the back gate.

[Brief description of the drawings]

FIG. 1 is an exemplary diagram showing an example of a circuit of an electronic volume according to a first embodiment of the invention.

FIG. 2 is an equivalent circuit diagram of the switch circuit in an ON state.

FIG. 3 is an equivalent circuit diagram in an off state of the switch circuit.

FIG. 4 is a diagram showing an example of a circuit of an electronic volume according to a second embodiment of the invention.

FIG. 5 is a diagram showing an example of a circuit of an electronic volume according to a third embodiment of the invention.

FIG. 6 is a diagram illustrating an example of a circuit of an electronic volume according to a fourth embodiment of the invention.

FIG. 7 is a diagram showing a modification of the circuit of the electronic volume according to the present invention.

FIG. 8 is a diagram showing another modification of the circuit of the electronic volume according to the present invention.

[Explanation of symbols]

 SW1 First switch circuit SW2 Second switch circuit NFA Negative feedback amplifier circuit FR Feedback resistor IR Input resistor OP Operational amplifier NM N-type MOS transistor PM P-type MOS transistor LKSW1 Link switch LKSW2 Link switch INV Inverter

Claims (10)

[Claims] 1. An operational amplifier, an input resistor connected between an input terminal and a negative terminal of the operational amplifier, and an input resistor connected between an output terminal of the operational amplifier and a negative terminal of the operational amplifier. And a feedback resistor connected thereto, a reference potential is applied to a positive terminal of the operational amplifier, and a gain from the input terminal to an output terminal of the operational amplifier is adjusted by the input resistor and the feedback resistor. A negative feedback amplifier circuit determined by a ratio of a value of the input resistor and the feedback resistor, at least one of the input resistor and the feedback resistor is constituted by a plurality of resistors, and a switch circuit for short-circuiting the plurality of resistors is provided. In an electronic volume in which the values of the input resistor and the feedback resistor are switched by turning on and off, the gain of the negative feedback amplifier circuit is switched. Connected N-type MO in parallel
An S transistor and a P-type MOS transistor are provided. The gate of these N-type MOS transistors and the P-type M
The gate of the OS transistor is connected via an inverter, and when the switch circuit is turned on, the N-type MOS
The potential of the power supply is applied to the gate of the transistor, the reference potential is applied to the back gate, the ground potential is applied to the gate of the P-type MOS transistor, and the reference potential is applied to the back gate. When turning off, the N-type MOS
A ground potential is applied to the gate of the transistor, a ground potential is also applied to the back gate, a potential of the power supply is applied to the gate of the P-type MOS transistor, and a potential of the power supply is also applied to the back gate. Electronic volume. 2. An input resistor comprising one or more resistors and one or more resistors.
Or a feedback resistor consisting of a plurality of resistors is connected to an operational amplifier, and a gain is changed by adjusting a ratio between the input resistor and the feedback resistor. In the electronic volume, the input resistor and the feedback resistor In one or both of the vessels, one or more of the resistors
A switch circuit for forming a bypass is connected in parallel, and the switch circuit includes an N-type MOS transistor and a P-type MOS transistor connected in parallel with each other for switching between an on state and an off state of the changeover switch circuit. And the gate of the N-type MOS transistor and the gate of the P-type MOS transistor are connected via an inverter. When the switch circuit is on, the N-type MOS transistor
By applying the reference potential to the back gate of the transistor and the back gate of the P-type MOS transistor, the potential of the back gate and the reference potential which is the potential of the connection terminal on the input side of the changeover switch circuit are set to the same potential. And when the switch circuit is off, the N-type MOS
Apply a ground potential to the back gate of the transistor,
An electronic volume, wherein current is prevented from flowing through the back gate by applying a potential of a power supply to the back gate of the P-type MOS transistor. 3. An input resistor comprising one or more resistors and one or more resistors.
Or a feedback resistor consisting of a plurality of resistors is connected to an operational amplifier, and a gain is changed by adjusting a ratio between the input resistor and the feedback resistor. In the electronic volume, the input resistor and the feedback resistor A plurality of switch circuits, one end of which is connected to a negative terminal of the operational amplifier circuit and the other end is connected to different connection midpoints of the plurality of resistors. The circuit includes an N-type MOS transistor and a P-type MOS transistor connected in parallel with each other for switching between an on state and an off state of the changeover switch circuit. The gate of the N-type MOS transistor and the P-type MOS transistor are connected to each other. The gate of the transistor is connected via an inverter, and when the switch circuit is on, the N-type MOS
By applying the reference potential to the back gate of the transistor and the back gate of the P-type MOS transistor, the potential of the back gate and the reference potential which is the potential of the connection terminal on the input side of the changeover switch circuit are set to the same potential. And when the switch circuit is off, the N-type MOS
Apply a ground potential to the back gate of the transistor,
An electronic volume, wherein current is prevented from flowing through the back gate by applying a potential of a power supply to the back gate of the P-type MOS transistor. 4. An input resistor having one or a plurality of resistors connected in series to a negative terminal of the operational amplifier, and an output terminal of the operational amplifier connected to a negative terminal of the operational amplifier. And a feedback resistor having a plurality of resistors connected in series or in series, a reference potential is applied to a positive terminal of the operational amplifier, a negative feedback amplifier circuit, the input resistor and the One or more switch circuits for selectively bypassing an arbitrary resistor and switching the number of resistors connected in series, for at least one of the feedback resistors, wherein the switch circuit includes An N-type MOS transistor and a P-type MOS transistor connected in parallel with each other for switching between an ON state and an OFF state of the N-type MOS transistor. The gate of the OS transistor are connected via the inverter, when the switching circuit is turned on, the N-type MOS
By applying the reference potential to the back gate of the transistor and the back gate of the P-type MOS transistor, the potential of the back gate and the reference potential which is the potential of the connection terminal on the input side of the changeover switch circuit are set to the same potential. And when the switch circuit is off, the N-type MOS
Apply a ground potential to the back gate of the transistor,
An electronic volume, wherein current is prevented from flowing through the back gate by applying a potential of a power supply to the back gate of the P-type MOS transistor. 5. The feedback resistor of the negative feedback amplifier circuit is provided with a plurality of resistors in series, and a switch circuit is connected to each of the plurality of resistors in parallel. By turning on these switch circuits in order from the side closer to the negative terminal of the operational amplifier,
5. The electronic volume according to claim 4, wherein the gain of the negative feedback amplifier circuit is switched by bypassing the resistor. 6. The feedback resistor of the negative feedback amplifier circuit is provided with a plurality of resistors in series, and the resistors are provided with a plurality of switch circuits. 5. The electronic volume according to claim 4, wherein a gain of the negative feedback amplifier circuit can be switched by bypassing the resistor by turning on any one of the switch circuits. 6. . 7. A plurality of resistors are provided in series with the input resistor of the negative feedback amplifier circuit, and a switch circuit is connected in parallel to each of the plurality of resistors. By turning on these switch circuits in order from the side closer to the negative terminal of the operational amplifier,
5. The electronic volume according to claim 4, wherein the gain of the negative feedback amplifier circuit is switched by bypassing the resistor. 8. A plurality of resistors are provided in series with the input resistor of the negative feedback amplifier circuit, and a plurality of switch circuits are provided for these resistors. 5. The electronic volume according to claim 4, wherein a gain of the negative feedback amplifier circuit can be switched by bypassing the resistor by turning on any one of the switch circuits. 6. . 9. A plurality of resistors are provided in series with each of the feedback resistor and the input resistor of the negative feedback amplifier circuit, and at least a part of the resistors is provided. A switch circuit is connected in parallel to each of the plurality of switch circuits, and the plurality of switch circuits are sequentially turned on from a side closer to the negative terminal of the operational amplifier,
5. The electronic volume according to claim 4, wherein the gain of the negative feedback amplifier circuit is switched by bypassing the resistor. 10. A plurality of resistors are provided in series for both the feedback resistor and the input resistor of the negative feedback amplifier circuit, and a plurality of switch circuits are provided for these resistors. By turning on one of the plurality of switch circuits, the resistor can be bypassed and the gain of the negative feedback amplifier circuit can be switched. The electronic volume according to claim 4.