JP2751747B2 - Current mirror circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mirror circuit, and more particularly to an output current limiting type current mirror circuit in which an output current is limited to a constant current with respect to an input current of a certain value or more (or less). About.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram of a conventional current mirror circuit having an output current limiting function. Referring to FIG. 6, a current detection resistor 60 (resistance value R3) having one end connected to the current input terminal 1, an input terminal connected to the other end of the resistor 60, and a common terminal connected to the ground potential. The current mirror circuit CM2, the emitter is the current input terminal 4 and the resistor 6
The PNP transistor Q5 has a base commonly connected to the input terminal 1 of the current mirror circuit CM2 and the other end of the resistor 60, and a collector connected to the ground potential. The output terminal of the current mirror circuit CM2 becomes the output terminal 2 of the output current limiting type current mirror circuit.

Here, assuming that the voltage between the emitter and the base at which the transistor Q5 starts to turn on is VBE (Q5ON) and the current input to the current input terminal 1 is Iin, VB
When E (Q5ON)> Iin × R3, the transistor Q
Reference numeral 5 denotes an off state, which does not affect the current mirror operation. Therefore, the output current of the current mirror circuit is
If Mout is obtained, the following equation (1) is obtained.

ICMout = Iin (1) That is, a normal current mirror operation is performed.

Next, VBE (Q5ON) <Iin × R3
In this case, the transistor Q5 is turned on, and a part of the input current Iin becomes the collector current IC (Q5) of the transistor Q5 and is bypassed to the ground potential GND. As a result, the current ICMin flowing to the input terminal of the current mirror circuit CM2
Are clamped, and ICMin = VBE (Q5ON) / R3 (2) Then, of the input current Iin, the collector current IC of the transistor Q5 bypassed to the ground potential GND
(Q5) becomes IC (Q5) = Iin-ICMin (3). Here, VBE (Q5ON) is 0.6V to 0.2V.
Since it becomes almost constant at about 7 V, the current mirror circuit C
The current ICMin of M2 becomes a limited and almost constant value.
Therefore, the output current ICMo of the current mirror circuit CM2
ut also has a substantially constant value as a result. Accordingly, the relational expression with the input current Iin is as follows: ICMout = ICMin <Iin (4) FIG. 7 is a graph showing the relationship between the input current Iin and the output current ICMout of the current mirror circuit CM2 at this time. As shown in FIG. 7, the output current (ICMout) is limited for an input current (Iin) equal to or more than a certain fixed value, and has a characteristic that becomes substantially constant thereafter.

Here, the reason why the output current does not become a completely constant value when the output current is limited and is slightly dependent on the input current is as follows.
Transistor Q5 base-emitter voltage VBE (Q
5ON) depends on the input current Iin.
That is, this VBE (Q5ON) is given by the following equation (5).

VBE (Q5ON) = VTin {(Iin−ICMin) / IS (Q5)} (5) where IS (Q5) is the reverse saturation current of transistor Q5, and VT is the thermal voltage (≒ 26 mV at = 25 ° C). However, as can be seen from the above equation (5), log compression is performed, and the effect is relatively small.

[0008]

In this conventional output current limiting type current mirror circuit, the output current limiting value is determined by the emitter-base voltage of the transistor Q5. Therefore, the base-emitter voltage is about -2 mV
/ ° C., the output current limit value also has a temperature characteristic proportional to this, resulting in a problem that the temperature characteristic is poor.

In addition, when the output current is limited, there is a problem that the base-emitter voltage of the transistor Q5 slightly varies depending on the magnitude of the input current Iin, and the output current limit value is not completely constant.

It is an object of the present invention to provide a current mirror circuit which solves the above problems and has a good temperature characteristic and a constant output current limit value.

[0011]

According to one aspect of the current mirror circuit of the present invention, a first resistor having one end connected to a current input terminal and the other end connected to a constant potential, and a collector connected to a current output terminal. A connected transistor, a second resistor having one end connected to the emitter of the transistor, the other end connected to the constant potential, an output connected to the base of the transistor, and an inverting input terminal connected to the transistor. The first non-inverting input terminal is connected to the first
And a voltage discriminating amplifier connected to one end of the resistor and having a second non-inverting input terminal connected to a constant voltage source.

[0012]

FIG. 1 is a circuit diagram showing an output current limiting type current mirror circuit according to an embodiment of the present invention.

Referring to FIG. 1, this embodiment has a constant current source Iin connected to a current input terminal 10 and an input current detection device having one end connected to the current input terminal 10 and the other end connected to the ground potential. Transistor 13 (resistance value R1), and an NPN transistor Q1 having a collector connected to the current output terminal 11.
One end is connected to the emitter of the transistor Q1, the other end is connected to the ground potential, the resistor 12 (resistance value R2) and the output are connected to the base of the transistor Q1, and the inverting input terminal is connected to the emitter of the transistor Q1. , A first non-inverting input terminal 16 is connected to one end of the resistor 13 and a second non-inverting input terminal 15 is configured to include an amplifier A1 with a voltage discriminating circuit connected to a constant voltage source VREF.

Here, the amplifier A1 with the voltage discriminating circuit 2
The two non-inverting input terminals 16 and 15 are circuits in which the input of the lower input voltage is effective among the voltages input here.

Therefore, when the voltage of the first non-inverting input In1 (+) is lower than the voltage of the second non-inverting input In2 (+),
That is, when Iin × R1 <VREF, the second forward input In2 (+) becomes invalid and the first forward input In1
(+) And the inverting input In (-) form a differential amplifier. Then, the voltage of the inverting input In (−) becomes the same potential as the voltage of the first non-inverting input In1 (+) due to the imaginary short. Therefore, the potential VR2 of the resistor 12 is expressed by the following equation (6).

VR2 = Iin × R1 (6) Therefore, the current IR2 flowing through the resistor 12 is expressed by the following equation (7).

IR2 = R1 × Iin / R2 (7) Here, the bias current flowing through the inverting input In (−) is sufficiently small, and the grounded emitter current amplification β of the transistor Q1 is sufficiently large. If it can be ignored, the collector current of the transistor Q1, that is, the output current Iout of the current mirror circuit becomes equal to the current flowing through the resistor 12. Therefore, the output current Iout is given by the following equation (8).

Iout = R1 × Iin / R2 (8) In the equation (8), when R1 = R2, Iout = I
in, and becomes a current mirror circuit having a current ratio of 1: 1. Also, by selecting the resistance ratio between R1 and R2, the current ratio of the current mirror circuit can be freely changed.

Next, consider the case where the first non-inverting input voltage In1 (+) is higher than the second non-inverting input voltage In2 (+), that is, the case of Iin × R1> VREF. At this time, the first non-inverting input In1 (+) becomes invalid, and the second non-inverting input In2 (+) and the inverting input In (-) constitute a differential amplifier. Then, the voltage of the inverting input In (−) becomes the same potential as the second non-inverting input voltage In2 (+) due to the imaginary short. Therefore, the potential VR2 of the resistor 12 becomes the following (9)
It becomes an expression.

VR2 = VREF (9) It is constant without affecting the input current Iin. Therefore, the resistance 1
2, the output current Iout also becomes constant, and the output current Io at this time also becomes constant.
ut is expressed by the following equation (10).

Iout = VREF / R2 (10) As can be seen from equation (10), the output current limit value of the current mirror circuit is determined by the reference voltage source VREF when the resistance value 12 is fixed. As described above, the relationship between the input current Iin and the output current Iout of the current mirror circuit is shown by a graph. As shown in FIG. It becomes the characteristic which becomes.

Next, an amplifier A1 with a voltage discriminating circuit shown in FIG.
FIG. 2 shows an example of the circuit configuration of FIG. Referring to FIG.
The amplifier A1 with the voltage discriminating circuit includes PNP transistors Q3 and Q4 each having an emitter and a collector interconnected.
And a PNP transistor Q2 whose emitter is commonly connected to the emitters of the transistors Q3 and Q4 to form a differential amplifier with the transistors Q3 and Q4.
A current mirror circuit CM1 serving as an active load of a differential stage composed of a transistor Q2 and a transistor Q2; an amplifier A2 for current amplifying and level shifting a signal converted to a single end by the active load; and a transistor Q2 connected in common. , Q3, Q4, and a constant current source Io for biasing the differential stage and connected between the positive power supply VCC.

The collectors of the commonly connected PNP transistors Q3 and Q4 are connected to a current mirror circuit CM1.
The collector of the PNP transistor Q2 is connected to the output terminal of the current mirror circuit CM1 and the input of the amplifier A2. The common terminal of the current mirror circuit CM1 is connected to the GND potential. Here, the base of the transistor Q2 is configured as an inverting input In (-), and the bases of the transistors Q4 and Q3 are connected to the first and second non-inverting inputs In1 (+) and In2, respectively.
(+). The output of the amplifier A2 becomes the output terminal OUT of the amplifier with a voltage discriminating circuit.

Here, the PNP transistors Q3 and Q4
Are connected in common, so that the PNP of the lower voltage of the two input voltages input to each base is
The transistor becomes active and the other PNP transistor becomes non-conductive. The PNP transistor Q2 of the active PNP transistor forms a differential amplifier.

This operation realizes a function as an amplifier with a voltage discriminator in which the lower input voltage is effective among the two input voltages input to the first and second non-inverting inputs.

FIG. 5 shows the amplifier A1 with the voltage discriminating circuit.
FIG. 7 is a characteristic diagram showing a relationship between an input current Iin and an output current Iout when a circuit in which a higher input voltage is effective for two non-inverting input terminals is used.

This is because when the voltage of the first non-inverting input In1 (+) is lower than the voltage of the second non-inverting input In2 (+),
That is, when Iin × R1 <VREF, the first forward input is invalid, the second forward input is invalid, and the constant voltage VREF connected to the second forward input In2 (+) is valid. Become. Therefore, in this region where the input current Iin is small, the current becomes a constant current determined by VREF as in the above-described equation (10).

Next, when the voltage of the first forward input In1 (+) is higher than the voltage of the second forward input In2 (+), that is, when Iin × R1> VREF, the second forward rotation is performed. The input becomes invalid, and the voltage applied to R1 connected to the first non-inverting input In1 (+) becomes valid. Therefore, in this region, a normal current mirror operation as shown in the above equation (8) is performed, and an output current proportional to the input current is obtained.

This application example is effective when the output current Iout is prevented from falling below a certain value when the input current Iin falls below a certain value.

FIG. 4 is a circuit diagram showing an example of a circuit configuration of the amplifier A1 with a voltage discriminating circuit used in this case.
Referring to FIG. 4, the PNP transistor in FIG. 2 is changed to an NPN transistor, and the polarities of the current mirror circuit CM1 and the bias constant current source Io are reversed. Other configurations are the same as those in FIG. 2, and thus the same reference numerals are given and the description thereof is omitted. Here, since the emitters of the NPN transistors Q3 and Q4 are commonly connected, of the two input voltages input to the respective bases, the NPN transistor of the higher voltage becomes active and the other NPN transistor becomes active.
The PN transistor is turned off. The active NPN transistor and the NPN transistor Q2 constitute a differential amplifier. By this operation,
Among the two input voltages input to the first and second non-inverting inputs, a function as an amplifier with a voltage discriminator in which a higher input voltage is effective can be realized.

In the circuit of FIG. 1 described above, the following equations (11) and (12) are obtained considering the error of the output current due to the common emitter current gain β of the NPN transistor Q1.

Iout = β / (1 + β) · R1 / R2 · In (Iin × R1 <VREF) (11) Iout = β / (1 + β) · VREF / R2 (Iin × R1> VREF) (12) If an error due to β becomes a problem, the NPN transistor Q1 may be an N-channel field effect transistor. In this case, the base of the transistor Q1 is used as the gate,
Simply replace the collector with the drain and the emitter with the source and reconnect (not shown). Since the field effect transistor has the same source current and drain current and has no error due to β unlike a bipolar transistor, the first term (β / (1+
β)) becomes 1.

Further, the above-mentioned error caused by β can be reduced by connecting the NPN transistor Q1 to the Darlington connection (not shown).

When it is desired to reverse the directions of the input current and the output current, the same configuration can be obtained by changing the NPN transistor Q1 to a PNP transistor and further changing the GND potential to the positive power supply VCC.

The transistor Q1 of the embodiment shown in FIG. 1 is constituted by a field effect transistor, the emitter is connected to the source or the drain, the base is connected to the gate, and the collector is connected to the drain or the source. Is also good.

[0036]

As described above, according to the present invention, the output limiting constant current of the current mirror circuit can be controlled by the reference constant voltage. Has the effect that a stable one can be obtained, and in the output limited current mode, the input current is completely separated from the input current. In particular, by changing the characteristics of the voltage discrimination circuit, there is also an effect that the output limiting current mode can be adapted to two cases, that is, a high current region and a low current region.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a current mirror circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of the amplifier with a voltage discriminator shown in FIG.

FIG. 3 is a characteristic diagram showing an input / output current relationship in the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing another example of the amplifier with a voltage discriminator shown in FIG. 1;

5 is a characteristic diagram showing an input / output current relationship when the circuit of FIG. 4 is used in the amplifier of FIG. 1;

FIG. 6 is a circuit diagram showing a conventional current mirror circuit.

FIG. 7 is a characteristic diagram showing an input / output current relationship in a conventional example.

[Explanation of symbols]

 Q1, to Q5 Transistors R1, R2, R3 Resistance VREF Constant voltage source Iin, Io Constant current source A1 Amplifier with voltage discriminator A2 Amplifier CM1, CM2 Current mirror circuit VCC Positive power supply terminal

Claims (4)

(57) [Claims] 1. A transistor having one end connected to a current input terminal and the other end connected to a constant potential, a transistor having a collector connected to the current output terminal, and one end connected to an emitter of the transistor. A second resistor having the other end connected to the constant potential, an output connected to the base of the transistor, an inverting input terminal connected to the emitter of the transistor, and a first non-inverting input terminal connected to the transistor. A current mirror circuit comprising: an amplifier with a voltage discriminating circuit connected to one end of the first resistor and having a second non-inverting input terminal connected to a constant voltage source. 2. The semiconductor device according to claim 1, wherein the transistor is a field-effect transistor, the emitter corresponds to a source or a drain, the base corresponds to a gate, and the collector is connected to a drain or a source. The current mirror circuit according to claim 1, wherein 3. The amplifier with a voltage discrimination circuit according to claim 1, wherein a lower one of the input voltages input to the first non-inverting input terminal and the second non-inverting input terminal is effective. The current mirror circuit according to claim 1, wherein: 4. The amplifier with a voltage discrimination circuit according to claim 1, wherein a higher input voltage is effective among input voltages input to the first non-inverting input terminal and the second non-inverting input terminal. The current mirror circuit according to claim 1, wherein: