JP2009153097A - Differential drive circuit and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential drive circuit and communication device which can output a differential signal with no common-mode component, in simple configuration, even when the gate voltage-drain current characteristic of transistors is non-linear or even when the characteristic differs between transistors of different polarities. <P>SOLUTION: A first resistor R1 and a second resistor R2 are connected between sources of first and second transistors Q1, Q2 and a power supply potential source VDD, and a third resistor R3 and a fourth resistor R4 are connected between sources of third and fourth transistors Q3, Q4 and a reference potential source VSS. Feeding-back is loaded so that source voltages of the first and second transistors Q1, Q2 and source voltages of the third and fourth transistors Q3, Q4 become equal to drive target voltages V1-V4, respectively, and gates of the first and second transistors Q1, Q2 and gates of the third and fourth transistors Q3, Q4 are driven to extract outputs from drains. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a differential drive circuit and a communication device that process a differential signal propagated through a differential transmission line or the like.

Differential signals are widely used to transmit high-speed data over long distances.
In particular, the push-pull type driver described in Patent Document 1 is frequently used because current consumption required to drive a differential signal to a load is small.

  In such a circuit, if the long-term average values of the pull-up current and pull-down current do not match, the average voltage of the load will not be stable.Therefore, feedback control is used to keep the output common mode voltage constant. Adjust the source.

Patent Document 2 discloses a technique for suppressing the generation of the common mode voltage by adjusting the drive timing of the drive transistor.
JP 2006-345259 A JP 2003-347860 A

However, the technique of adjusting the current source by using feedback control that makes the output common mode voltage constant is a slow response control and only keeps the average voltage constant. The instantaneous value of the common mode voltage varies greatly due to variations in the on / off timing of the push-pull transistor.
Such fluctuations in the common mode voltage generate a pulsating current that propagates through the differential transmission path and returns through the line connecting the ground potential GND of the transceiver, causing a large amount of radiation noise.

As described above, the technique disclosed in Patent Document 2 suppresses the generation of a common mode voltage by adjusting the drive timing of the drive transistor.
However, strictly speaking, this method is effective when the rise time of the pull-up drive circuit and the fall time of the pull-down drive circuit are equal. In reality, there is a difference in the time, so the common mode voltage fluctuation is reduced to zero. It cannot be suppressed.

More generally, a technique is used in which the output of the differential drive circuit including fluctuations in the common mode voltage is suppressed by a filter element called a common mode filter or a pulse transformer.
However, these filter elements are large and cannot be integrated together with a drive circuit on a semiconductor substrate, which disadvantageously increases the number of components and is expensive.

  The present invention has a simple configuration, and even if the gate voltage-drain current characteristic of the transistor is non-linear, or even if the characteristic is different between transistors having different polarities, a differential signal without a common mode component is output. It is an object of the present invention to provide a possible differential driving circuit and communication device.

  A differential drive circuit according to a first aspect of the present invention includes a first conductivity type first field effect transistor, the first conductivity type second field effect transistor, a first resistance element, and a second resistance element. A first circuit for controlling the source voltage of the first field effect transistor to be equal to the first driving target voltage to be supplied; and a second circuit to which the source voltage of the second field effect transistor is supplied. And a second circuit for controlling to be equal to the drive target voltage of the first field effect transistor, the source of the first field effect transistor being connected to the power source potential source through the first resistance element, and the drain of the second circuit being A first drive connected to a first output node, a source of the second field effect transistor connected to a power supply potential source via the second resistance element, and a drain connected to the second output node; System and second conductivity type 3 field effect transistor, the second conductivity type fourth field effect transistor, the third and fourth resistance elements, and the third driving target to which the source voltage of the third field effect transistor is supplied. And a fourth circuit for controlling the source voltage of the fourth field effect transistor to be equal to the fourth drive target voltage to be supplied. The source of the third field effect transistor is connected to the reference potential source through the third resistance element, the drain is connected to the first output node, and the source of the fourth field effect transistor is the first 4 has at least one of a second drive system connected to a reference potential source through a resistance element and a drain connected to a second output node, and a common-mode voltage is constant across the load resistor. Differential It is driven so as to form a No..

  Preferably, the first drive target voltage and the second drive target voltage form a differential signal pair whose sum is constant, and the third drive target voltage and the fourth drive target voltage are summed. A constant differential signal pair is formed.

  Preferably, the first drive target voltage and the third drive target voltage are the same waveform signal including an offset, and the second drive target voltage and the fourth drive target voltage include an offset. Same waveform signal.

  Preferably, an average voltage of the first drive target voltage and the second drive target voltage is biased so as to be a certain amount lower than the power supply potential, and the third drive target voltage and the fourth drive target voltage are biased. The average voltage of the drive target voltage is biased so as to be a certain amount higher than the reference potential.

  Preferably, in the first circuit, a first input terminal is connected to a supply line of the first drive target voltage, a second input terminal is connected to a source of the first field effect transistor, A first operational amplifier having an output connected to the gate of the first field effect transistor, wherein the second circuit has a first input terminal connected to a supply line of the second drive target voltage; A second operational amplifier having a second input terminal connected to the source of the second field effect transistor and an output connected to the gate of the second field effect transistor; The first input terminal is connected to the third drive target voltage supply line, the second input terminal is connected to the source of the third field effect transistor, and the output is connected to the gate of the third field effect transistor. Connected second The fourth circuit has a first input terminal connected to the fourth drive target voltage supply line, and a second input terminal connected to the source of the fourth field effect transistor. And a fourth operational amplifier whose output is connected to the gate of the fourth field effect transistor.

  Preferably, a fifth resistance element is connected between the source of the first field effect transistor and the source of the second field effect transistor, and the source of the third field effect transistor and the fourth field effect are connected. A sixth resistance element is connected between the sources of the transistors.

  Preferably, the first drive target voltage and the second drive target voltage are generated in response to the differential voltage, the generated first drive target voltage is supplied to the first circuit, and the first circuit is supplied. A first differential amplifier for supplying the second drive target voltage to the second circuit; and receiving the differential voltage to generate the third drive target voltage and the fourth drive target voltage, And a second differential amplifier that supplies the third drive target voltage to the third circuit and supplies the fourth drive target voltage to the fourth circuit.

  Preferably, the first drive system includes a digital-analog converter (DAC) that generates the first drive target time potential and the second drive target potential according to input digital data, The second drive system has a digital-analog converter (DAC) that generates the third drive target time potential and the fourth drive target potential in accordance with input digital data.

  Preferably, the first drive system includes a first DAC that generates the first drive target potential based on a first addition / subtraction result of two numerical inputs, and a second addition / subtraction result of two numerical inputs. A second DAC that generates the second drive target potential, and the second drive system generates the third drive target potential based on a third addition / subtraction result of two numerical inputs. 3 DAC and a fourth DAC that generates the fourth drive target potential based on the result of the fourth addition / subtraction of two numerical inputs.

  Preferably, the first drive system includes a stabilization circuit that stabilizes outputs of the first DAC and the second DAC, and the second drive system includes the third DAC and the third DAC. A stabilizing circuit for stabilizing the output of the fourth DAC;

  Preferably, the first drive system includes a multiplier that multiplies the input by a coefficient defined so that an output of the DAC with respect to a specific input becomes a constant value and inputs the coefficient to the DAC. The second drive system includes a multiplier that multiplies the input by a coefficient defined so that the output of the DAC with respect to a specific input becomes a constant value and inputs the input to the DAC.

  Preferably, the first drive system includes an offset addition circuit for adding an offset to the first drive target potential and the second drive target potential generated by the first differential amplifier, The second drive system includes an offset addition circuit for adding an offset to the third drive target potential and the fourth drive target potential generated by the second differential amplifier.

  Preferably, the first drive system is connected in parallel to a load resistance of the first differential amplifier, and a first field effect transistor for resistance adjustment and a gate potential of the first field effect transistor. The second drive system is connected in parallel to the load resistance of the second differential amplifier, the second field effect transistor for resistance adjustment, and the second And an adjustment circuit for adjusting a gate potential of the field effect transistor.

  Preferably, a common mode feedback circuit that suppresses common mode voltage fluctuations is connected to the load side.

  A communication apparatus according to a second aspect of the present invention includes transmitters arranged on both ends of a differential transmission line, and the transmitter forms a differential signal having a constant common-mode voltage at both ends of a load resistor. The differential drive circuit includes a first conductivity type first field effect transistor, a first conductivity type second field effect transistor, and a second conductivity type. A third field effect transistor; a second field effect transistor of the second conductivity type; first and second output nodes; and first, second, third, and fourth resistance elements. And the source of the first field effect transistor is connected to the power supply potential via the first resistance element, the drain is connected to the first output node, and the source of the second field effect transistor is Connected to the power supply potential via the second resistance element, IN is connected to the second output node, the source of the third field effect transistor is connected to the reference potential through the third resistance element, the drain is connected to the first output node, and The source of the fourth field effect transistor is connected to the reference potential via the fourth resistance element, the drain is connected to the second output node, and the source voltage of the first field effect transistor is supplied. A first circuit for controlling to be equal to the first drive target voltage, and a second circuit for controlling the source voltage of the second field effect transistor to be equal to the second drive target voltage to be supplied A third circuit for controlling the source voltage of the third field effect transistor to be equal to the third drive target voltage to be supplied, and the source of the fourth field effect transistor. It has a fourth circuit which scan voltage is controlled to be equal to the fourth drive target voltage supplied, the.

  Preferably, a receiver is provided in parallel with the transmitter with respect to the differential transmission path.

According to the present invention, the first resistance element and the second resistance element are connected between the source of the first and second field effect transistors and the power supply potential, respectively, and the source of the third and fourth field effect transistors The third resistance element and the fourth resistance element are connected between the first and second reference potentials.
Then, feedback is performed so that the voltages of the sources of the first and second field effect transistors and the sources of the third and fourth field effect transistors are equal to the respective drive target voltages, and the first and second electric field effects are applied. The gate of the effect transistor and the gates of the third and fourth field effect transistors are driven to extract the output from the drain.
This differential drive circuit functions as a so-called differential push-pull driver.

  According to the present invention, even if the gate voltage-drain current characteristics of a transistor are non-linear and the characteristics are different for transistors having different polarities, the differential having no common mode component can be obtained. A signal can be output.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the first embodiment of the present invention.

  The driver 1 includes a differential drive circuit 2, a first digital-analog converter (DAC) 3, a second DAC 4, and a common mode feedback (CMFB) circuit 5.

The differential drive circuit 2 includes a PMOS transistor Q1 which is a first field effect transistor of a first conductivity type, for example, a p-channel type (P type), a PMOS transistor Q2 which is a P type second field effect transistor, Have
The differential drive circuit 2 includes an NMOS transistor Q3, which is a second field-type, for example, an n-channel (N-type) third field effect transistor, an NMOS transistor Q4, which is an N-type fourth field-effect transistor, Have
Further, the differential drive circuit 2 includes a first output node NO1, a second output node NO2, a first resistance element R1, a second resistance element R2, a third resistance element R3, 4 resistive elements R4.

The source of the first transistor Q1 is connected to the power supply potential source VDD via the first resistance element R1, and the drain is connected to the first output node NO1.
The source of the second transistor Q2 is connected to the power supply potential source VDD via the second resistance element R2, and the drain is connected to the second output node NO2.
The source of the third transistor Q3 is connected to the reference potential source VSS via the third resistance element R3, and the drain is connected to the first output node NO1.
The source of the fourth transistor Q4 is connected to the reference potential source VSS via the fourth resistance element R4, and the drain is connected to the second output node NO2.
Note that the reference potential VSS includes the ground potential GND.

Furthermore, the differential drive circuit 2 of the present embodiment includes a first circuit 21 that controls the source voltage S1 of the first transistor Q1 to be equal to the first drive target voltage V1 supplied from the DAC 3.
The differential drive circuit 2 includes a second circuit 22 that controls the source voltage S2 of the second transistor Q2 to be equal to the second drive target voltage V2 supplied from the DAC 3.
The differential drive circuit 2 includes a third circuit 23 that controls the source voltage S3 of the third transistor Q3 to be equal to the third drive target voltage V3 supplied from the DAC 4.
The differential drive circuit 2 includes a fourth circuit 24 that controls the source voltage S4 of the fourth transistor Q4 to be equal to the fourth drive target voltage V4 supplied.
The differential drive circuit 2 drives, for example, a transmission line on the output side so as to form a differential signal having a constant common-mode voltage at both ends of the load resistor Rload.

The first circuit 21 includes a first operational amplifier A1.
In the first circuit 21, a non-inverting input terminal (+) as a first input terminal is connected to a supply line of the first drive target voltage V1, and an inverting input terminal (−) as a second input terminal is connected. The output of the first transistor Q1 is connected to the source of the first transistor Q1, and the output is connected to the gate of the first transistor Q1.

The second circuit 22 includes a second operational amplifier A2.
In the second circuit 22, the non-inverting input terminal (+) as the third input terminal is connected to the supply line of the second drive target voltage V 2, and the inverting input terminal (−) as the fourth input terminal is connected. The output of the second transistor Q2 is connected to the source of the second transistor Q2, and the output is connected to the gate of the second transistor Q2.

The third circuit 23 is configured by a third operational amplifier A3.
In the third circuit 23, the non-inverting input terminal (+) as the fifth input terminal is connected to the supply line of the third drive target voltage V3, and the inverting input terminal (−) as the sixth input terminal is connected. The output is connected to the source of the third transistor Q3, and the output is connected to the gate of the third transistor Q3.

The fourth circuit 24 is configured by a fourth operational amplifier A4.
In the fourth circuit 24, the non-inverting input terminal (+) which is the seventh input terminal is connected to the supply line of the fourth drive target voltage V4, and the inverting input terminal (−) which is the eighth input terminal. Connected to the source of the fourth transistor Q4, the output is connected to the gate of the fourth transistor Q4.

  The DAC 3 receives the N-bit digital signal D, generates the first drive target voltage V1 and the second drive target voltage V2, and uses the generated first drive target voltage V1 for the first drive target voltage V1 of the differential drive circuit 2. The second drive target voltage V <b> 2 is supplied to the second circuit 22.

  The DAC 4 receives the N-bit digital signal D, generates the third drive target voltage V3 and the fourth drive target voltage V4, and uses the generated third drive target voltage V3 for the third drive target voltage V3. The fourth drive target voltage V4 is supplied to the fourth circuit 24.

The DAC 3 is connected between the first supply line LV1 of the first drive target voltage V1 and the power supply potential source VDD, and between the first supply line LV1 and the reference potential source VSS. And a current source I31.
The DAC 3 is connected between the second supply line LV2 of the second drive target voltage V2 and the power supply potential source VDD, and between the second supply line LV2 and the reference potential source VSS. And a current source I32.
The DAC 3 includes N current sources I3-0 to I3-N-1 connected to the reference potential source VSS and weighted with current values.
Further, the DAC 3 includes switches SW3-0 to SW3-N-1 that selectively connect the current sources I3-0 to I3-N-1 and the first or second supply lines LV1 and LV2. .
Note that the reference potential VSS includes the ground potential GND.

The DAC 4 is connected between the third supply line LV3 of the third drive target voltage V3 and the reference potential source VSS, and between the third supply line LV3 and the power supply potential source VDD. And a current source I41.
The DAC 4 is connected between the fourth supply line LV4 of the fourth drive target voltage V4 and the reference potential source VSS, and between the fourth supply line LV4 and the power supply potential source VDD. And a current source I42.
The DAC 4 includes N current sources I4-0 to I4-N-1 connected to the power supply potential source VDD and weighted with current values.
Further, the DAC 4 includes switches SW4-0 to SW4-N-1 that selectively connect the current sources I4-0 to I4-N-1 and the third or fourth supply lines LV3, LV4. .
Note that the reference potential VSS includes the ground potential GND.

  The common mode feedback (CMFB) circuit 5 has a function of absorbing a surplus current supplied to the load side.

The common mode feedback (CMFB) circuit 5 includes N-type field effect transistors Q51 and Q52, an operational amplifier A51, resistance elements R51 and R52, and a common voltage source V51.
The drain of the transistor Q51 is connected to the first output node NO1 side of the differential drive circuit 2, the source is connected to the reference potential VSS (for example, the ground potential GND), and the gate is connected to the output of the operational amplifier A51.
The drain of the transistor Q52 is connected to the second output node NO2 side of the differential drive circuit 2, the source is connected to the reference potential VSS (for example, the ground potential GND), and the gate is connected to the output of the operational amplifier A51.
Resistive elements R51 and R52 are connected in series between the first output node NO1 and the second output node NO2 of the differential drive circuit 2, and the connection point of both the resistive elements is the inverting input terminal (−) of the operational amplifier A51. It is connected to the. The common voltage source V51 is connected to the non-inverting input terminal (+) of the operational amplifier A51.

In the driver 1 having such a configuration, output voltage information given digitally is converted by the DAC 3 and the DAC 4 as follows.
That is, in the DAC 3, the output voltage information is changed to the first drive target voltage V1 and the second drive target voltage V2, which are analog voltages that are the drive target values of the first and second transistors (PMOS transistors) Q1 and Q2. Converted.
In the DAC 4, the output voltage information is converted into a third drive target voltage V3 and a fourth drive target voltage V4, which are analog voltages serving as drive target values for the third and fourth transistors (NMOS transistors) Q3 and Q4. The

The first drive target voltage V1 and the second drive target voltage V2 are a differential signal pair whose sum is constant, and the third drive target voltage V3 and the fourth drive target voltage V4 are also a differential signal pair whose sum is constant. is there.
Further, the first drive target voltage V1 and the third drive target voltage V3 are signals having the same waveform with an offset, and the second drive target voltage V2 and the fourth drive target voltage V4 are also the same waveform having an offset. Signal.
The first drive target voltage V1 and the second drive target voltage V2 are biased so that the average voltage is a certain amount lower than the power supply potential VDD.
The third drive target voltage V3 and the fourth drive target voltage V4 are biased so that the average voltage is a value higher than the reference potential VSS by a certain amount.

  The instantaneous voltages of the first to fourth drive target voltages V1 to V4 are expressed by the following formula having one parameter V (t).

[Equation 1]
V1 (t) = VbiasP + V (t) (1)
V2 (t) = VbiasP−V (t) (2)
V3 (t) = VbiasN + V (t) (3)
V4 (t) = VbiasN−V (t) (4)

The operational amplifier An (n = 1 to 4) constitutes negative feedback (NFB) so that the source voltage Sn of the transistor Qn becomes equal to the drive target voltage Vn.
As a result, a current determined by V (t) flows through the resistance elements R1 to R4, and an equal amount of current flows also through the drains of the transistors Q1 to Q4.
Assuming that the resistance values of the resistance elements R1 to R4 are all R, the current Ipos from the drain coupling point of the transistors Q1 and Q3 to the load is expressed by the following equation.

[Equation 2]
Ipos
= (VDD-VbiasP-V (t)) / R- (VbiasN + V (t)) / R
= (VDD-VbiasP-VbiasN-2V (t)) / R (5)

  Similarly, the current Ineg flowing from the load into the drain coupling point of the transistors Q2 and Q4 is expressed by the following equation.

[Equation 3]
Ineg
= (VbiasN-V (t)) / R- (VDD-VbiasP + V (t)) / R
= (VbiasN + VbiasP-VDD-2V (t)) / R (6)

  Here, the current Ipos and the current Ineg are equal if the following formula is set to be biased.

[Equation 4]
VDD-VbiasP = VbiasN (7)

[Equation 5]
Ipos = Ineg = -2V (t) / R (8)

  This indicates that the circuit neither charges nor discharges the average voltage to the load, indicating that the common mode voltage is kept constant.

In an actual circuit, the bias cannot perfectly satisfy the relationship of the above expression (7) due to variations in element performance.
To cope with this, the bias is set so that the current Ipos is slightly larger than the current Ineg but surely, and the current supplied by the current Ipos is absorbed by the common mode feedback (CMFB) circuit 5. Good.
The CMFB may be a narrow band regardless of the band of the signal V (t). The load driving based on the AC component V (t) of the signal is balanced as shown in the above equations (5) and (6) and has no common mode component.

<Second Embodiment>
FIG. 2 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the second embodiment of the present invention.

The driver 1A in FIG. 2 differs from the driver 1 in FIG. 1 in the following points.
First, in the differential drive circuit 2A, a fifth resistor element R5 is connected between the source of the first transistor and the source of the second transistor Q2, and the source of the third transistor Q3 and the fourth transistor Q4. The sixth resistance element R6 is connected between the sources of the first and second sources.
Second, a first differential amplifier 6 and a second differential amplifier 7 are provided in place of the DACs 3 and DAC4.
The first differential amplifier 6 receives the analog differential voltage, generates the first drive target voltage V1 and the second drive target voltage V2, and uses the generated first drive target voltage V1 to the first circuit 21. And the second drive target voltage V 2 is supplied to the second circuit 22.
The second differential amplifier 7 receives the analog differential voltage with the first differential amplifier 6, generates the third drive target voltage V3 and the fourth drive target voltage V4, and generates the generated third drive. The target voltage V3 is supplied to the third circuit 23, and the fourth drive target voltage V4 is supplied to the fourth circuit 24.

The first differential amplifier 6 includes NMOS transistors Q61 and Q62, which are second conductivity type field effect transistors, resistance elements RA1, RA2 and R61, and current sources I61 and I62.
The source of the NMOS transistor Q61 is connected to the current source I61, the drain is connected to the power supply potential source VDD via the resistor element RA1, and the gate is connected to the supply line of the analog differential voltage VinP.
The source of the NMOS transistor Q62 is connected to the current source I62, the drain is connected to the power supply potential source VDD via the resistor element RA2, and the gate is connected to the supply line of the analog differential voltage VinN.
A resistance element R61 is connected between the source of the NMOS transistor Q61 and the source of the NMOS transistor Q62.

The second differential amplifier 7 includes PMOS transistors Q71 and Q72 which are field effect transistors of the first conductivity type, resistance elements RA3, RA4 and R71, and current sources I71 and I72.
The source of the PMOS transistor Q71 is connected to the current source I71, the drain is connected to the reference potential source VSS (for example, the ground potential GND) via the resistor element RA1, and the gate is connected to the supply line of the analog differential voltage VinP. .
The source of the PMOS transistor Q72 is connected to the current source I72, the drain is connected to the reference potential source VSS via the resistor element RA3, and the gate is connected to the supply line of the analog differential voltage VinN.
A resistance element R71 is connected between the source of the NMOS transistor Q71 and the source of the NMOS transistor Q72.

In this example, the signal to be driven to the output is given by an analog differential voltage VinP-VinN.
This voltage is converted into first to fourth drive target voltages V1 to V4 by the first and second differential amplifiers 6 and 7.
In order for the first differential amplifier 6 and the second differential amplifier 7 to maintain good linearity, the peak values of the drain current ratios of the differential pair transistors Q61 and Q62 and Q71 and Q72 cannot be made very large. .
For example, if the current ratio is 3: 1, the maximum current is supplied to the load if the differential drive circuit 2 does not have the fifth resistance element R5 and the sixth resistance element R6, as in the first embodiment. The current ratio between the first transistor Q1 and the second transistor Q2 at the moment is also 3: 1. As a result, the ratio of the current consumed by the differential drive circuit (output circuit) to the current that can be extracted as output is 4: 2.
Since the output is a circuit that supplies a large current to the load, it is a waste of power that the output circuit always consumes twice the maximum drive current.

In the second embodiment, the fifth resistor R5 that short-circuits the sources of the first transistor Q1 and the second transistor Q2, and the first that short-circuits the sources of the third transistor Q3 and the fourth transistor Q4. 6 resistive elements R6.
Since a potential difference of 2 V (t) is applied to these resistance elements R5 and R6, the current ratio between the first transistor Q1 and the second transistor Q2 and the current ratio between the third MMOS transistor Q3 and the fourth transistor Q4 are as follows. The current ratio of the transistors in the differential amplifiers 6 and 7 is exceeded.
As a result, since the current that can be supplied to the load is increased, the current consumption of the output circuit for obtaining the same drive current is reduced, and the power efficiency is improved.

The following example shows how the insertion of the fifth resistor element R5 and the sixth resistor element R6 improves the current efficiency of the differential drive circuit 2A.
Here, the value of the first to fourth resistance elements R1 to R4 is R (Ω), and the value of the fifth and sixth resistance elements R5 and R6 is r (Ω).

First, consider a case where the fifth and sixth resistance elements R5 and R6 are not provided.
Temporarily, the potentials of the third drive target voltage V3 and the fourth drive target voltage V4, that is, the source voltage S3 of the third transistor and the potential of the source voltage S4 of the fourth transistor Q4 are the maximum value 0.6 (V). Suppose that it is given by a waveform having a minimum value of 0.2 (V).
The reason why the minimum value cannot be lowered to the ground potential GND is to keep the input / output linearity of the preceding circuit good.

At the moment when the source voltage S3 is the minimum voltage 0.2 (V), the current that the third transistor Q3 draws from the drain and flows through the source to the third resistance element R3 is 0.2 / R (A). Since the source voltage S4 becomes the maximum voltage 0.6 (V) at the same time, the current that the fourth NMOS transistor Q4 draws from the drain and flows through the source to the fourth resistance element R4 is 0.6 / R (A). is there.
In the circuit of this embodiment, the current discharged from the drains of the first transistor Q1 and the second transistor Q2 at this moment is 0.6 / R (A) from the first transistor Q1, and the second transistor It is designed so that the current from Q2 is 0.2 / R (A).
As a result, the current that can be supplied to the load is 0.4 / R (A), which is the difference that the third transistor Q3 cannot be drawn by being discharged from the first transistor Q1.
This is equal to the difference that the second transistor Q2 could not cover in the current that the fourth transistor Q4 sucks.
On the other hand, since the total current flowing through the output circuit is 0.8 / R (A), the current to drive the load is half of the total current consumption.

Next, consider the case where there are fifth and sixth resistance elements R5 and R6.
Here, the maximum voltage and the minimum voltage of the source voltage S3 of the third transistor Q3 and the source voltage S4 of the fourth transistor Q4 are also 0.6 (V) and 0.2 (V).
The current flowing from the drain to the source of the third transistor Q3 at the moment when the source voltage S3 is the minimum voltage and the source voltage S4 is the maximum voltage has the following value.
That is, the current flowing from the drain to the source of the third transistor Q3 is from 0.2 / R (A) flowing through the source to, for example, the ground potential GND, through the sixth resistor element R6, and the third transistor Q3. The value is obtained by subtracting the current 0.4 / r (A) supplied to the source.
At the same time, the current flowing from the drain to the source of the fourth transistor Q4 is the current 0.6 / R (A) flowing through the fourth resistance element R4 to the current 0.4 / r (A) flowing through the sixth resistance element R6. ) Is added.

Since the current flowing out of the drain of the first transistor Q1 is the same as the current drawn in by the drain of the fourth transistor Q4, the current flowing into the load from the connection point between the first transistor Q1 and the third transistor Q3 is 0. 4 / R + 0.8 / r (A).
Since the current flowing out from the drain of the second transistor Q2 is the same as the current drawn by the drain of the third transistor Q3, the current flowing from the load to the connection point of the second transistor Q2 and the fourth transistor Q4 is also 0. 4 / R + 0.8 / r (A).
At this time as well, the total current consumption of the output circuit is 0.8 / R (A), which is the same as when the fifth resistance element R5 and the sixth resistance element R6 are not present, but the current that can be passed through the load is 0. 8 / r (A) increase.
In calculation, when r = 2R, the load driving current becomes equal to the circuit consumption current, and the total consumption current can be contributed to the drive. However, in reality, the fact that the transistor current becomes zero means that the source potential and the target This is not preferable because a feedback loop for matching potentials is opened. The resistance value r is adjusted so that at least a current for maintaining the feedback loop is left in the transistor.

<Third Embodiment>
FIG. 3 is a diagram illustrating a configuration example of a communication apparatus according to the third embodiment of the present invention.
The communication apparatus 100 of FIG. 3 has a driver including a differential drive circuit according to an embodiment of the present invention in a transmitter.

The communication device 100 includes transmitters 120 and 130 disposed on both ends of the differential transmission path 110, and is configured to be capable of bidirectional communication.
The transmitters 120 and 130 include the differential drive circuits 2 and 2A of the first or second embodiment described above.
The communication apparatus 100 includes receivers 140 and 150 in parallel with the transmitters 120 and 130 with respect to the differential transmission path 110, respectively.
The differential transmission line 110 is connected to a terminating resistor Rterm at both ends.

Since the differential drive circuit according to the embodiment of the present invention can output the same current as the target current to the load without being influenced by the voltage of the load, it does not interfere with the output state of the transmitter at the other end.
Therefore, a beautiful sum signal of the signals to be output from the transmitters 120 and 130 at both ends is generated in the load.
The receivers 140 and 150 provided in parallel with the transmitters 120 and 130 at both ends of the differential transmission line 110 subtract the target output of the parallel transmitters 120 and 130 from the sum signal generated in the load, thereby transmitting at the other end. The signal of the instrument can be obtained.

As described above, according to the present embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q1 to Q4, which are output transistors, with the drive target voltage value is provided, the target can be obtained even if there is a disturbance in the drain potential. Current can be output accurately.
This is because, for example, an accurate output current can be obtained regardless of the received waveform in bidirectional multiplexing as is done in Ethernet (registered trademark) 1000BASE-T, and the accurate sum signal of the transmitted and received signals is not distorted. There is an advantage that it can be generated.

Moreover, according to this embodiment, the following effects can be acquired.
Even if the gate voltage-drain current characteristic of a MOS transistor (field effect transistor) is non-linear or is different between PMOS and NMOS, a differential signal having no common mode component can be output.
In this embodiment, since the linearity of the drive target voltage and the output voltage given as input is good, it is possible to correctly send a waveform that has been strictly adjusted to limit the band to the load.

Furthermore, according to the present embodiment, the ratio of the load driving current to the consumption current of the output stage can be increased, and there is an advantage that the power efficiency is excellent.
Further, it is possible to accurately output a current proportional to the target drive voltage regardless of the load condition. By observing the voltage of the load and subtracting a constant multiple of the target drive current by calculation, it can be identified that the second drive circuit applies current to the load. This makes it possible to perform two-way communication with a single load, that is, a transmission line.
In addition, the differential drive circuit of this embodiment has only one transistor and one resistance element between the output terminal (output node), the reference potential VSS (for example, the ground potential GND), and the power supply potential VDD.
This operates at a lower voltage than a circuit disclosed in Patent Document 1 in which a current source transistor and a differential transistor are stacked vertically.

The driver including the differential drive circuit has been described as the first and second embodiments, and the communication apparatus including the driver has been described as the third embodiment.
Hereinafter, another configuration example of the driver 1 including the differential drive circuit according to the first embodiment, another configuration example of the driver 1A including the differential drive circuit according to the second embodiment, and the third Another configuration example of the communication apparatus 100 according to the embodiment will be described.

  First, other configuration examples of the driver 1 including the differential drive circuit according to the first embodiment will be described as fourth to tenth embodiments with reference to FIGS. 4 to 11.

<Fourth Embodiment>
FIG. 4 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the fourth embodiment of the present invention.

  The driver 1B according to the fourth embodiment is different from the driver 1 according to the first embodiment in that the drive of the load is performed using only the pull-up circuit as the first drive system. is there.

Specifically, the driver 1B in FIG. 4 uses PMOS transistors Q1, Q2, first and second circuits 21, 22, resistance elements R1, R2, and DAC3 among the components of the driver 1 in FIG. To drive the load.
The drains of the PMOS transistors Q1 and Q2 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

  According to the fourth embodiment, since the negative potential (NFB) for matching the source potentials of the transistors Q1 and Q2, which are output transistors, to the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.

<Fifth Embodiment>
FIG. 5 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the fifth embodiment of the present invention.

  The driver 1C according to the fifth embodiment is different from the driver 1 according to the first embodiment in that the load is driven using only a pull-down circuit as a second drive system. .

Specifically, the driver 1C in FIG. 5 uses NMOS transistors Q3 and Q4, third and fourth circuits 23 and 24, resistance elements R3 and R4, and DAC4 among the components of the driver 1 in FIG. To drive the load.
The drains of the NMOS transistors Q3 and Q4 are connected to the load resistors Rload3 and Rload4, respectively, and the load resistors Rload3 and Rload4 are connected to the power source 9 of the bias voltage Vbias.

  According to the fifth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q3 and Q4, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.

<Sixth Embodiment>
FIG. 6 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the sixth embodiment of the present invention.

  The driver 1D according to the sixth embodiment is different from the driver 1 according to the first embodiment in that the driver 1D is output according to numerical values Ddiff and Dcom to which a differential voltage and an in-phase voltage are applied.

Therefore, pull-up side DAC 3 is separated into two first DACs 3-1 and second 3-2, and pull-down side DAC 4 is separated into two third DACs 4-1 and fourth DAC 4-2. ing.
Further, adders / subtracters 10, 11, 12, and 13 for adding and subtracting the numerical values Ddiff and Dcom are arranged at the input stages of the DACs 3-1, 3-2, 4-1, and 4-2, and the DACs 3-1, 3 and 3 are arranged. Different numerical values are input to 2, 4-1, 4-2.
Note that the first and second output nodes NO1, NO2 of the differential drive circuit 2D are connected to the load resistors Rload1, Rload2, respectively, and the load resistors Rload1, Rload2 are connected to the power source 8 of the bias voltage Vbias.

The adder / subtractor 10 receives a numerical value Ddiff as a negative input, receives a numerical value Dcom as a positive input, obtains an N-bit numerical value [Dcom−Ddiff] as a second addition / subtraction result by performing an operation on the input, and this numerical value [Dcom -Ddiff] is supplied to the DAC 3-2.
The adder / subtractor 11 receives a numerical value Ddiff as a first positive input and a numerical value Dcom as a second positive input, and obtains an N-bit numerical value [Dcom + Ddiff] as a first addition / subtraction result by performing an operation on the input. [Dcom + Ddiff] is supplied to the DAC 3-1.
The adder / subtractor 12 receives a numerical value Ddiff as a positive input and a numerical value Dcom as a negative input, and obtains an N-bit numerical value [−Dcom + Ddiff] as a fourth addition / subtraction result by performing an operation on the input, and this numerical value [−Dcom + Ddiff]. ] Is supplied to the DAC 4-2.
The adder / subtractor 13 receives a numerical value Ddiff as a first negative input, receives a numerical value Dcom as a second negative input, and obtains an N-bit numerical value [−Dcom−Ddiff] as a third addition / subtraction result by calculating the input. The numerical value [-Dcom-Ddiff] is supplied to the DAC 4-1.

The DAC 3-1 includes switches SW3-10 to SW3-1N-1 and current sources I3-10 to I3-1N.
As shown in FIG. 6, each of the current sources I3-10 to I3-1N-1 and the switches SW3-10 to SW3-1N-1 includes a power supply potential source VDD and a first supply line LV1. Are connected in series. The current source I3-1N is connected between the power supply potential source VDD and the first supply line LV1.
Then, a numerical value [Dcom-Ddiff] for controlling the current value is supplied to the control gates of the current sources I3-10 to I3-1N.

The DAC 3-2 includes switches SW3-20 to SW3-2N-1 and current sources I3-20 to I3-2N.
As shown in FIG. 6, each of the current sources I3-20 to I3-2N-1 and the switches SW3-20 to SW3-2N-1 includes a power supply potential source VDD and a second supply line LV2, respectively. Are connected in series. The current source I3-2N is connected between the power supply potential source VDD and the second supply line LV2.
Then, a numerical value [Dcom + diff] for controlling the current value is supplied to the control gates of the current sources I3-20 to I3-2N.

The DAC 4-1 includes switches SW4-10 to SW4-1N-1 and current sources I4-10 to I4-1N.
As shown in FIG. 6, each of the current sources I4-10 to I4-1N-1 and the switches SW4-10 to SW4-1N-1 includes a power supply potential source VDD and a third supply line LV3. Are connected in series. The current source I4-1N is connected between the power supply potential source VDD and the third supply line LV3.
Then, a numerical value [-Dcom-Ddiff] for controlling the current value is supplied to the control gates of the current sources I4-10 to I4-1N.

The DAC 4-2 includes switches SW4-20 to SW4-2N-1 and current sources I4-20 to I4-2N.
As shown in FIG. 6, each of the current sources I4-20 to I4-2N-1 and the switches SW4-20 to SW4-2N-1 includes a power supply potential source VDD and a fourth supply line LV4. Are connected in series. The current source I4-2N is connected between the power supply potential source VDD and the fourth supply line LV4.
Then, a numerical value [−Dcom + Ddiff] for controlling the current value is supplied to the control gates of the current sources I4-20 to I4-2N.

In the driver 1D, the drive target potential V1 is applied to the resistor element R1 and the PMOS transistor Q1 that pull up the first output node NO1 (output VoutP), and the drive target potential V3 is applied to the resistor element R3 and the NMOS transistor Q3 that pull down. It is done.
The drive target potential V2 is applied to the resistor element R2 and the PMOS transistor Q2 that pull up the second output node NO2 (output VoutN), and the drive target potential V4 is applied to the resistor element R4 and the NMOS transistor Q4 that pull down.

The drive target potentials V1 to V4 are generated by the four DACs 3-1, 3-2, 4-1, and 4-2.
The digital inputs to the DACs 3-1, 3-2, 4-1, 4-2 are [Dcom + Ddiff], [Dcom-Ddiff], [−Dcom-Ddiff], [− for the two numerical data Ddiff and Dcom. Dcom + Ddif] is given.

  Here, if the analog voltage values corresponding to Ddiff and Dcom are Vdiff and Vcom, the following relationship is established.

[Equation 6]
VDD-V1 = + Vdiff + Vcom
VDD-V2 = -Vdiff + Vcom
V3-GND = -Vdiff-Vcom
V4-GND = + Vdiff-Vcom

  When the resistance values of the resistance elements R1 to R4 are all R, the output current IQ1 of the PMOS transistor Q1, the output current IQ3 of the NMOS transistor Q3, and the current IVoutP from the first output node NO1 to the load are given by the following equations.

[Equation 7]
IQ1 = (+ Vdiff + Vcom) / R
IQ3 = (− Vdiff−Vcom) / R
IVoutP = 2 · (+ Vdiff + Vcom) / R

  Similarly, when all the resistance values of the resistance elements R1 to R4 are R, the output current IQ2 of the PMOS transistor Q2, the output current IQ4 of the NMOS transistor Q4, and the current IVoutN from the second output node NO2 to the load are given by the following equations. It is done.

[Equation 8]
IQ2 = (− Vdiff + Vcom) / R
IQ4 = (+ Vdiff−Vcom) / R
IVoutN = 2 · (−Vdiff + Vcom) / R

  The potential VoutP on the first output node NO1 side and the potential VoutN on the second output node NO2 side are given by the following equations.

[Equation 9]
VoutP = Vbias + 2 · Rload · (+ Vdiff + Vcom) / R
VoutN = Vbias + 2 · Rload · (−Vdiff + Vcom) / R

  Therefore, the differential voltage VDPN of the outputs VoutP and VoutN and the common-mode voltage VIPN are as follows.

[Equation 10]
VDPN = 4 ・ Rload ・ Vdiff / R
VIPN = Vbias + 2 ・ Rload ・ Vcom / R

This indicates that in the circuit of FIG. 6, the output differential voltage VDPN and the common-mode voltage VIPN are output according to the numerical values Ddiff and Dcom.
Even if such common-mode voltage drive is taken into account, the circuit of the present invention flows through the resistance elements R1 to R4, that is, the current output from the transistors Q1 to Q4 is accurately controlled. It is output accurately without being modulated or distorted depending on the size of.

According to the sixth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q1 to Q4, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.
Even if the gate voltage-drain current characteristics of a MOS transistor (field effect transistor) are non-linear, or even if the characteristics are different between PMOS and NMOS, a differential signal having no common mode component can be output. it can.
In the sixth embodiment, since the linearity of the drive target voltage and the output voltage given as input is good, it is possible to correctly send a waveform that has been strictly adjusted to limit the band to the load. is there.
Furthermore, according to the sixth embodiment, the ratio of the load driving current to the consumption current of the output stage can be increased, and there is an advantage that the power efficiency is excellent.
Further, it is possible to accurately output a current proportional to the target drive voltage regardless of the load condition.
Further, the differential output can be output accurately without being modulated or distorted depending on the magnitude of the common-mode output.

<Seventh Embodiment>
FIG. 7 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the seventh embodiment of the present invention.

  The driver 1E according to the seventh embodiment is different from the driver 1D according to the sixth embodiment in that the drive of the load is performed using only the pull-up circuit as the first drive system. is there.

Specifically, the driver 1E shown in FIG. 7 includes, among the components of the driver 1D shown in FIG. 6, PMOS transistors Q1 and Q2, first and second circuits 21 and 22, resistor elements R1 and R2, DACs 3-1 and DAC3-1. 3-2 and the adder / subtracters 10 and 11 are used to drive the load.
The drains of the PMOS transistors Q1 and Q2 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

According to the seventh embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q1 and Q2 that are output transistors to the drive target voltage value is provided, the target current can be obtained even if the drain potential is disturbed. It can output accurately.
Further, the output differential voltage VDPN and the common-mode voltage VIPN can be output according to the numerical values Ddiff and Dcom.
In this case, the differential output can be output accurately without being modulated or distorted by the magnitude of the in-phase output.

<Eighth Embodiment>
FIG. 8 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the eighth embodiment of the present invention.

  The driver 1F according to the eighth embodiment is different from the driver 1D according to the sixth embodiment in that the load is driven by using only a pull-down circuit as a second drive system. .

Specifically, the driver 1D of FIG. 8 includes NMOS transistors Q3 and Q4, third and fourth circuits 23 and 24, resistance elements R3 and R4, DAC 4-1, DAC 4-1, among the components of the driver 1D of FIG. 4-2 and the adder / subtracters 12 and 13 are used to drive the load.
The drains of the NMOS transistors Q3 and Q4 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

According to the eighth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q3 and Q4, which are output transistors, to the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.
Further, the output differential voltage VDPN and the common-mode voltage VIPN can be output according to the numerical values Ddiff and Dcom.
In this case, the differential output can be output accurately without being modulated or distorted by the magnitude of the in-phase output.

<Ninth Embodiment>
FIG. 9 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the ninth embodiment of the present invention.

  The driver 1G of the ninth embodiment is different from the driver 1F of the eighth embodiment in that it has a DAC stabilizing circuit 30 for stabilizing the output.

The DAC stabilization circuit 30 includes PMOS transistors QA and QB, operational amplifiers A31 and A32, resistance elements RA31 and RA32, a reference resistance element Rext31, and a power supply V31.
The source of the PMOS transistor QA is connected to the power supply potential source VDD, and the drain is connected to one end of the resistor element RA31 and the non-inverting input terminal (+) of the operational amplifier A31. The other end of the resistor element RA31 is connected to the reference potential source VSS.
The gate of the PMOS transistor QA is connected to the output of the operational amplifier A31.
The source of the PMOS transistor QB is connected to one end of the reference resistance element Rext31 and the inverting input terminal (−) of the operational amplifier A32.
The drain of the PMOS transistor QB is connected to one end of the resistance element RA32 and the inverting input terminal (−) of the operational amplifier A31.
The gate of the PMOS transistor QB is connected to the output of the operational amplifier A32. The other end of the reference resistor element Rext31 is connected to the power supply potential source VDD, and the other end of the resistor element RA32 is connected to the reference potential source VSS.
The non-inverting input (+) of the operational amplifier A32 is connected to the power supply V31 that supplies the reference voltage Vref.

The DAC 4-1 includes switches SW 4-10 to SW 4-1 N- 1 and PMOS transistors Q 4-10 to Q 4-1 N as current sources.
As shown in FIG. 9, the PMOS transistors Q4-10 to Q4-1N-1 and the switches SW4-10 to SW4-1N-1 each include a power supply potential source VDD and a third supply line LV3. Are connected in series. The PMOS transistor Q4-1N has a source connected to the power supply potential source VDD and a drain connected to the third supply line LV3.
The gates of the PMOS transistors Q4-10 to Q4-1N as current sources are connected to the output of the operational amplifier A31 of the replica circuit 30.

The DAC 4-2 includes switches SW4-20 to SW4-2N-1 and PMOS transistors Q4-20 to Q4-2N as current sources.
As shown in FIG. 9, the PMOS transistors Q4-20 to Q4-2N-1 and the switches SW4-20 to SW4-2N-1 each have a pair of power supply potential source VDD and fourth supply line LV4. Are connected in series. The PMOS transistor Q4-2N has a source connected to the power supply potential source VDD and a drain connected to the fourth supply line LV4.
The gates of the PMOS transistors Q4-20 to Q4-2N as current sources are connected to the output of the operational amplifier A31 of the replica circuit 30.

In the stabilization circuit 30, the transistor QA and the resistance element RA31 function as replicas of the DACs 4-1 and 4-2 that generate the drive target voltages V3 and V4. The stabilization circuit 30 including this replica outputs the same output VA as when a specific numerical value input is given to the DACs 4-1 and 4-2.
The output VA is subjected to negative feedback (NFB) so that the relationship of the following equation is obtained.

[Equation 11]
VA = Vref · (RA / Rext)

Therefore, the output when the DACs 4-1 and 4-2 are input with specific numerical values is also VA.
Since the transconductance of the output stage is 1 / R where R = R3 = R4, the output potential is as follows.

[Equation 12]
VA / Rload / R = Vref / (RA / R) / (Rload / Rext)

Here, the resistance element RA31 and the resistance elements R3 and R4 are both resistors of the same integrated circuit, and the ratio is substantially constant. If both the load resistances Rload1 and 2 and the reference resistance element Rext31 are high-precision resistors outside the integrated circuit, the ratio Is also constant.
Therefore, the output when a specific numerical value is input to the DACs 4-1 and 4-2 is a constant multiple of the reference voltage Vref.
If the reference voltage Vref is a stable voltage given by a band gap reference output or a trimmed bias generation circuit, the driver 1G of the ninth embodiment has a stable output when a specific numerical value input is given. It will be.

  A similar stabilization circuit can be applied to the driver 1 in FIG. 1, the driver 1B in FIG. 4, the driver 1C in FIG. 5, the driver 1D in FIG. 6, and the driver 1E in FIG.

According to the ninth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q3 and Q4, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.
Further, the output differential voltage VDPN and the common-mode voltage VIPN can be output according to the numerical values Ddiff and Dcom.
In this case, the differential output can be output accurately without being modulated or distorted by the magnitude of the in-phase output.
In addition, the output when a specific numerical input is given can be stabilized.

<Tenth Embodiment>
FIG. 10 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the tenth embodiment of the present invention.

The difference between the driver 1H of the tenth embodiment and the driver 1C of the fifth embodiment is that a multiplier 14 that multiplies the coefficient C in the preceding stage of the DAC so that the output for a specific numerical input becomes a constant value. It is to have done.
The coefficient C is generated by a stabilization circuit 40 having a DAC replica function.

The stabilization circuit 40 includes a PMOS transistor Q41, resistance elements RA41 and RA42, a reference resistance element Rext41, operational amplifiers A41 and A42, and a power source V41.
The coefficient generation circuit 40 further includes switches SW41-0 to SW41-N-1, current sources I41-0 to I41-N, a supply line LV41, a multiplier 41, and a state machine 42.

The source of the PMOS transistor Q41 is connected to one end of the reference resistance element Rext41 and the inverting input terminal (−) of the operational amplifier A41.
The drain of the PMOS transistor Q41 is connected to one end of the resistor element RA41 and the inverting input terminal (−) of the operational amplifier A42.
The gate of the PMOS transistor Q41 is connected to the output of the operational amplifier A41. The other end of the reference resistance element Rext41 is connected to the power supply potential source VDD, and the other end of the resistance element RA41 is connected to the reference potential source VSS.
The non-inverting input (+) of the operational amplifier A41 is connected to the power supply V41 that supplies the reference voltage Vref.
The non-inverting input (−) of the operational amplifier A42 is connected to the supply line LV41. The resistor element RA42 has one end connected to the supply line LV41 and the other end connected to the reference potential source VSS.
As shown in FIG. 10, each of the current sources I41-0 to I41-N-1 and the switches SW41-10 to SW41-N-1 is set between the power supply potential source VDD and the supply line LV41. Connected in series. The current source I41-N is connected between the power supply potential source VDD and the supply line LV41.
Then, N-bit data obtained by multiplying a fixed value by a coefficient C for controlling on / off is supplied to the control gates of the switches SW41-0 to SW4-N-1.

The multiplier 41 supplies N-bit data obtained by multiplying the fixed value by the coefficient C to the control gates of the switches SW41-0 to SW4-N-1.
The state machine 42 scans the coefficient C with the minimum value and searches for a value at which the output level P of the operational amplifier A42 as a comparator changes from 0 to 1. The state machine 42 supplies the searched coefficient C to the multipliers 42 and 14.

  FIG. 11 is a flowchart showing an operation of an example of a state machine of the stabilization circuit according to the tenth embodiment.

First, the state machine 42 sets the coefficient C to the minimum value (ST1).
Next, the state machine 42 determines whether the output P of the operational amplifier A42 is 0 or 1 (ST2).
If it is determined in step ST2 that the output P is 0, the state machine 42 determines whether or not the coefficient C is the maximum value (ST3).
If it is determined in step ST3 that the coefficient C is not the maximum value, the state machine 42 adds 1 to the value of the coefficient C and repeats the processing from step ST2.
When it is determined in step ST2 that the output P is 1, the state machine 42 ends the process.
The state machine 42 also ends the process when it is determined in step ST3 that the coefficient C has reached the maximum value.

As described above, the state machine 42 scans the coefficient C from the minimum value and finds the C value at which the comparator output changes from 0 to 1.
The output of the stabilization circuit 40 including the DAC replica function to which the value obtained by multiplying the coefficient C by the fixed value Fixed is input is as follows.

[Equation 13]
VA = Vref · (RA / Rext)

  The differential drive circuit 2H, which is an output circuit to which the same numerical input is applied, also outputs the same voltage as VA to the drive target voltage V3 or V4 because the numerical value is multiplied by the coefficient C at the input of the DAC 4. At that time, the output voltage is as follows with R = R3 = R4, and is thus stabilized at a constant value.

[Formula 14]
VA · (Rload / R) = Vref · (RA / R) · (Rload / Rext)

  A similar stabilization circuit can be applied to the driver 1 in FIG. 1, the driver 1B in FIG. 4, the driver 1C in FIG. 5, the driver 1D in FIG. 6, and the driver 1E in FIG.

According to the tenth embodiment, since the negative potential (NFB) for matching the source potentials of the transistors Q3 and Q4, which are output transistors, to the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.
Further, the output differential voltage VDPN and the common-mode voltage VIPN can be output according to the numerical values Ddiff and Dcom.
In this case, the differential output can be output accurately without being modulated or distorted by the magnitude of the in-phase output.
In addition, the output when a specific numerical input is given can be stabilized.

The other configuration example of the driver 1 including the differential drive circuit according to the first embodiment has been described above.
Next, another configuration example of the driver 1A including the differential drive circuit according to the second embodiment will be described as the 11th to 16th embodiments with reference to FIGS.

<Eleventh embodiment>
FIG. 12 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the eleventh embodiment of the present invention.

  The driver 1I according to the eleventh embodiment is different from the driver 1A according to the second embodiment in that the drive of the load is performed using only the pull-up circuit as the first drive system. is there.

Specifically, the driver 1I in FIG. 12 includes PMOS transistors Q1 and Q2, first and second circuits 21 and 22, resistance elements R1 and R2, and a differential amplifier among the components of the driver 1A in FIG. 6 is used to drive the load.
The drains of the PMOS transistors Q1 and Q2 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

  According to the eleventh embodiment, since the negative potential (NFB) for matching the source potentials of the transistors Q1 and Q2, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.

<Twelfth Embodiment>
FIG. 13 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the twelfth embodiment of the present invention.

  The driver 1J according to the twelfth embodiment is different from the driver 1A according to the second embodiment in that the load is driven using only a pull-down circuit as a second drive system. .

Specifically, the driver 1J in FIG. 13 includes NMOS transistors Q3 and Q4, third and fourth circuits 23 and 24, resistance elements R3 and R4, and a differential amplifier among the components of the driver 1A in FIG. 7 is used to drive the load.
The drains of the NMOS transistors Q3 and Q4 are connected to the load resistors Rload3 and Rload4, respectively, and the load resistors Rload3 and Rload4 are connected to the power source 9 of the bias voltage Vbias.

  According to the twelfth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q3 and Q4, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately. At the same time, the intended common-mode voltage can be accurately output.

<13th Embodiment>
FIG. 14 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to a thirteenth embodiment of the present invention.

The driver 1K according to the thirteenth embodiment is different from the driver 1A according to the second embodiment in that it has an offset adding circuit 50 that gives an offset to the drive target potentials V1 to V4.
Note that the first and second output nodes NO1, NO2 of the differential drive circuit 2K are connected to load resistors Rload1, Rload2, respectively, and the load resistors Rload1, Rload2 are connected to a power source 8 of a bias voltage Vbias.

  The offset addition circuit 50 includes a differential amplifier 51, current mirror circuits 52 and 53, and a resistance element R51.

The differential amplifier 51 includes PMOS transistors QP51 and QP52, a resistance element R51, and current sources I51 and I52.
The current mirror circuit 52 includes NMOS transistors QN51 to QN53 and a current source I53.
The current mirror circuit 53 includes NMOS transistors QN54 and QN55, PMOS transistors QP53 to QP55, and a current source I54.

The source of the PMOS transistor QP51 of the differential amplifier 51 is connected to the current source I51, and the drain is connected to the drain of the NMOS transistor QN54 of the current mirror circuit 52 and the gates of the NMOS transistors QN54 and QN55.
The source of the PMOS transistor QP52 is connected to the current source I52, and the drain is connected to the drain of the NMOS transistor QN51 of the current mirror circuit 52.
A resistance element R51 is connected between the source of the PMOS transistor QP51 and the source of the PMOS transistor QP52.
The gate of the PMOS transistor QP51 is connected to the supply line of the voltage VcomP. The gate of the PMOS transistor QP52 is connected to the supply line of the voltage VcomN.

In the current mirror circuit 52, the drain of the NMOS transistor QN51 is connected to the current source I53, the gate thereof, the gates of the NMOS transistors QN52 and QN53, and the source is connected to the reference potential source VSS.
The source of the NMOS transistor QN52 is connected to the reference potential source VSS, and the drain is connected to the output portion of the drive target potential V1 of the first differential amplifier 6, that is, the connection point between the resistor element RA1 and the drain of the NMOS transistor Q61. ing.
The source of the NMOS transistor QN53 is connected to the reference potential source VSS, and the drain is connected to the output portion of the drive target potential V2 of the first differential amplifier 6, that is, the connection point between the resistor element RA2 and the drain of the NMOS transistor Q62. ing.

In the current mirror circuit 53, the sources of the NMOS transistors QN54 and QN55 are connected to the reference potential source VSS.
The drain of the NMOS transistor QN55 is connected to the drain of the PMOS transistor QP53 and the current source I54.
The source of the PMOS transistor QP53 is connected to the power supply potential source VDD, and the drain is connected to its own gate and the gates of the PMOS transistors QP54 and QP55.
The source of the PMOS transistor QP54 is connected to the power supply potential source VDD, and the drain is connected to the output portion of the drive target potential V4 of the second differential amplifier 7, that is, the connection point between the resistor element RA4 and the drain of the PMOS transistor Q72. ing.
The source of the PMOS transistor QP55 is connected to the power supply potential source VDD, and the drain is connected to the output portion of the drive target potential V3 of the second differential amplifier 7, that is, the connection point between the resistor element RA3 and the drain of the PMOS transistor Q71. ing.

In the driver 1K, an offset is given to the drive target potentials V1 to V4 by the differential amplifier 51 that is the added differential pair.
When the signal given by [VcomP−VconN] is more positive than when the voltages VcomP and VcomN given to the differential amplifier 51 are balanced, the currents flowing through the first and second differential amplifiers 6 and 7 are Change.
That is, when the signal given by [VcomP−VconN] is positive, the current flowing through the resistance elements RA1 and RA2 of the first differential amplifier 6 increases, and the resistance elements RA3 and RA4 of the second differential amplifier 7 are increased. The flowing current decreases.
As a result, the drive target potential V1 and the drive target potential V2 are lowered, the current flowing through the resistance elements R1 and R2 of the differential drive circuit 2K is increased, and the drive target potential V3 and the drive target potential V4 are lowered. The current flowing through R4 decreases.
That is, the pull-up current output from the first and second transistors Q1 and Q2 increases and the pull-down current output from the third and fourth transistors Q3 and Q4 decreases, so that the in-phase of the outputs VoutP and VoutN The voltage rises.
However, the output current increments of the first and second transistors Q1 and Q2 are the same, and the output decrease of the third and fourth transistors Q3 and Q4 is also the same, so there is no change in the differential voltage.
That is, this circuit also shows that an accurate differential output is possible regardless of the magnitude of the common-mode voltage.

According to the thirteenth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q1 to Q4, which are output transistors, with the drive target voltage value is provided, the target current can be obtained even if there is a disturbance in the drain potential. It can output accurately.
Even if the gate voltage-drain current characteristics of a MOS transistor (field effect transistor) are non-linear, or even if the characteristics are different between PMOS and NMOS, a differential signal having no common mode component can be output. it can.
Further, in the thirteenth embodiment, since the linearity of the drive target voltage and the output voltage given as input is good, it is possible to correctly send a waveform that has been strictly adjusted to limit the band to the load. is there.
Furthermore, according to the thirteenth embodiment, the ratio of the load driving current to the consumption current of the output stage can be increased, and there is an advantage that the power efficiency is excellent.
Further, it is possible to accurately output a current proportional to the target drive voltage regardless of the load condition.
Further, the differential output can be output accurately without being modulated or distorted depending on the magnitude of the common-mode output.

<Fourteenth embodiment>
FIG. 15 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the fourteenth embodiment of the present invention.

  The driver 1L according to the fourteenth embodiment is different from the driver 1K according to the thirteenth embodiment in that the driving of the load is performed using only the pull-up circuit as the first driving system. is there.

Specifically, the driver 1L in FIG. 15 includes PMOS transistors Q1 and Q2, first and second circuits 21 and 22, resistance elements R1 and R2, and a differential amplifier 6 among the components of the driver 1K in FIG. The differential amplifier 51 and the current mirror circuit 52 are used to drive the load.
The drains of the PMOS transistors Q1 and Q2 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

  However, the drain of the PMOS transistor QP51 of the differential amplifier 51 is connected to the reference potential source VSS.

According to the fourteenth embodiment, since the negative feedback (NFB) for matching the source potentials of the transistors Q1 and Q2 that are output transistors to the drive target voltage value is provided, the target current can be obtained even if the drain potential is disturbed. It can output accurately.
Further, the differential output can be output accurately without being modulated or distorted depending on the magnitude of the common-mode output.

<Fifteenth embodiment>
FIG. 16 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the fifteenth embodiment of the present invention.

  The driver 1M according to the fifteenth embodiment is different from the driver 1K according to the thirteenth embodiment in that the load is driven using only a pull-down circuit as a second drive system. .

Specifically, the driver 1M in FIG. 16 includes PMOS transistors Q3 and Q4, third and fourth circuits 23 and 24, resistance elements R3 and R4, and a differential amplifier 7 among the components of the driver 1K in FIG. The differential amplifier 51 and the current mirror circuit 53 are used to drive the load.
The drains of the PMOS transistors Q1 and Q2 are connected to the load resistors Rload1 and Rload2, respectively, and the load resistors Rload1 and Rload2 are connected to the power source 8 of the bias voltage Vbias.

However, the drain of the PMOS transistor QP52 of the differential amplifier 51 is connected to the reference potential source VSS.
In the current mirror circuit 53, the NMOS transistors QN54 and QN55 of FIG. 14 are not used, and the drain of the PMOS transistor QP51 of the differential amplifier 51 is connected to the current source I54 and the drain of the PMOS transistor QP53.

According to the fifteenth embodiment, since the negative feedback (NFB) that matches the source potentials of the transistors Q1 and Q2 that are output transistors to the drive target voltage value is provided, the target current can be obtained even if the drain potential is disturbed. It can output accurately.
Further, the differential output can be output accurately without being modulated or distorted depending on the magnitude of the common-mode output.

<Sixteenth Embodiment>
FIG. 17 is a circuit diagram showing a configuration example of a driver including a differential drive circuit according to the sixteenth embodiment of the present invention.

The driver 1N of the sixteenth embodiment is configured by adding the following elements to the configuration of the driver 1I of the twelfth embodiment.
That is, in the driver 1N, PMOS transistors QA61 and QA62 for resistance adjustment are connected in parallel with the load resistors RA1 and RA2 of the first-stage differential amplifier 6, and the gate potential Vadj is controlled by the gain adjustment circuit 60.

  The driver 1N has a transconductance circuit at the output stage that outputs a current proportional to the drive target potentials V1 and V2 and inversely proportional to the resistors R1 and R2.

  The consistent gain Gtot from the differential input [VinP−VinN] to the differential amplifier 6 at the first stage to the differential output [VoutP−VoutN] of the differential drive circuit 2N is assumed to be Gamp as the gain of the differential amplifier 6 at the first stage. Is expressed by the following equation.

[Equation 15]
Gtot = Gamp · (1 / R) · Rload

Here, R is a combined resistance value determined by the resistance elements R1, R2, and R12 of the differential drive circuit 2N. Since R is an element in the integrated circuit, the ratio of R to Rload is not constant when the load resistance Rload is placed outside the integrated circuit. The gain of the differential amplifier 6 also varies depending on the element characteristics and temperature of the integrated circuit.
Therefore, the integrated gain has a large manufacturing variation and temperature drift of the integrated circuit.

Therefore, the circuit of FIG. 17 employs the above-described configuration in order to keep the consistent gain Gtot constant.
That is, in the circuit of FIG. 17, an amplification stage (level shifter) 6A is configured by connecting PMOS transistors QA11 and QA12 for resistance adjustment in parallel with the load resistors RA1 and RA2 of the differential amplifier 6 in the first stage.
The circuit of FIG. 17 is configured such that the gate potential Vadj is controlled by the gain adjustment circuit 60.

  FIG. 18 is a circuit diagram showing a first configuration example of the gain adjustment circuit 60 of FIG.

The gain adjustment circuit 60A of FIG. 18 includes a replica circuit 61 of the amplification stage 6A and a reference voltage and offset voltage supply unit (hereinafter referred to as a voltage supply unit) 62.
The gain adjustment circuit 60A further includes an offset addition circuit 63 that adds an offset to the output of the replica circuit 61, and a feedback amplifier (error amplifier) 64 that balances the replica output with the offset.

The replica circuit 61 has a configuration similar to that of the amplification stage 6A.
That is, the replica circuit 61 includes NMOS transistors QN61 and QN62, resistance elements RB1, RB2, and RB61, current sources IB61 and IB62, and PMOS transistors QP61 and QP62.

In the replica circuit 61, the source of the NMOS transistor QN61 is connected to the current source IB61, the drain is connected to one end of the resistance element RB1 and the drain of the PMOS transistor QP61, and a node ND61 is formed by the connection point. The other end of the resistance element RB1 and the source of the PMOS transistor QP61 are connected to the power supply potential source VDD.
The source of the NMOS transistor QN62 is connected to the current source IB62, the drain is connected to one end of the resistor RB2 and the drain of the PMOS transistor QP62, and a node ND62 is formed by the connection point. The other end of the resistance element RB2 and the source of the PMOS transistor QP62 are connected to the power supply potential source VDD.
A resistance element RB61 is connected between the drain of the NMOS transistor QN61 and the drain of the NMOS transistor QN62.
The gates of the NMOM transistors QN61 and QN62 are connected to the reference voltage supply unit of the voltage supply unit 62.
The gates of the PMOS transistors QP61 and QP62 are supplied with the output of the error amplifier 64 fed back.
The output of the error amplifier 64 is given as the gate potential Vadj of the PMOS transistors QA61 and QA62 in the amplification stage 6A.

The voltage supply unit 62 includes a reference voltage source V61, a monitor resistor element Rpoly, a reference resistor element Rext, and operational amplifiers A61 and A62.
The voltage supply unit 62 includes PMOS transistors QP63 to QP66, an NMOS transistor QN63, and output-side resistance elements R62 and R63 for a reference voltage.

One end of the monitor resistance element Rpoly is connected to the non-inverting input terminal (+) of the operational amplifier A61 and the drain of the PMOS transistor QP63, and the other end is connected to the reference potential source VSS (for example, the ground potential GND).
The source of the PMOS transistor QP63 is connected to the power supply potential source VDD, and the gate is connected to the output of the operational amplifier A61.
The source of the PMOS transistor QP 63 is connected to the power supply potential source VDD, the drain is connected to one end of the resistance element R 62, and the connection node ND 63 is connected to the gate of the NMOS transistor QN 61 of the replica circuit 61.
One end of the resistance element R62 is connected to one end of the resistance element R63, and the connection node ND64 is connected to the gate of the NMOS transistor QN62 of the replica circuit 61. The other end of the resistance element R63 is connected to the reference potential source VSS.
The inverting input terminals (−) of the operational amplifiers A61 and A62 are commonly connected to the reference voltage source V61.
One end of the reference resistance element Rext is connected to the non-inverting input terminal (+) of the operational amplifier A62 and the drain of the PMOS transistor QP65. The sources of the PMOS transistors QP65 and QP66 are connected to the power supply potential source VDD, and the gates are connected to the output of the operational amplifier A62.
The drain of the PMOS transistor QP66 is connected to the drain and gate of the NMOS transistor QN63, and the connection node ND65 is connected to the input portion of the offset adding circuit 63.

  The offset voltage adding unit 63 includes PMOS transistors QP67 and QP68, NMOS transistors QN64 and QN65, and resistance elements R64 and R65.

In the offset addition circuit 63, the source of the PMOS transistor QP67 is connected to the power supply potential source VDD, the drain is connected to one end of the resistance element R64, and the gate is connected to the node ND62 on the high output side (VH) of the replica circuit 61. Yes.
The other end of the resistance element R64 is connected to the drain of the NMOS transistor QN64, and the connection node ND66 is connected to the inverting input terminal (−) of the error amplifier 64. The source of the NMOS transistor QN64 is connected to the reference potential source VSS.
The source of the PMOS transistor QP68 is connected to the power supply potential source VDD, the drain is connected to one end of the resistor element R65, and the connection node ND67 is connected to the non-inverting input terminal (+) of the error amplifier 64.
The gate of the PMOS transistor QP 68 is connected to the node ND 61 on the low output side (VL) of the replica circuit 61.
The other end of the resistor element R65 is connected to the drain of the NMOS transistor QN65, and the source of the NMOS transistor QN64 is connected to the reference potential source VSS.
The gates of the NMOS transistors QN64 and QN65 are commonly connected to the node ND65 on the output side of the offset voltage of the voltage supply unit 62.

Here, the reference resistance element Rext is a resistance that is outside the integrated circuit and maintains the ratio with the load resistance with high accuracy, and the monitor resistance element Rpoly is a resistance within the integrated circuit and always maintains an accurate ratio with R.
In the circuit of FIG. 18, a state in which the reference potential Vref is applied to the monitor resistance element Rpoly is realized by negative feedback (NFB).
The current flowing through the monitor resistor element Rpoly in that state flows through the bias resistor element R62 at the input of the differential pair of the replica circuit 61 by the current mirror including the PMOS transistor QP64. As a result, the differential input of the differential amplifier formed by the NMOS transistors QN61 and QN62 of the replica circuit 61 is α · Vref.
Here, α is a ratio of the monitor resistance element Rpoly and the bias resistance element R62. When these resistance elements are formed in the same integrated circuit, α is always a substantially constant value.

Similarly, the reference voltage Vref is applied to the reference resistance element Rext, and the same current that flows through the reference resistance element Rext is also supplied to the output offset resistance elements R64 and R65.
The output offset resistance elements R64 and R65 can be always made substantially constant by forming them in the same integrated circuit as the monitor resistance element Rpoly.
In such a configuration, the output offset voltage is proportional to the value obtained by multiplying the reference voltage Vref by the ratio of the monitor resistance element Rpoly and the reference resistance element Rext.
The output of the differential amplifier of the replica circuit 61 to which the offset is applied is input to the error amplifier 64, and the input of the error amplifier 62 is balanced by operating the gates of the load adjustment PMOS transistors QP61 and QP62 of the differential amplifier. Has been applied.
When this balance is established, the gain Gamp of the differential amplifier is adjusted as shown below.

[Equation 16]
Gamp == (Vref * β * Rpoly / Rext) / (α * Vref) = (1 / α) * β * Rpoly / Rext

Since R is a combined resistance of the integrated circuit resistance, it has a certain ratio with the monitor resistance element Rpoly.
Rewriting the consistent gain equation with R = Rpoly / γ yields:

  Gtot = (1 / α) * β * γ * Rload / Rext

Since α, β, and γ are resistance ratios in the same integrated circuit as described above, they have substantially constant values that do not depend on manufacturing variations or temperature.
The ratio of Rload / Rext is also constant as long as it is a resistor having a small absolute value and accurate temperature characteristics provided outside the integrated circuit.
Therefore, this equation shows that the circuit of the sixteenth embodiment provides a stable and consistent gain that is independent of manufacturing variations and temperature.

By changing the polarity of the gain adjustment circuit, the gain of the pull-down drive circuit shown in FIG. 13 can be adjusted.
Further, the push-pull type drive circuit as in the second embodiment can be adjusted by using both the circuit of FIG. 17 and its polarity inversion circuit.

  FIG. 19 is a circuit diagram showing a second configuration example of the gain adjustment circuit 60 of FIG.

The gain adjustment circuit 60B of FIG. 19 is different from the gain adjustment circuit 60A of FIG. 18 as follows.
That is, in the voltage supply unit 62A, the current ratio of the current mirror circuit that causes the current flowing through the monitor resistor element Rpoly to flow into the input bias resistor R62 of the differential amplifier of the replica circuit 61 is slightly changed by the control signal TRIM.

Specifically, in the voltage supply unit 62A, PMOS transistors QP70 to QP73 are connected in parallel to the PMOS transistor QP64 forming the current mirror circuit.
The drain of the PMOS transistor QP70 is connected to the node ND63, the source is connected to the drain of the PMOS transistor QP72, and the source of the PMOS transistor QP72 is connected to the power supply potential source VDD.
The drain of the PMOS transistor QP71 is connected to the node ND63, the source is connected to the drain of the PMOS transistor QP73, and the source of the PMOS transistor QP73 is connected to the power supply potential source VDD.
The gates of the PMOS transistors QP70 and QP71 are connected to the output of the operational amplifier A61 in common with the gate of the PMOS transistor QP64.
The gate of the PMOS transistor QP72 is connected to the supply line of the control signal TRIM1, and the gate of the PMOS transistor QP73 is connected to the supply line of the control signal TRIM2.

  In the voltage supply unit 62A, the current ratio of the current mirror circuit that flows through the input bias resistor element R62 is slightly changed by opening and closing the PMOS transistors QP72 and QP73 with the control signals TRIM1 and TRIM0.

This equivalently adjusts the ratio α between the monitor resistance element Rpoly and the bias resistance element R62. As a result, the consistent gain can also be adjusted.
Even though the resistance ratios α, β, and γ in an integrated circuit are almost constant, there are slight differences due to manufacturing variations, and if many integrated circuits are manufactured, there are rare cases that have large differences. .
In the gain adjustment circuit 60B of FIG. 19, the consistent gain generated due to the resistance ratio shift due to manufacturing variation can be corrected by the control signals TRIM1 and TRIM0.

  By inverting the polarity of the circuit of FIG. 19 and using it in combination with the inverted one, application to the circuit of FIG. 13 according to the fourteenth embodiment and the circuit of the second embodiment is possible.

The other configuration example of the driver 1A including the differential drive circuit according to the second embodiment has been described above.
Next, another configuration example of the communication device 100 according to the third embodiment will be described as the seventeenth to twentieth embodiments with reference to FIGS.

<Seventeenth embodiment>
FIG. 20 is a diagram illustrating a configuration example of a communication device according to the seventeenth embodiment of the present invention.

In the communication device 100A according to the seventeenth embodiment, a transmitter 160 on the transmitter 120 side is further arranged in the configuration of the communication device 100 according to the third embodiment, the receiver 17 on the transmitter 130 side, and A bias power supply 180 is disposed.
One end of the differential transmission line 110 is terminated by one termination resistor Rterm1 in the vicinity of the transmitter 120, and the output of the transmitter 160 is connected to the differential transmission line 110 via two termination resistors Rterm2. Yes.
On the other end side of the differential transmission line 110, it is terminated with one termination resistor Rterm 1 in the vicinity of the transmitter 120, and is connected to a DC bias power supply 180 via two termination resistors Rterm 24.
A receiver 170 is connected to the other end side of the differential transmission path 110.

The transmitters 120 and 130 include, for example, the differential drive circuits 2 and 2A of the first or second embodiment described above.
The differential drive circuit (output circuit) of this embodiment always outputs an accurate differential current independent of the output potential. Therefore, even if another signal is superimposed on the differential signal pair with the common-mode potential, the differential signal will not be disturbed, and the common-mode signal associated with the differential signal drive that causes noise for the common-mode signal will not be generated. Leakage is small.

As described above, in the communication device 100A according to the seventeenth embodiment, the differential transmission line 110 is connected in parallel with one Rterm1 resistor and two Rterm2 (-1, -2) in series near the transmitter 120. Terminating, a low impedance signal voltage is applied to the node of Rterm2 on the transmitter 120 side, and biased with a DC voltage on the transmitter 130 side.
When the transmitter is viewed from the differential transmission line 110 side, the parallel resistance of the termination resistor Rterm1 and the termination resistor Rterm2 can be seen in the differential mode, and the two parallel resistors Rterm2 can be seen in the in-phase mode.
For example, if the termination resistance Rterm1 is 1 kΩ and the termination resistance Rterm2 is 56Ω, the termination is about 100Ω differential and 28Ω in phase. The impedance is matched to 100Ω dynamic and 30Ω in phase.
When an in-phase voltage signal is sent to such a transmission line by the transmitter 160, the receiver 170 can receive the signal as an average voltage of the differential pair.
This transmission is realized without interfering with the differential signal transmission from the transmitter 129 to the receiver 150 and the differential signal transmission from the transmitter 130 to the receiver 140.

<Eighteenth embodiment>
FIG. 21 is a diagram illustrating a configuration example of a communication device according to the eighteenth embodiment of the present invention.

  In the communication device 100B according to the eighteenth embodiment, the receiver 200 is arranged in parallel with the transmitter 160 on one end side of the differential transmission path 110, and the transmitter 190 and the transmitter 210 are similarly arranged on the other end side. Connected in parallel.

  In this communication device 100B, the in-phase signal is also realized without simultaneous interference between the transmission from the transmitter 160 to the receiver 210 and the bidirectional transmission from the transmitter 190 to the receiver 200.

<Nineteenth embodiment>
FIG. 22 is a diagram illustrating a configuration example of a communication device according to the nineteenth embodiment of the present invention.

The communication device 100C according to the nineteenth embodiment differs from the communication device 100A according to the eighteenth embodiment in that the transmitter 120C on one end side of the differential transmission line 100 is connected to the driver 1D according to the sixth embodiment. The driver 1K according to the thirteenth embodiment is applied.
The communication device 100C has a bias power source 220 instead of the transmitter 160, and one end side of the differential transmission path 110 is also biased with a DC voltage through the resistor Rterm2.

<20th Embodiment>
FIG. 23 is a diagram illustrating a configuration example of a communication device according to the twentieth embodiment of the present invention.

The communication device 100D according to the twentieth embodiment is different from the communication device 100C according to the nineteenth embodiment in that the transmitter 130D on the other end side of the differential transmission line 100 is also connected to the driver according to the sixth embodiment. 1D and the driver 1K of the thirteenth embodiment are applied.
A receiver 230 is connected in parallel to the transmitter 120C.

  According to the twentieth embodiment, simultaneous bidirectional transmission of in-phase signals can be performed using the driver 1D of the sixth embodiment or the driver 1K of the thirteenth embodiment.

1 is a circuit diagram illustrating a configuration example of a driver including a differential drive circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the communication apparatus which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 7th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 8th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 9th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 10th Embodiment of this invention. It is a flowchart which shows operation | movement of the state machine in FIG. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit based on the 11th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit based on the 12th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit which concerns on the 13th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit based on the 14th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit based on the 15th Embodiment of this invention. It is a circuit diagram which shows the structural example of the driver containing the differential drive circuit based on the 16th Embodiment of this invention. FIG. 18 is a circuit diagram illustrating a first configuration example of the gain adjustment circuit of FIG. 17. FIG. 18 is a circuit diagram illustrating a second configuration example of the gain adjustment circuit of FIG. 17. It is a figure which shows the structural example of the communication apparatus which concerns on the 17th Embodiment of this invention. It is a figure which shows the structural example of the communication apparatus which concerns on the 18th Embodiment of this invention. It is a figure which shows the structural example of the communication apparatus which concerns on the 19th Embodiment of this invention. It is a figure which shows the structural example of the communication apparatus which concerns on the 20th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1A-1N ... Driver, 2, 2A ... Differential drive circuit, Q1 ... 1st field effect transistor, Q2 ... 2nd field effect transistor, Q3 ... 3rd Field effect transistor, Q4 ... fourth field effect transistor, R1 ... first resistance element, R2 ... second resistance element, R3 ... third resistance element, R4 ... first 4 resistive elements, R5... 5th resistive element, R6... 6th resistive element, 21... First circuit, A1. A2 ... second operational amplifier 23 ... third circuit A3 ... third operational amplifier 24 ... fourth circuit A4 ... fourth operational amplifier 3, 4... DAC, 5 ... common mode feedback (CMFB) circuit, 6 ... first differential amplifier, 7 ... second differential amplifier, 100,100A~100D ··· communication device.

Claims (20)

A first field effect transistor of a first conductivity type;
A second field effect transistor of the first conductivity type;
First and second resistance elements;
A first circuit for controlling the source voltage of the first field effect transistor to be equal to a first drive target voltage supplied;
A second circuit for controlling the source voltage of the second field effect transistor to be equal to a second drive target voltage to be supplied;
The source of the first field effect transistor is connected to the power supply potential source via the first resistance element, the drain is connected to the first output node,
A first drive system in which a source of the second field effect transistor is connected to a power supply potential source through the second resistance element, and a drain is connected to a second output node;
A third field effect transistor of the second conductivity type;
A fourth field effect transistor of the second conductivity type;
Third and fourth resistance elements;
A third circuit for controlling the source voltage of the third field effect transistor to be equal to a third drive target voltage supplied;
A fourth circuit for controlling the source voltage of the fourth field effect transistor to be equal to a fourth drive target voltage to be supplied;
The source of the third field effect transistor is connected to the reference potential source via the third resistance element, the drain is connected to the first output node,
A source of the fourth field effect transistor is connected to a reference potential source via the fourth resistance element, and a second drive system having a drain connected to a second output node;
At least one of
A differential drive circuit that drives to form a differential signal with a constant common-mode voltage across the load resistor. In the first drive system,
The first drive target voltage and the second drive target voltage form a differential signal pair whose sum is constant,
In the second drive system,
The differential drive circuit according to claim 1, wherein the third drive target voltage and the fourth drive target voltage form a differential signal pair whose sum is constant. When having the first drive system and the second drive system,
The first drive target voltage and the third drive target voltage are the same waveform signal including an offset,
The differential drive circuit according to claim 2, wherein the second drive target voltage and the fourth drive target voltage are the same waveform signal including an offset. In the first drive system,
The average voltage of the first drive target voltage and the second drive target voltage is biased to be a certain amount lower than the power supply potential,
In the second drive system,
The differential drive circuit according to claim 2, wherein an average voltage of the third drive target voltage and the fourth drive target voltage is biased so as to be a value higher than the reference potential by a certain amount. The first circuit has a first input terminal connected to the supply line of the first drive target voltage, a second input terminal connected to the source of the first field effect transistor, and an output connected to the first circuit. A first operational amplifier connected to the gate of one field effect transistor;
The second circuit has a third input terminal connected to the supply line of the second drive target voltage, a fourth input terminal connected to the source of the second field effect transistor, and an output connected to the second circuit. A second operational amplifier connected to the gates of the two field effect transistors;
The third circuit has a fifth input terminal connected to the third drive target voltage supply line, a sixth input terminal connected to the source of the third field effect transistor, and an output connected to the third circuit. A third operational amplifier connected to the gates of the three field effect transistors;
The fourth circuit has a seventh input terminal connected to the fourth drive target voltage supply line, an eighth input terminal connected to the source of the fourth field effect transistor, and an output connected to the fourth circuit. The differential drive circuit according to claim 1, further comprising a fourth operational amplifier connected to the gates of the four field effect transistors. In the first drive system,
A fifth resistance element is connected between the source of the first field effect transistor and the source of the second field effect transistor;
In the second drive system,
The differential drive circuit according to claim 1, wherein a sixth resistance element is connected between a source of the third field effect transistor and a source of the fourth field effect transistor. In the first drive system,
A fifth resistance element is connected between the source of the first field effect transistor and the source of the second field effect transistor;
In the second drive system,
The differential drive circuit according to claim 5, wherein a sixth resistance element is connected between a source of the third field effect transistor and a source of the fourth field effect transistor. The first drive system is
A digital-to-analog converter (DAC) that generates the first driving target potential and the second driving target potential according to input digital data;
The second drive system is
The differential drive circuit according to claim 1, further comprising a digital-to-analog converter (DAC) that generates the third drive target time potential and the fourth drive target potential according to input digital data. The first drive system is
A first DAC for generating the first drive target potential based on a first addition / subtraction result of two numerical inputs;
A second DAC that generates the second drive target potential based on a second addition / subtraction result of two numerical inputs,
The second drive system is
A third DAC for generating the third drive target potential based on a third addition / subtraction result of two numerical inputs;
The differential drive circuit according to claim 8, further comprising: a fourth DAC that generates the fourth drive target potential based on a fourth addition / subtraction result of two numerical inputs. The first drive system is
A stabilization circuit for stabilizing the outputs of the first DAC and the second DAC;
The second drive system is
The differential drive circuit according to claim 9, further comprising a stabilization circuit that stabilizes outputs of the third DAC and the fourth DAC. The first drive system is
A multiplier that multiplies the input by a coefficient defined so that the output of the DAC with respect to a specific input has a constant value and inputs the coefficient to the DAC;
The second drive system is
The differential drive circuit according to claim 8, further comprising a multiplier that multiplies the input by a coefficient defined so that an output of the DAC with respect to a specific input becomes a constant value and inputs the input to the DAC. The first drive system is
In response to the differential voltage, the first drive target voltage and the second drive target voltage are generated, the generated first drive target voltage is supplied to the first circuit, and the second drive target voltage is generated. A first differential amplifier for supplying a voltage to the second circuit;
The second drive system is
The third driving target voltage and the fourth driving target voltage are generated in response to the differential voltage, the generated third driving target voltage is supplied to the third circuit, and the fourth driving is performed. The differential drive circuit according to claim 1, further comprising a second differential amplifier that supplies a target voltage to the fourth circuit. In the first drive system,
A fifth resistance element is connected between the source of the first field effect transistor and the source of the second field effect transistor;
In the second drive system,
The differential drive circuit according to claim 12, wherein a sixth resistance element is connected between a source of the third field effect transistor and a source of the fourth field effect transistor. In the first drive system,
An offset adding circuit for adding an offset to the first drive target potential and the second drive target potential generated by the first differential amplifier;
In the second drive system,
The differential drive circuit according to claim 12, further comprising an offset addition circuit that adds an offset to the third drive target potential and the fourth drive target potential generated by the second differential amplifier. The first drive system is
A first field-effect transistor connected in parallel to the load resistance of the first differential amplifier for resistance adjustment;
An adjustment circuit for adjusting a gate potential of the first field effect transistor,
The second drive system is
A second field effect transistor connected in parallel to the load resistance of the second differential amplifier, for resistance adjustment;
The differential drive circuit according to claim 12, further comprising: an adjustment circuit that adjusts a gate potential of the second field effect transistor. The differential drive circuit according to claim 5, wherein a common mode feedback circuit that absorbs a surplus current supplied to the load side is connected. Having transmitters arranged at both ends of the differential transmission path;
The transmitter includes a differential drive circuit that drives to form a differential signal with a constant common-mode voltage across the load resistor,
The differential drive circuit is
A first field effect transistor of a first conductivity type;
A second field effect transistor of the first conductivity type;
A third field effect transistor of the second conductivity type;
A fourth field effect transistor of the second conductivity type;
First and second output nodes;
First, second, third, and fourth resistance elements,
The source of the first field effect transistor is connected to the power supply potential via the first resistance element, the drain is connected to the first output node,
The source of the second field effect transistor is connected to the power supply potential via the second resistance element, the drain is connected to the second output node,
The source of the third field effect transistor is connected to the reference potential via the third resistance element, the drain is connected to the first output node,
The source of the fourth field effect transistor is connected to the reference potential via the fourth resistance element, the drain is connected to the second output node,
A first circuit for controlling the source voltage of the first field effect transistor to be equal to a first drive target voltage supplied;
A second circuit for controlling the source voltage of the second field effect transistor to be equal to the second drive target voltage supplied;
A third circuit for controlling the source voltage of the third field effect transistor to be equal to a third drive target voltage supplied;
And a fourth circuit that controls the source voltage of the fourth field effect transistor to be equal to a fourth drive target voltage to be supplied. In the above differential drive circuit,
A fifth resistance element is connected between the source of the first field effect transistor and the source of the second field effect transistor;
The communication device according to claim 17, wherein a sixth resistance element is connected between a source of the third field effect transistor and a source of the fourth field effect transistor. In response to the differential voltage, the first drive target voltage and the second drive target voltage are generated, the generated first drive target voltage is supplied to the first circuit, and the second drive target voltage is generated. A first differential amplifier for supplying a voltage to the second circuit;
The third driving target voltage and the fourth driving target voltage are generated in response to the differential voltage, the generated third driving target voltage is supplied to the third circuit, and the fourth driving is performed. The communication apparatus according to claim 17, further comprising: a second differential amplifier that supplies a target voltage to the fourth circuit. The communication device according to claim 17, further comprising a receiver in parallel with the transmitter with respect to the differential transmission path.

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