CN101447785B - Differential drive circuit and communication device - Google Patents

Abstract

A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.

Description

Differential drive circuit and communication equipment

The cross reference of related application

The present invention comprises the theme relevant with JP2008-231338 with Japanese patent application JP2007-311134, these two Japanese patent applications were submitted to Japan Patent office respectively on November 30th, 2007 and on September 9th, 2008, and their full content is incorporated herein by reference.

Technical field

The present invention relates to the differential drive circuit and the communication equipment of the differential signal that a kind of processing propagates on difference transmission lines or analog.

Background technology

Differential signal is widely used for the long Distance Transmission of high speed of data.

Especially, the patent application publication number of Japanese unexamined is that the push-pull actuator of putting down in writing among the No.2006-345259 is used continually, because it is very little that differential signal is urged to the required electric current of load.

In such circuit, the average voltage instability at load two ends is unless the mean value of pull-up current and pull-down current mates mutually on one period long period.Therefore, make the constant FEEDBACK CONTROL of common-mode voltage output regulate current source by utilization.

Have, the patent application publication number of Japanese unexamined is a kind of technology that discloses among the No.2003-347860 again, is used for suppressing by the driving timing of regulating driving transistors the generation of common-mode voltage.

Summary of the invention

But, be slow response control by utilizing this technology that makes the constant FEEDBACK CONTROL of common-mode voltage output regulate current source, only can be used for keeping average voltage constant.The instantaneous value of common-mode voltage can the fluctuation tempestuously owing to the variation of the transistorized connection of push-and-pull/shutoff timing.

This fluctuation in the common-mode voltage produces a kind of pulsating current, and this pulsating current returns at the line of the ground potential GND of differential transfer above-the-line promotion and process connection transmitter and receiver, and this can disseminate big radiated noise.

As mentioned above, the patent application publication number of Japanese unexamined is the generation that disclosed technology suppresses common-mode voltage among the No.2003-347860 by the driving timing of regulating driving transistors.

Yet, said on the stricti jurise that this method was only effective when equate to the fall time of last rise time of drawing drive circuit and pull-down circuit.In fact, rise time and fall time there are differences between the two, therefore are difficult to the common-mode voltage fluctuation is suppressed to zero.

More a kind of method of Shi Yonging is to suppress the fluctuation of common-mode voltage by a kind of filter element that utilization is called common-mode filter or pulse converter, and this common-mode filter or pulse converter are used for suppressing the output of the differential drive circuit that common-mode voltage fluctuates.

Yet disadvantageously, such filter element size is big, makes to be difficult to this filter element is integrated into drive circuit at semiconductor-based the end.Moreover this filter element has increased the quantity and the price height of parts.

Expectation provides a kind of differential drive circuit and communication equipment, even when transistorized grid voltage-drain current characteristics when being non-linear, even perhaps when the characteristics of transistor of opposed polarity not simultaneously, also can export differential signal with the common mode component that needs.

According to one embodiment of present invention, provide a kind of differential drive circuit, comprised that first drive system and second drive system are one of at least.This first drive system comprises first field-effect transistor of first conduction type, second field-effect transistor, first resistor and second resistor, first circuit and the second circuit of first conduction type, this first circuit control the source voltage of first field-effect transistor in case make that it equals to apply first drive target voltage, what the source voltage that this second circuit is controlled second field-effect transistor made that it equals to apply second drives target voltage.The source electrode of first field-effect transistor is connected to the power supply potential source through first resistor, and drain electrode is connected to first output node, and the source electrode of second field-effect transistor is connected to the power supply potential source through second resistor, and drain electrode is connected to second output node.Second drive system comprises the 3rd field-effect transistor of second conduction type, the 4th field-effect transistor, the 3rd resistor, the 4th resistor, tertiary circuit and the 4th circuit of second conduction type.What the source voltage that this tertiary circuit is controlled the 3rd field-effect transistor made that it equals to apply the 3rd drives target voltage, and the 4th circuit is controlled the 4 wheel driven moving-target voltage that the source voltage of the 4th field-effect transistor makes it equal to apply.The source electrode of the 3rd field-effect transistor is connected to source of reference potential through the 3rd resistor, and drain electrode is connected to first output node.The source electrode of the 4th field-effect transistor is connected to source of reference potential through the 4th resistor, and drain electrode is connected to second output node.This differential drive circuit drives common-mode voltage, so that form the constant difference sub-signal across load resistance.

Preferably, this first drives target voltage and second and drives target voltage to form a differential signal right, the two and be constant.In second drive system, the 3rd drives target voltage and 4 wheel driven moving-target voltage, and to form a differential signal right, the two and be constant.

Preferably, it is the signal with same waveform as of a deviant that this first driving target voltage and the 3rd drives target voltage, and the second driving target voltage and 4 wheel driven moving-target voltage are the signals with same waveform as of a deviant.

Preferably, this first average voltage that drives the target voltage and the second driving target voltage is biased so that it is lower than constant value of power supply potential, and the 3rd average voltage that drives target voltage and 4 wheel driven moving-target voltage is biased so that it is higher than constant value of reference potential.

Preferably, first circuit comprises first operational amplifier, the first input end of this first operational amplifier is connected to the power line of the first driving target voltage, and second input is connected to the source electrode of first field-effect transistor, and output is connected to the grid of first field-effect transistor.Second circuit comprises second operational amplifier, and the 3rd input of this second operational amplifier is connected to the power line of the second driving target voltage, and four-input terminal is connected to the source electrode of second field-effect transistor, and output is connected to the grid of second field-effect transistor.Tertiary circuit comprises the 3rd operational amplifier, and the 5th input of the 3rd operational amplifier is connected to the power line of the 3rd driving target voltage, and the 6th input is connected to the source electrode of the 3rd field-effect transistor, and output is connected to the grid of the 3rd field-effect transistor.The 4th circuit comprises four-operational amplifier, and the 7th input of this four-operational amplifier is connected to the power line of 4 wheel driven moving-target voltage, and the 8th input is connected to the source electrode of the 4th field-effect transistor, and output is connected to the grid of the 4th field-effect transistor.

Preferably, first drive system also comprises the 5th resistor between the source electrode of the source electrode that is connected first field-effect transistor and second field-effect transistor, and second drive system also comprises the 6th resistor between the source electrode of the source electrode that is connected the 3rd field-effect transistor and the 4th field-effect transistor.

Preferably, first drive system also comprises first differential amplifier, this amplifier receives differential voltage and produces first and drives the target voltage and the second driving target voltage, and the first driving target voltage that is produced is provided to first circuit, the second driving target voltage that is produced is provided to second circuit, second drive system also comprises second differential amplifier, this amplifier receives differential voltage and produces the 3rd and drives target voltage and 4 wheel driven moving-target voltage, and the 3rd driving target voltage that is produced is provided to tertiary circuit, the 4 wheel driven moving-target voltage that is produced is provided to the 4th circuit.

Preferably, first drive system also comprises digital analog converter (DAC), and this digital analog converter produces the first driving target current potential and the second driving target current potential according to the numerical data of input.Second drive system also comprises digital analog converter (DAC), and this digital analog converter produces the 3rd driving target current potential and 4 wheel driven moving-target current potential according to the numerical data of input.

Preferably, first drive system also comprises a DAC and the 2nd DAC, and a DAC adds/subtracts the result from first of two digital inputs and produces the first driving target current potential, and the 2nd DAC adds/subtracts the result from second of two numeral inputs and produces the second driving target current potential.Second drive system also comprises the 3rd DAC and the 4th DAC, and the 3rd DAC adds/subtracts the result from the 3rd of two numeral inputs and produces the 3rd driving target current potential, and the 4th DAC produces 4 wheel driven moving-target current potential from the 4th added/subtracted results of two numeral inputs.

Preferably, first drive system also comprises the stabilizing circuit of the output of stablizing a DAC and the 2nd DAC, and second drive system also comprises the stabilizing circuit of the output of stablizing the 3rd DAC and the 4th DAC.

Preferably, first drive system also comprises multiplier, and this multiplier multiply by the coefficient of appointment so that the output of DAC becomes a steady state value with respect to input with specific input, and will take advantage of the input of coefficient to be input to DAC.Second drive system also comprises multiplier, and this multiplier multiply by the coefficient of appointment so that the output of DAC becomes a steady state value with respect to input with specific input, and will take advantage of the input of coefficient to be input to DAC.

Preferably, first drive system also comprises the skew adjunct circuit, and this circuit first drives target current potential and second and drives on each of target current potential what a skew appended to that first differential amplifier produced.Second drive system also comprises the skew adjunct circuit, and this circuit is with the 3rd driving on each of target current potential and 4 wheel driven moving-target current potential that a skew appends to that second differential amplifier produced.

Preferably, first drive system also comprises the first resistance adjustment field-effect transistor and a regulating circuit, this first resistance adjustment field-effect transistor is in parallel with the load resistance of first differential amplifier, and this regulating circuit is regulated the grid potential of the first resistance adjustment field-effect transistor.Second drive system also comprises the second resistance adjustment field-effect transistor and a regulating circuit, this second resistance adjustment field-effect transistor is in parallel with the load resistance of second differential amplifier, and this regulating circuit is regulated the grid potential of the second resistance adjustment field-effect transistor.

Preferably, differential drive circuit is connected with common mode feedback circuit, and this feedback circuit suppresses the variation of the common-mode voltage of load one side.

According to one embodiment of present invention, provide a kind of communication equipment, this equipment comprises the transmitter of the arbitrary end that is arranged on difference transmission lines.This transmitter comprises differential drive circuit, and this differential drive circuit drives common-mode voltage to form the constant difference sub-signal across the load resistance two ends.This differential drive circuit comprises first field-effect transistor of first conduction type, second field-effect transistor of first conduction type, the 3rd field-effect transistor of second conduction type, the 4th field-effect transistor, first output node and second output node, first resistor, second resistor, the 3rd resistor and the 4th resistor, first circuit, second circuit, tertiary circuit and the 4th circuit of second conduction type.The source electrode of this first field-effect transistor is connected to power supply potential through first resistor, and drain electrode is connected to first output node, and the source electrode of second field-effect transistor connects power supply potential through second resistor, and drain electrode is connected to second output node.The source electrode of the 3rd field-effect transistor is connected to reference potential through the 3rd resistor, and drain electrode is connected to first output node.The source electrode of the 4th field-effect transistor is connected to reference potential through the 4th resistor, and drain electrode is connected to second output node.The source voltage that this first circuit is controlled first field-effect transistor makes its first driving target voltage that equals to apply, what the source voltage that second circuit is controlled second field-effect transistor made that it equals to apply second drives target voltage, what the source voltage that tertiary circuit is controlled the 3rd field-effect transistor made that it equals to apply the 3rd drives target voltage, and the 4th circuit is controlled the 4 wheel driven moving-target voltage that the source voltage of the 4th field-effect transistor makes it equal to apply.

Preferably, this communication equipment also comprises with respect to this difference output line and the parallel receiver that is provided with of this transmitter.

According to one embodiment of present invention, this first and second resistor is connected between the source electrode and power supply potential of first and second field-effect transistors, and third and fourth resistor is connected between the source electrode and reference potential of third and fourth field-effect transistor.

So, carry out FEEDBACK CONTROL, make the source voltage of source voltage and the 3rd, the 4th field-effect transistor of first and second field-effect transistors become and equal their driving target voltages separately, the grid of the grid of first and second field-effect transistors and the 3rd, the 4th field-effect transistor is driven from drain electrode and extracts output.

This differential drive circuit can be used as so-called difference push-pull actuator.

According to one embodiment of present invention, even when transistorized grid voltage-drain current characteristics is non-linear, even the characteristic perhaps between the transistor of opposed polarity is not simultaneously, also can have the differential signal of the common mode component that needs by simple structure output.

Description of drawings

Fig. 1 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of first embodiment of the invention;

Fig. 2 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of second embodiment of the invention;

Fig. 3 is the structure chart that shows according to the communication equipment of third embodiment of the invention;

Fig. 4 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fourth embodiment of the invention;

Fig. 5 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fifth embodiment of the invention;

Fig. 6 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of sixth embodiment of the invention;

Fig. 7 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of seventh embodiment of the invention;

Fig. 8 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of eighth embodiment of the invention;

Fig. 9 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of ninth embodiment of the invention;

Figure 10 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of tenth embodiment of the invention;

Figure 11 is the flow chart of operation that shows the state machine of Figure 10;

Figure 12 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of eleventh embodiment of the invention;

Figure 13 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of twelveth embodiment of the invention;

Figure 14 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of thriteenth embodiment of the invention;

Figure 15 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fourteenth embodiment of the invention;

Figure 16 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fifteenth embodiment of the invention;

Figure 17 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of sixteenth embodiment of the invention;

Figure 18 is the circuit diagram of first structure that shows the gain adjusting circuit of Figure 17;

Figure 19 is the circuit diagram of second structure that shows the gain adjusting circuit of Figure 17;

Figure 20 is the schematic diagram of demonstration according to the structure of the communication equipment of seventeenth embodiment of the invention;

Figure 21 is the schematic diagram of demonstration according to the structure of the communication equipment of eighteenth embodiment of the invention;

Figure 22 is the schematic diagram of demonstration according to the structure of the communication equipment of nineteenth embodiment of the invention;

Figure 23 is the schematic diagram of demonstration according to the structure of the communication equipment of twentieth embodiment of the invention.

Embodiment

Embodiments of the invention are described below with reference to accompanying drawings.

First embodiment

Fig. 1 is the circuit diagram of demonstration according to the structure of the driver that comprises differential drive circuit of first embodiment of the invention.

Driver 1 according to this embodiment has differential drive circuit 2, first digital analog converter (DAC) 3, the 2nd DAC4 and common-mode feedback (CMFB) circuit 5.

Differential drive circuit 2 have as first conduction type for example first field-effect transistor of P channel type (P type) PMOS transistor Q1 and as the PMOS transistor Q2 of P type second field-effect transistor.

Differential drive circuit 2 have as second conduction type for example the 3rd field-effect transistor of N channel type (N type) nmos pass transistor Q3 and as the N MOS transistor Q4 of N type the 4th field-effect transistor.

The source electrode of the first transistor Q1 is connected to power supply potential source VDD through first resistor R 1, and drain electrode is connected to the first output node NO1.

The source electrode of transistor seconds Q2 is connected to power supply potential source VDD through second resistor R 2, and drain electrode is connected to the second output node NO2.

The source electrode of the 3rd transistor Q3 is connected to source of reference potential VSS through the 3rd resistor R 3, and drain electrode is connected to the first output node NO1.

The source electrode of the 4th transistor Q4 is connected to source of reference potential VSS through the 4th resistor R 4, and drain electrode is connected to the second output node NO2.

Reference potential VSS comprises ground potential GND.

In addition, has first circuit 21 of the source voltage S1 of control the first transistor Q1, so that make voltage S1 that the first driving target voltage V1 that provides from DAC3 is provided according to the differential drive circuit 2 of this embodiment.

Differential drive circuit 2 has the second circuit 22 of the source voltage S2 of control transistor seconds Q2, so that make voltage S2 that the second driving target voltage V2 that provides from DAC3 is provided.

Differential drive circuit 2 has the tertiary circuit 23 of the source voltage S3 of control the 3rd transistor Q3, so that make voltage S3 that the 3rd driving target voltage V3 that provides from DAC4 is provided.

Differential drive circuit 2 has the 4th circuit 24 of the source voltage S4 of control the 4th transistor Q4, so that the 4 wheel driven moving-target voltage V4 that voltage S4 equals to provide is provided.

Differential drive circuit 2 drives for example transmission line of outlet side, so that common-mode voltage forms the constant difference sub-signal of striding load resistance Rload.

First circuit 21 is made of first operational amplifier A 1.

In first circuit 21, be connected to the power line of the first driving target voltage V1 as the non-inverting input (+) of first input end, be connected to the source electrode of the first transistor Q1 as the inverting input (-) of second input, output is connected to the grid of the first transistor Q1.

Second circuit 22 is made of second operational amplifier A 2.

In second circuit 22, be connected to the power line of the second driving target voltage V2 as the non-inverting input (+) of the 3rd input, be connected to the source electrode of transistor seconds Q2 as the inverting input (-) of four-input terminal, output is connected to the grid of transistor seconds Q2.

Tertiary circuit 23 is made of the 3rd operational amplifier A 3.

In tertiary circuit 23, be connected to the power line of the 3rd driving target voltage V3 as the non-inverting input (+) of the 5th input, be connected to the source electrode of the 3rd transistor Q3 as the inverting input (-) of the 6th input, output is connected to the grid of the 3rd transistor Q3.

The 4th circuit 24 is made of four-operational amplifier A4.

In the 4th circuit 24, be connected to the power line of 4 wheel driven moving-target voltage V4 as the non-inverting input (+) of the 7th input, be connected to the source electrode of the 4th transistor Q4 as the inverting input (-) of the 8th input, output is connected to the grid of the 4th transistor Q4.

DAC3 receives N bit digital signal D and produces the first driving target voltage V1 and the second driving target voltage V2, drive first circuit 21 that target voltage V1 is provided to differential drive circuit 2 with first, second driven target voltage V2 and be provided to second circuit 22 what produce.

DAC4 receives N bit digital signal D and produces the 3rd driving target voltage V3 and 4 wheel driven moving-target voltage V4, the 3rd driven the tertiary circuit 23 that target voltage V3 is provided to differential drive circuit 4 with what produce, V4 is provided to the 4th circuit 24 with 4 wheel driven moving-target voltage.

DAC3 has resistor R A1, and this resistor is connected first and drives between the first power line LV1 and power supply potential source VDD of target voltage V1, and current source I31 is connected between the first power line LV1 and the source of reference potential VSS.

DAC3 has resistor R A2, and this resistor is connected second and drives between the second source line LV2 and power supply potential source VDD of target voltage V2, and current source I32 is connected between second source line LV2 and the source of reference potential VSS.

DAC3 has N power supply I3-0 to I3-N-1, and each power supply is connected to source of reference potential VSS, and their current value is weighting.

In addition, DAC3 has switch SW 3-0 to SW3-N-1, and these switches optionally are connected to I3-N-1 each current source I3-0 with first or second source line LV1 or LV2.

Reference potential VSS comprises ground potential GND.

DAC4 has resistor R A3, and this resistor is connected the 3rd and drives between the 3rd power line L V3 and source of reference potential VSS of target voltage V3, and current source I41 is connected between the 3rd power line L V3 and the power supply potential source VDD.

DAC4 has resistor R A4, and this resistor is connected between the 4th power line LV4 and source of reference potential VSS of 4 wheel driven moving-target voltage V4, and current source I42 is connected between the 4th power line L V4 and the power supply potential VDD.

DAC4 has N power supply I4-0 to I4-N-1, and each power supply is connected to power supply potential source VDD, and their current value is weighting.

In addition, DAC4 has switch SW 4-0 to SW4-N-1, and these switches optionally are connected to I4-N-1 each current source I4-0 with the 3rd or the 4th power line LV3 or LV4.

Reference potential VSS comprises ground potential GND.

Common-mode feedback (CMFB) circuit 5 has the function that absorbs the unnecessary electric current that is provided to load-side.

Common-mode feedback (CMFB) circuit 5 has n type field effect transistor Q51 and Q52, operational amplifier A 51, resistor R 51 and R52 and public voltage source V51.

The drain electrode of transistor Q51 is connected to the first output node NO1 side of differential drive circuit 2, and source electrode is connected to reference potential VSS (for example ground potential GND), and grid is connected to the output of operational amplifier A 51.

The drain electrode of transistor Q52 is connected to the second output node NO2 side of differential drive circuit 2, and source electrode is connected to reference potential VSS (for example ground potential GND), and grid is connected to the output of operational amplifier A 51.

Resistor R 51 and R52 are connected between the first output node NO1 and the second output node NO2 of differential drive circuit 2.The tie point of two resistors is connected to the non-inverting input (+) of operational amplifier A 51.The inverting input (-) of public voltage source V51 tie point operational amplifier A 51.

In driver 1, in DAC3 and DAC4, change as follows with the output voltage that digital form provides with said structure.

That is, in DAC3, output voltage information is converted into first and drives the target voltage V1 and the second driving target voltage V2, and these two voltages are aanalogvoltage, as the driving desired value of first and second transistors (PMOS transistor) Q1 and Q2.

In DAC4, output voltage information is converted into the 3rd and drives target voltage V3 and 4 wheel driven moving-target voltage V4, and these two voltages are aanalogvoltage, as the driving desired value of third and fourth transistor (nmos pass transistor) Q3 and Q4.

First drives target voltage V1 and second, and to drive target voltage V2 be that differential signal is right, the two and be constant, the 3rd drives target voltage V3 and 4 wheel driven moving-target voltage V4 also is that differential signal is right, the two and be constant.

It is the signal with skew that the first driving target voltage V1 and the 3rd drives target voltage V3, but waveform is identical, and the second driving target voltage V2 and 4 wheel driven moving-target voltage V4 also are the signals with same waveform as of skew.

The first driving target voltage V1 and second drives target voltage V2 and is biased separately, makes average voltage become and is lower than steady state value of power supply potential VDD.

The 3rd driving target voltage V3 and 4 wheel driven moving-target voltage V4 are biased separately, make average voltage become and are higher than steady state value of reference potential VSS.

First by following equation is represented to the instantaneous voltage of V4 that to 4 wheel driven moving-target voltage V1 these equatioies contain single parameter V (t).

[equation 1]

V1(t)＝VbiasP+V(t) (1)

V2(t)＝VbiasP-V(t) (2)

V3(t)＝VbiasN+V(t) (3)

V4(t)＝VbiasN-V(t) (4)

Operational amplifier A n (n=1 to 4) constitutes negative feedback (NFB), makes the source voltage Sn of transistor Qn become and equals to drive target voltage Vn.

Consequently, flow to resistor R 1 to R4 by the definite electric current of V (t), equal electric current flows to the drain electrode of transistor Q1 to Q4.

The resistance value of supposing resistor R 1 to R4 all is R, and the electric current I pos that flows to load from the drain electrode tie point of transistor Q1 and transistor Q3 is then represented by following equation.

[equation 2]

Ipos＝(VDD-VbiasP-V(t))/R-(VbiasN+V(t))/R

＝(VDD-VbiasP-VbiasN-2V(t))/R (5)

Similarly, the electric current I neg that flows to the drain electrode tie point of transistor Q2 and transistor Q4 from load is then represented by following equation.

[equation 3]

Ineg＝(VbiasN-V(t))/R-(VDD-VbiasP+V(t))/R

＝(VbiasN+VbiasP-VDD-2V(t))/R (6)

By the mode of representing with following equation amount of bias is set, electric current I pos and electric current I neg become equal.

[equation 4]

VDD-VbiasP＝VbiasN (7)

[equation 5]

Ipos＝Ineg＝-2V(t))/R (8)

This means this circuit with respect to the load average voltage that also do not discharge that neither charges, but keep common-mode voltage constant.

In side circuit, the factors such as difference owing to such as equipment performance may be difficult to make amount of bias ideally to satisfy the represented relation of above-mentioned equation (7).

This problem can solve by amount of bias is set in the following manner, that is, make electric current I pos become and guarantee to be slightly larger than electric current I neg, so that the unnecessary electric current that provides with electric current I pos is absorbed by common-mode feedback (CMFB) circuit 5.

CMFB can irrespectively be the arrowband with signal V (t).Load driving based on the AC component V (t) of signal is balanced shown in above-mentioned equation (5) (6), and does not have common mode component.

Second embodiment

Fig. 2 is the circuit diagram of demonstration according to the structure of the driver that comprises differential drive circuit of second embodiment of the invention.

Driver 1A shown in Figure 2 has driver 1 difference among following and Fig. 1.

At first, in differential drive circuit 2A, the 5th resistor R 5 is connected between the source electrode of the source electrode of the first transistor Q1 and transistor seconds Q2, and the 6th resistor R 6 is connected between the source electrode of the source electrode of the 3rd transistor Q3 and the 4th transistor Q4.

Secondly, first differential amplifier 6 and second differential amplifier 7 rather than DAC3 and DAC4 are provided.

First differential amplifier 6 receives analog differential voltage and produces the first driving target voltage V1 and the second driving target voltage V2, and the first driving target voltage V1 that is produced is offered first circuit 21, drives target voltage V2 with second and offers second circuit 22.

Second differential amplifier 7 receives analog differential voltage and produces the 3rd driving target voltage V3 and 4 wheel driven moving-target voltage V4, and the 3rd driving target voltage V3 that is produced is offered tertiary circuit 23, and V4 offers the 4th circuit 24 with 4 wheel driven moving-target voltage.

First differential amplifier 6 has as the nmos pass transistor Q61 of the field-effect transistor of second conduction type and Q62, resistor R A1, RA2 and RA61, current source I61 and I62.

The source electrode of nmos pass transistor Q61 is connected to current source I61, and drain electrode is connected to power supply potential source VDD through resistor R A1, and grid is connected to the power line of analog differential voltage VinP.

The source electrode of nmos pass transistor Q62 is connected to current source I62, and drain electrode is connected to power supply potential source VDD through resistor R A2, and grid is connected to the power line of analog differential voltage VinN.

Resistor R 61 is connected between the source electrode of the source electrode of nmos pass transistor Q61 and nmos pass transistor Q62.

Second differential amplifier 7 has as the PMOS transistor Q71 of the field-effect transistor of first conduction type and Q72, resistor R A3, RA4 and RA71, current source I71 and I72.

The source electrode of PMOS transistor Q71 is connected to current source I71, and drain electrode is connected to source of reference potential VSS (for example ground potential GND) through resistor R A3, and grid is connected to the power line of analog differential voltage VinP.

The source electrode of PMOS transistor Q72 is connected to current source I72, and drain electrode is connected to source of reference potential VSS through resistor R A4, and grid is connected to the power line of analog differential voltage VinN.

Resistor R 71 is connected between the source electrode of the source electrode of PMOS transistor Q71 and PMOS transistor Q72.

In this example, the signal to output to be driven is provided by analog differential voltage VinP-VinN.

This voltage converts first to 4 wheel driven moving-target voltage V1-V4 by first and second differential amplifiers 6 and 7.

For making first differential amplifier 6 and second differential amplifier 7 keep well linear, the peak value of the leakage current ratio of differential pair transistors Q61 and Q62, Q71 and Q72 cannot be provided with too much.

For example, suppose that this ratio is 3:1, under differential drive circuit 2 did not have situation as the 5th resistor R 5 among first embodiment and the 6th resistor R 6, the current ratio between the first transistor Q1 and the transistor seconds Q2 was 3:1 in the moment that maximum current is provided for load.Consequently, differential drive circuit (output circuit) the institute's consumed current and the ratio that can be extracted as between the electric current of output are 4:2.

Because output is the circuit that big electric current is provided to load, the electric current that doubles maximum drive current always is output circuitry consumes, and this fact can be described as waste of electric energy.

In a second embodiment, provide the source electrode of the 5th resistor R 5 and the 6th resistor R 6, the five resistor R, 5 short circuit the first transistor Q1 and transistor seconds Q2, the source electrode of the 6th resistor R 6 short circuits the 3rd transistor Q3 and the 4th transistor Q4.

Because the potential difference of 2V (t) is provided to resistor R 5 and R6, the current ratio between the current ratio between the first transistor Q1 and the transistor seconds Q2, the 3rd nmos pass transistor Q3 and the 4th nmos pass transistor Q4 surpasses the transistorized current ratio in differential amplifier 6 and 7.

Consequently, the electric current that can offer load increases, and the current drain that therefore is used to provide the output circuit of identical drive current reduces, and has improved energy efficiency thus.

To insert the energy efficiency how the 5th resistor R 5 and the 6th resistor R 6 have improved differential drive circuit 2A by following Example explanation.

Here suppose that each resistance of first to the 4th resistor R 1 to R4 is R (Ω), the resistance of each of the 5th and the 6th resistor R 5 and R6 is r (Ω).

At first, consider not have the situation of the 5th and the 6th resistor R 5 and R6.

Suppose that the 3rd drives the current potential of target voltage V3 and 4 wheel driven moving-target voltage V4, promptly each of the current potential of the source voltage S4 of the source voltage S3 of the 3rd transistor Q3 and the 4th transistor Q4 all is the waveform with maximum 0.6 (V) and minimum value 0.2 (V).

The reason that minimum value cannot drop to ground potential GND is for example in order to keep upstream circuitry to have good I/O linearity.

When source voltage S3 is the moment of minimum voltage 0.2 (V), the 3rd transistor Q3 attracts and is 0.2/R (A) through the electric current that source electrode is delivered to the 3rd resistor R 3 from drain electrode.Because simultaneously source voltage S4 becomes maximum voltage 0.6 (V), the 4th nmos pass transistor Q4 attracts and is 0.6/R (A) through the electric current that source electrode is delivered to the 4th resistor R 4 from drain electrode.

Becoming to make the electric current that discharges from the drain electrode of the first transistor Q1 and transistor seconds Q2 for this moment according to the circuit design of present embodiment, is 0.6/R (A) from the electric current of the first transistor Q1, is 0.2/R (A) from the electric current of transistor seconds Q2.

Consequently, the electric current that can be sent to load is 0.4/R (A), and this electric current equals to deduct the magnitude of current that can be attracted fully by the 3rd transistor Q3 from the electric current that the first transistor Q1 discharges.

This electric current also equals to deduct the magnitude of current that can be handled fully by transistor seconds Q2 by the electric current that the 4th transistor Q4 attracts.

On the other hand, because the total current of output circuit of flowing through is 0.8/R (A), be exactly total can send half of current sinking of the electric current that drives load so.

Below, consideration has the situation of the 5th and the 6th resistor R 5 and R6.

Here maximum voltage and the minimum voltage of supposing the source voltage S4 of the source voltage S3 of the 3rd transistor Q3 and the 4th transistor Q4 also are 0.6 (V) and 0.2 (V).

When source voltage S3 is that minimum voltage, source voltage S4 are the moment of maximum voltage, the value of the electric current that flows to source electrode from the 3rd transistor Q3 below being.

That is, for example, the value that flows to the electric current of source electrode from the drain electrode of the 3rd transistor Q3 obtains by deduct the electric current 0.4/r (A) that is provided to the source electrode of the 3rd transistor Q3 through the 6th resistor R 6 from the electric current 0.2/R (A) that flows to ground potential GND through source electrode.

Synchronization adds that by the electric current 0.6/R (A) to the 4th resistor R 4 of flowing through the electric current 0.4/r (A) of the 6th resistor R 6 of flowing through obtains from the value that the drain electrode of the 4th transistor Q4 flows to the electric current of source electrode.

Because the electric current that flows out from the drain electrode of the first transistor Q1 equals the electric current that attracts from the drain electrode of the 4th transistor Q4, the electric current that flows into load from the tie point of the first transistor Q1 and the 3rd transistor Q3 is 0.4/R+0.8/r (A).

Because the electric current that flows out from the drain electrode of transistor seconds Q2 equals from the electric current of the drain electrode attraction of the 3rd transistor Q3, the electric current that flows to the tie point of transistor seconds Q2 and the 4th transistor Q4 from load also is 0.4/R+0.8/r (A).

Though total current sinking of output circuit is 0.8/R (A) this moment, this is identical with value when the 5th and the 6th resistor R 5 and R6 are not provided, and the electric current that can be sent to load has increased 0.8/r (A).

During calculating, when r=2R, the load driving electrorheological must equal the circuitry consumes electric current, and current sinking is totally contributed for driving load.But in the reality, it is not preferred that transistorized electric current becomes 0, because be used to make the feedback loop of source potential coupling target current potential to become open.

Resistance value r is adjusted to and makes stay the electric current of keeping feedback loop at least in transistor.

The 3rd embodiment

Fig. 3 is the structural representation according to the communication equipment of third embodiment of the invention.

Communication equipment 100 among Fig. 3 has a driver in its each transmitter, this driver comprises the differential drive circuit according to the embodiment of the invention.

Communication equipment 100 has transmitter 120 and 130, is separately positioned on the both sides of difference transmission lines 110.This communication equipment can two-way communication.

Transmitter 120 and 130 each all have above-mentioned differential drive circuit 2 or 2A according to first or second embodiment.

Communication equipment 100 has receiver 140 and 150, and walking abreast with transmitter 120 and 130 respectively with respect to difference transmission lines 110 is provided with.

Difference transmission lines 110 is connected with terminating resistor Rterm at arbitrary end.

Because differential drive circuit according to an embodiment of the invention can export the electric current identical with target current and arrive load and have nothing to do with load voltage, thus at the other end not to the interference of the output state of transmitter.

Thus, striding load produces by the transmitter 120 at two ends and the perfect and signal of 130 signals of exporting.

Be provided at the receiver 140 and 150 and transmitter 120 and 130 and connect at the two ends of difference transmission lines 110, each receiver can by produce from the load two ends with signal deduct the signal of exporting the transmitter that obtains the other end with each target of receiver 140 and the 150 parallel transmitters 120 that are provided with and 130.

As mentioned above, present embodiment provides coupling as each transistor Q1 of output transistor negative feedback (NFB) to source potential with the driving target voltage values of Q4.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

The advantage of the foregoing description is, for example under the two-way multiplexing situation of in Ethernet (R) 1000BASE-T, carrying out, can be independent of the reception waveform and obtain accurate output current, can under the condition that does not have distortion, produce the accurate and signal of transmission/received signal.

Have again,, can obtain following effect according to this embodiment.

Even, also can export differential signal with the common mode component that needs when the grid voltage-drain current characteristics of MOS transistor (field-effect transistor) is not linear or under discrepant situation between PMOS and the NMOS.

Have again, in this embodiment, owing to, can correctly send by strict and adjust so that the waveform of limiting bandwidth to load as the driving target voltage of input and the good linear between the output voltage.

In addition, present embodiment also has such advantage, and promptly the load driving electric current can be provided with very greatly with the ratio of the current sinking of output stage, so that excellent energy efficient is provided.

Have again, can be independent of loading condition and accurately output and the proportional electric current of target drives voltage.Voltage by observing load and cut a constant times of target drive current by calculating can determine that second drive circuit applies electrical current to load.This makes to be that single transmission line is carried out two-way communication by single load.

Have again, in differential drive circuit, between each of output (output node) and reference potential VSS (for example ground potential GND) and power supply potential VDD, a transistor level and a resistor are only arranged according to present embodiment.

This makes and can be operated by lower voltage, the patent application publication number that this low voltage is lower than Japanese unexamined is disclosed circuit or a similar situation among the 2006-345259, has used the vertical stacking of so-called current source transistor and difference transistor among the latter.

In the foregoing, the driver that comprises differential drive circuit has been described, the communication equipment that comprises this driver has been described as the 3rd embodiment as first and second embodiment.

Below explanation is comprised another structure, comprise according to another structure of the driver 1A of the differential drive circuit of second embodiment with according to another structure of the communication equipment 100 of the 3rd embodiment according to the driver 1 of the differential drive circuit of first embodiment.

At first, will comprise that another structure according to the driver 1 of the differential drive circuit of first embodiment is as the 4th to the tenth embodiment with reference to figure 4 to Figure 11 explanation.

The 4th embodiment

Fig. 4 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fourth embodiment of the invention.

Be that with difference the driving of load is only to utilize as the push-pull circuit of first drive system to implement according to the driver 1B of the 4th embodiment according to the driver 1 of first embodiment.

Particularly, use PMON transistor Q1 and Q2, first and second circuit 21 and 22, resistor R 1 and R2 and DAC3 to carry out the driving of load outside each parts of the driver 1 of the driver 1B among Fig. 4 in Fig. 1.

The drain electrode of PMOS transistor Q1 and Q2 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

According to the 4th embodiment, provide coupling as output transistor transistor Q1 and Q2 in each source potential and drive the negative feedback (NFB) of target power values.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

The 5th embodiment

Fig. 5 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fifth embodiment of the invention.

Driver 1 part that is different from first embodiment according to the driver 1C of the 5th embodiment is that the driving of load only is to utilize to carry out as the pull-down circuit of second drive system among the 5th embodiment.

Particularly, the element of the driver 1 of the driver 1C among Fig. 5 in using Fig. 1, also use nmos pass transistor Q3 and Q4, third and fourth circuit 23 and 24, resistor R 3 and R4 and DAC4 to carry out the driving of load.

The drain electrode of nmos pass transistor Q3 and Q4 is connected respectively to load resistance Rload3 and Rload4, and load resistance Rload3 and Rload4 are connected to the power supply 9 of bias voltage Vbias.

According to the 5th embodiment, the transistor Q3 of coupling as output transistor and each the source potential and the negative feedback (NFB) that drives target voltage values of Q4 are provided.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

The 6th embodiment

Fig. 6 is the circuit diagram that shows the activation configuration that comprises differential drive circuit according to a sixth embodiment of the invention.

Driver 1 part that is different from according to first embodiment according to the driver 1D of the 6th embodiment is that in the 6th embodiment, the differential voltage of output and common-mode voltage are output according to the numerical value Ddiff and the Dcom that provide.

Correspondingly, on draw the DAC3 of side to be divided into two DAC, a DAC3-1 and the 2nd DAC3-2, the DAC4 of drop-down side are divided into two DAC, i.e. the 3rd DAC4-1 and the 4th DAC4-2.

Adder/ subtracter 10,11,12 and 13 is set at the input stage of each DAC3-1,3-2,4-1 and 4-2, and each is used for adding/subtrahend value Ddiff and Dcom.So different numerical value is imported into each DAC3-1,3-2,4-1 and 4-2.

The first and second output node NO1 and the NO2 of differential drive circuit 2D are connected respectively to load resistance Rload1 and Rload2.Load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

Adder/subtracter 10 receives the input of numerical value Ddiff as negative input, and the input that receives numerical value Dcom is as positive input.Adder/subtracter 10 is by calculating the numerical value [Dcom-Ddiff] that obtains the N bit to input, and numerical value [Dcom-Ddiff] is offered DAC3-2.

The input that adder/subtracter 11 receives numerical value Ddiff is as first positive input, and the input that receives numerical value Dcom is as second positive input.Adder/subtracter 11 is by calculating the numerical value [Dcom+Ddiff] that obtains the N bit to input, and numerical value [Dcom+Ddiff] is offered DAC3-1.

The input that adder/subtracter 12 receives numerical value Ddiff is as positive input, and the input that receives numerical value Dcom is as negative input.Adder/subtracter 12 is by calculating the numerical value [Dcom+Ddiff] that obtains the N bit to input, and numerical value [Dcom+Ddiff] is offered DAC4-2.

The input that adder/subtracter 13 receives numerical value Ddiff is as the first negative input, and the input that receives numerical value Dcom is as the second negative input.Adder/subtracter 13 is by calculating the numerical value [Dcom-Ddiff] that obtains the N bit to input, and numerical value [Dcom-Ddiff] is offered DAC4-1.

DAC3-1 have switch SW 3-10 to SW3-1N-1 and current source I3-10 to I3-1N.

As shown in Figure 6, current source I3-10 is connected between the power supply potential source VDD and the first power line LV1 to SW3-1N-1 in couples to I3-1N-1 and switch SW 3-10.Current source I3-1N is connected between the power supply potential source VDD and the first power line LV1.

Numerical value [Dcom+Ddiff] is provided to the control grid of current source I3-10 to I3-1N.

DAC3-2 have switch SW 3-20 to SW3-2N-1 and current source I3-20 to I3-2N.

As shown in Figure 6, current source I3-20 is connected between power supply potential source VDD and the second source line LV2 to SW3-2N-1 in couples to I3-2N-1 and switch SW 3-20.Current source I3-2N is connected between power supply potential VDD and the second source line LV2.

Numerical value [Dcom-Ddiff] is provided to the control grid of current source I3-20 to I3-2N.

DAC4-1 have switch SW 4-10 to SW4-1N-1 and current source I4-10 to I4-1N.

As shown in Figure 6, current source I4-10 is connected between power supply potential VDD and the 3rd power line LV3 to SW4-1N-1 in couples to I4-1N-1 and switch SW 4-10.Current source I4-1N is connected between power supply potential source VDD and the 3rd power line LV3.

Numerical value [Dcom-Ddiff] is provided to the control grid of current source I4-10 to I4-1N.

DAC4-2 have switch SW 4-20 to SW4-2N-1 and current source I4-20 to I4-2N.

As shown in Figure 6, current source I4-20 is connected between power supply potential source VDD and the 4th power line LV4 to SW4-2N-1 in couples to I4-2N-1 and switch SW 4-20.Current source I4-2N is connected between power supply potential source VDD and the 4th power line LV4.

Numerical value [Dcom+Ddiff] is provided to the control grid of current source I4-20 to I4-2N.

In driver 1D, drive target current potential V1 and be provided for resistor R 1 and PMOS transistor Q1, draw the first output node NO1 (output VoutP) on the latter, drive target current potential V3 and be provided for resistor R 3 and nmos pass transistor Q3, the drop-down first output node NO1 of the latter (output VoutP).

Have again, drive target current potential V2 and be provided for resistor R 2 and PMOS transistor Q2, draw the second output node NO2 (output VoutP) on the latter, drive target current potential V4 and be provided for resistor R 4 and NMON transistor Q4, the drop-down second output node NO2 of the latter (output VoutP).

By four DAC, promptly DAC3-1,3-2,4-1 and 4-2 generate driving target voltage V1 to V4.

As numeral input to DAC3-1,3-2,4-1 and 4-2, [Dcom+Ddiff], [Dcom-Ddiff], [Dcom-Ddiff], [Dcom+Ddiff] is presented with respect to two numerical data Dcom and Ddiff.

Suppose that the analog voltage corresponding to Ddiff and Dcom is Vdiff and Vcom, following relational expression is set up.

Equation 6:

VDD-V1＝+Vdiff+Vcom

VDD-V2＝-Vdiff+Vcom

V3-GND＝-Vdiff-Vcom

V4-GND＝+Vdiff-Vcom

When the resistance of resistor R 1 to R4 all is R, the output current IQ1 of PMOS transistor Q1, the output current IQ3 of nmos pass transistor Q3 and provide by following equation from the electric current I VOutP that the first output node NO1 flows to load.

Equation 7:

IQ1＝(+Vdiff+Vcom)/R

IQ3＝(-Vdiff-Vcom)/R

IVoutP＝2×(+Vdiff+Vcom)/R

Similarly, when the resistance of resistor R 1 to R4 all is R, the output current IQ2 of PMOS transistor Q2, the output current IQ4 of nmos pass transistor Q4 and provide by following equation from the electric current I VoutN that the second output node NO2 flows to load.

Equation 8:

IQ2＝(-Vdiff+Vcom)/R

IQ4＝(+Vdiff-Vcom)/R

IVoutN＝2·(-Vdiff+Vcom)/R

The current potential VoutP of the first output node NO1 side and the second output node NO2 side current potential VoutN are provided by equation.

Equation 9:

VoutP＝Vbias+2·Rload·(+Vdiff+Vcom)/R

VoutN＝Vbias+2·Rload·(-Vdiff+Vcom)/R

Therefore, differential voltage VDPN and the common-mode voltage VIPN of output VoutP and VoutN are as follows.

Equation 10:

VDPN＝4·Rload·Vdiff/R

VIPN＝Vbias+2·Rload·Vcom/R

The differential voltage VDPN and the common-mode voltage VIPN that this means output export according to digital value Ddiff and Dcom.

Even when adding the common-mode voltage driving, according to the circuit of the embodiment of the invention accurately control flows cross the electric current of resistor R 1 to R4, the i.e. electric current of output from transistor Q1 to Q4 is not relied on the level of common mode output and is adjusted or is out of shape so difference output can accurately export.

According to the 6th embodiment, provide a kind of coupling as each transistor Q1 of output transistor source potential and the negative feedback (NFB) that drives target voltage values to Q4.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

Even when the grid voltage-drain current characteristics of MOS transistor (field-effect transistor) is non-linear or when variant, also can exports the differential signal with the common mode component that needs between PMOS and NMOS.

Have again, in the 6th embodiment,, can correctly be sent to load by the strict waveform that limits bandwidth owing to favorable linearity between driving target voltage that provides as input and the output voltage.

In addition, another advantage of the 6th embodiment is that the load driving electric current can be provided with very greatly with the ratio of output stage current sinking, thereby the excellent energy utilance is provided.

Have again, can accurately be exported with the proportional electric current of target drives voltage and irrelevant with the situation of load.

Have, difference output can accurately be exported and do not relied on common mode output level and be adjusted or be out of shape again.

The 7th embodiment

Fig. 7 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of seventh embodiment of the invention.

Difference according to the driver 1D of the driver 1E of seventh embodiment of the invention and the 6th embodiment is that the driving of load is only to utilize as the pull-up circuit of first drive system to realize in the present embodiment.

Particularly, the driver 1E of Fig. 7 is except each parts of the driver 1D that utilizes Fig. 6, also utilize PMOS transistor Q1 and Q2, first and second circuit 21 and 22, resistor R 1 and R2, DAC3-1 and 3-2 and adder/ subtracter 10 and 11 to carry out load driving.

The drain electrode of PMOS transistor Q1 and Q2 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

According to the 7th embodiment, a kind of coupling each transistor Q1 and the source potential and the negative feedback (NFB) that drives target voltage values of Q2 are provided as output transistor.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

Have, the differential voltage VDPN of output and common-mode voltage VIPN can be according to numerical value Ddiff and Dcom outputs again.

In this case, difference output can accurately be exported and not relied on common mode output level and be adjusted or be out of shape.

The 8th embodiment

Fig. 8 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of eighth embodiment of the invention.

Difference according to the driver 1D of the driver 1F of eighth embodiment of the invention and the 6th embodiment is that the driving of load is only to utilize as the pull-down circuit of second drive system to realize in the present embodiment.

Particularly, the driver 1F of Fig. 8 is except each parts of the driver 1D that utilizes Fig. 6, also utilize nmos pass transistor Q3 and Q4, third and fourth circuit 23 and 24, resistor R 3 and R4, DAC4-1 and 4-2 and adder/ subtracter 12 and 13 to carry out load driving.

The drain electrode of nmos pass transistor Q3 and Q4 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

According to the 8th embodiment, a kind of coupling each transistor Q3 and the source potential and the negative feedback (NFB) that drives target voltage values of Q4 are provided as output transistor.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

Have, the differential voltage VDPN of output and common-mode voltage VIPN can be according to numerical value Ddiff and Dcom outputs again.

In this case, difference output can accurately be exported and not relied on common mode output level and be adjusted or be out of shape.

The 9th embodiment

Fig. 9 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of ninth embodiment of the invention.

Difference according to the driver 1F of the driver 1G of ninth embodiment of the invention and the 8th embodiment is that present embodiment driver 1G has stabilizing circuit 30, is used for the stable output of DAC.

The stabilizing circuit 30 of DAC has PMOS transistor QA and QB, operational amplifier A 31 and A32, resistor R A31 and RA32 and reference resistor Rext31 and power supply V31.

The source electrode of PMOS transistor QA is connected to power supply potential VDD, and drain electrode is connected to the end of resistor R A31 and the non-inverting input (+) of operational amplifier A 31.The other end of resistor R A31 is connected to reference potential VSS.

The grid of PMOS transistor QA is connected to the output of operational amplifier A 31.

The source electrode of PMOS transistor QB is connected to an end and operational amplifier A 32 inverting inputs (-) of reference resistor Rext31.

The drain electrode of PMOS transistor QB is connected to the end of resistor R A32 and the inverting input (-) of operational amplifier A 31.

The grid of PMOS transistor QB is connected to the output of operational amplifier A 32.The other end of reference resistor Rext31 is connected to power supply potential VDD, and the other end of resistor R A32 is connected to reference potential VSS.

The noninverting input (+) of operational amplifier A 32 is connected to provides the power supply of reference voltage Vref V31.

DAC4-1 have switch SW 4-10 to SW4-1N-1 and PMOS transistor Q4-10 to Q4-1N as current source.

As shown in Figure 9, PMOS transistor Q4-10 is connected between power supply potential VDD and the 3rd power line LV3 to SW4-1N-1 in pairs to Q4-1N-1 and switch SW 4-10.The source electrode of PMOS transistor Q4-1N is connected to power supply potential VDD, and drain electrode is connected to the 3rd power line LV3.

PMOS transistor Q4-10 is connected to the output of the operational amplifier A 31 of stabilizing circuit 30 to the grid of Q4-1N.

DAC4-2 have switch SW 4-20 to SW4-2N-1 and PMOS transistor Q4-20 to Q4-2N as current source.

As shown in Figure 9, PMOS transistor Q4-20 is connected between power supply potential VDD and the 4th power line LV4 to SW4-2N-1 in pairs to Q4-2N-1 and switch SW 4-20.The source electrode of PMOS transistor Q4-2N is connected to power supply potential VDD, and drain electrode is connected to the 4th power line LV3.

PMOS transistor Q4-20 is connected to the output of the operational amplifier A 31 of stabilizing circuit 30 to the grid of Q4-2N.

In stabilizing circuit 30, transistor QA and resistor R A31 produce and drive target voltage V3 and V4 as the duplicate (replica) of DAC4-1 and 4-2.Comprise stabilizing circuit 30 output of these duplicates and the identical output VA of output that imports when specific numeral when being provided among DAC4-1 and the 4-2 each.

Negative feedback (NFB) is applied to exporting VA so that obtain the relation of following equation representative.

Equation 11:

VA＝Vref·(RA/Rext)

Therefore, when special value was input among DAC4-1 and the 4-2 each, output also became VA.

When R=R3=R4, the transconductance ratio of output stage is 1/R, so output potential is as follows:

Equation 12:

VA·Rload/R＝Vref·(RA/R)·(Rload/Rext)

Suppose that resistor R 31 and R3, R4 are the resistance in the identical integrated circuit, and their ratio comes down to constant, load resistance Rloadl and Rload2 and reference resistance Rext31 are the outer precision resisters of integrated circuit, and their ratio also is constant.

Therefore, when specific numerical value was input among DAC4-1 and the 4-2 each, output was the integral multiple of reference voltage Vref.

If reference voltage Vref is the burning voltage that is provided by bandgap reference output or finishing (trimmed) biasing generative circuit, this means when special value input is provided, stabilized according to the output of the driver 1G of the 9th embodiment.

Identical stabilizing circuit also can be used for the driver 1D of driver 1C, Fig. 6 of driver 1B, Fig. 5 of driver 1, Fig. 4 of Fig. 1 and the driver 1E of Fig. 7.

According to the 9th embodiment, a kind of coupling each transistor Q3 and the source potential and the negative feedback (NFB) that drives target voltage values of Q4 are provided as output transistor.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

Have, the differential voltage VDPN of output and common-mode voltage VIPN can be according to numerical value Ddiff and Dcom outputs again.

In this case, difference output can accurately be exported and not relied on common mode output level and be adjusted or be out of shape.

Have again, when the output that specific numerical value is imported when given can be stabilized.

The tenth embodiment

Figure 10 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of tenth embodiment of the invention.

The driver 1C part that is different from the 5th embodiment according to the driver 1H of the tenth embodiment is that the upstream stage at DAC in the present embodiment is provided with the multiplier 14 that input be multiply by coefficient C, makes that output becomes constant with respect to specific numerical value input.

Coefficient C generates by having the stabilizing circuit 40 that duplicates the DAC function.

Stabilizing circuit 40 has PMOS transistor Q41, resistor R A41 and RA42, reference resistor Rext41, operational amplifier A 41 and A42, and power supply V41.

Stabilizing circuit 40 also have switch SW 41-0 to SW41-N-1, current source I41-0 to I41-N, power line LV41, multiplier 41 and state machine 42.

The source electrode of PMOS transistor P41 is connected to the end of reference resistor Rext41 and the inverting input (-) of operational amplifier A 41.

The drain electrode of PMOS transistor Q41 is connected to the end of resistor R A41 and the inverting input (-) of operational amplifier A 42.

The grid of PMOS transistor Q41 is connected to the output of operational amplifier A 41.The other end of reference resistor Rext41 is connected to power supply potential VDD, and the other end of resistor R A41 is connected to reference potential VSS.

The noninverting input (+) of operational amplifier A 41 is connected to provides the power supply of reference voltage Vref V41.

The noninverting input (+) of operational amplifier A 42 is connected to power line LV41.

The end of resistor R A42 is connected to power line LV41, and the other end is connected to reference potential VSS.

As shown in figure 10, current source I41-0 is connected between power supply potential VDD and the power line LV41 to SW41-1N-1 in pairs to I41-N-1 and switch SW 41-10.Current source I41-1N is connected between power supply potential VDD and the power line LV41.

Be provided to the control gate pole of switch SW 41-10 by the N Bit data that is used for ON/OFF control that fixed value be multiply by coefficient C acquisition to SW41-1N-1.

Multiplier 41 provides by fixed value being multiply by the control gate pole of N Bit data to switch SW 41-10 to SW41-1N-1 that coefficient C obtains.

State machine 42 is by obtaining the value of coefficient C from minimum value scanning, the output level P of the operational amplifier A 42 of device changes to 1 from 0 as a comparison on this value.State machine 42 provides the coefficient C that obtains to multiplier 41 and 14.

Figure 11 is the state machine operational flow diagram that shows according to the stabilizing circuit of tenth embodiment of the invention.

At first, state machine 42 is set to minimum value (ST1) with coefficient C.

Next, state machine 42 determines that the output P of operational amplifier A 42 is 0 still is 1 (ST2).

If determine that at step ST2 output P is 0, state machine 42 determines whether coefficient C is maximum (ST3).

If determine that at step ST3 coefficient C is not a maximum, state machine 42 adds 1 for the value of coefficient C, and begins to repeat this process from step ST2.

Then, in case determine that at step ST2 output P is 1, then state machine 42 stops this process.

In case determine that at step ST3 coefficient C has reached maximum, state machine 42 also stops this process.

In this way, state machine 42 begins scan fraction C and finds the value of coefficient C from minimum value, and comparator output changes to 1 from 0 on this value.

Comprise the common following expression of output of the stabilizing circuit 40 (being transfused to it) of DAC copy function by fixed value being multiply by the value that coefficient C obtains.

Equation 13:

VA＝Vref·(RA/R)

Be provided the differential drive circuit 2H as output circuit that aforesaid identical numerical value is imported, also the output voltage identical with VA is used to drive target voltage V3 or V4, and this is because this numerical value is multiplied by coefficient C in the input of DAC4.Suppose R=R3=R4, the output voltage of this moment obtains as follows, and is stabilized to a steady state value.

Equation 14:

VA·(Rload/R)＝Vref·(RA/R)·(Rload/Rext)

Identical stabilizing circuit can also be applied to the driver 1D of driver 1C, Fig. 6 of driver 1B, Fig. 5 of driver 1, Fig. 4 of Fig. 1 and the driver 1E of Fig. 7.

According to the tenth embodiment, a kind of coupling each transistor Q3 and the source potential and the negative feedback (NFB) that drives target voltage values of Q4 are provided as output transistor.So, even accurately export target electric current is arranged in drain potential under the situation of fluctuation also.

In this case, difference output can accurately be exported and not relied on common mode output level and be adjusted or be out of shape.

Have again, the output when providing specific numerical value to import can be provided.

The front has illustrated other structure according to the driver that comprises differential drive circuit 1 of first embodiment of the invention.

12 to 19 explanations are as other structure according to the driver 1A of the differential drive circuit of second embodiment of the invention of comprising of the 11 to the 16 embodiment below with reference to accompanying drawings.

The 11 embodiment

Figure 12 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of eleventh embodiment of the invention.

The driver 1A part that is different from according to second embodiment according to the driver 1I of the 11 embodiment is that the driving of load is only to utilize as the pull-up circuit of first drive system to realize in the present embodiment.

Particularly, each parts of the driver 1A of the driver 1I among Figure 12 in Fig. 2, also use PMOS transistor Q1 and Q2, first and second circuit 21 and 22, resistor R 1 and R2 and differential amplifier 6 to carry out the driving of load.

The drain electrode of PMOS transistor Q1 and Q2 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

According to the 11 embodiment, provide coupling as each transistor Q1 of output transistor and the source voltage and the negative feedback (NFB) that drives target voltage values of Q2.Even so occur under the situation of fluctuation also accurately export target electric current in the drain potential.

The 12 embodiment

Figure 13 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of twelveth embodiment of the invention.

The driver 1A part that is different from second embodiment according to the driver 1J of the 12 embodiment is that in the present embodiment, the driving of load is only to utilize as the pull-down circuit of second drive system to realize.

Particularly, each parts of the driver 1A of the driver 1J among Figure 13 in Fig. 2, also use nmos pass transistor Q3 and Q4, third and fourth circuit 23 and 24, resistor R 3 and R4 and differential amplifier 7 to carry out the driving of load.

The drain electrode of nmos pass transistor Q3 and Q4 is connected respectively to load resistance Rload3 and Rload4, and load resistance Rload3 and Rload4 are connected to the power supply 9 of bias voltage Vbias.

According to the 12 embodiment, provide the source potential and the negative feedback (NFB) that drive target voltage values of coupling as each the transistor Q3 and the Q4 of output transistor.Even so occur under the situation of fluctuation also accurately export target electric current in the drain potential.Simultaneously, can accurately export the common-mode voltage of expectation.

The 13 embodiment

Figure 14 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of thriteenth embodiment of the invention.

The driver 1A part that is different from second embodiment according to the driver 1K of the 13 embodiment is that in the present embodiment, driver 1K has skew adjunct circuit 50, and this circuit 50 appends to a skew and drives target current potential V1 on each of V4.

The first and second output node NO1 and the NO2 of differential drive circuit 2K are connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

Skew adjunct circuit 50 has differential amplifier 51, current mirroring circuit 52 and 53 and resistor R 51.

Differential amplifier 51 has PMOS transistor QP51 and QP52, resistor R 51 and current source I51 and 152.

Current mirroring circuit 52 has nmos pass transistor QN51 to QN53 and current source I53.

Current mirroring circuit 53 has nmos pass transistor QN54 and QN55, PMOS transistor QP53 to QP55 and current source I54.

The source electrode of the PMOS transistor QP51 of differential amplifier 51 is connected to current source I51, and drain electrode is connected to the drain electrode of nmos pass transistor QN54 of current mirroring circuit 52 and the grid of nmos pass transistor QN54 and QN55.

The source electrode of PMOS transistor QP52 is connected to current source I52, and drain electrode is connected to the drain electrode of the nmos pass transistor QN51 of current mirroring circuit 52.

Resistor R 51 is connected between the source electrode of the source electrode of PMOS transistor QP51 and PMOS transistor QP52.

The grid of PMOS transistor QP51 is connected to the power line of voltage VcomP.The grid of PMOS transistor QP52 is connected to the power line of voltage VcomN.

In current mirroring circuit 52, the drain electrode of nmos pass transistor QN51 is connected to the grid of grid, nmos pass transistor QN52 and the QN53 of current source I53, nmos pass transistor QN51 itself, and source electrode is connected to reference potential VSS.

The source electrode of nmos pass transistor QN52 is connected to reference potential VSS, and drain electrode is connected to the output of driving target current potential V1 of first differential amplifier 6, promptly is connected to the tie point between the drain electrode of resistor R 1 and nmos pass transistor Q61.

The source electrode of nmos pass transistor QN53 is connected to reference potential VSS, and drain electrode is connected to the output of driving target current potential V2 of first differential amplifier 6, promptly is connected to the tie point between the drain electrode of resistor R A2 and nmos pass transistor Q62.

In current mirroring circuit 53, the source electrode of nmos pass transistor QN54 and QN55 is connected to reference potential VSS.

The drain electrode of nmos pass transistor QN55 is connected to drain electrode and the current source I54 of PMOS transistor QP53.

The source electrode of PMOS transistor QP53 is connected to power supply potential VDD, and drain electrode is connected to the grid of PMOS transistor QP53 self and the grid of PMOS transistor QP54 and QP55.

The source electrode of PMOS transistor QP54 is connected to power supply potential VDD, and drain electrode is connected to the output of driving target current potential V4 of second differential amplifier 7, promptly is connected to the tie point between the drain electrode of resistor R A4 and PMOS transistor Q72.

The source electrode of PMOS transistor QP55 is connected to power supply potential VDD, and drain electrode is connected to the output of driving target current potential V3 of second differential amplifier 7, promptly is connected to the tie point between the drain electrode of resistor R A3 and PMOS transistor Q71.

In driver 1K, differential amplifier 51 is provided to each with a skew and drives target current potential V1 to V4, and this skew is the differential pair that increases.

With as the voltage VcomP that is provided to differential amplifier 51 and VcomN be balance the time relatively, when being positive signal for the signal of making [VcomP-VcomN], the electric current that flows to first and second differential amplifiers 6 and 7 changes.

That is to say that when being positive signal for the signal of making [VcomP-VcomN], the resistor R A1 of first differential amplifier 6 of flowing through and the electric current of RA2 increase, the resistor R A3 of second differential amplifier 7 of flowing through and the electric current of RA4 reduce.

The result is to drive target current potential V1 and drive target current potential V2 and reduce the resistor R 1 of the differential drive circuit 2K that flows through and the increase of the electric current of R2.Reduce owing to drive target current potential V3 and drive target current potential V4, the electric current of resistor R of flowing through 3 and R4 reduces.

That is to say, increase that reduce from the pull-down current of the third and fourth transistor Q3 and Q4 output, the common-mode voltage of therefore exporting VoutP and VoutN raises from the pull-up current of the first and second transistor Q1 and Q2 output.

Yet because the increase of the output of the first and second transistor Q1 and Q2 is identical, reducing of the output of the third and fourth transistor Q3 and Q4 also is identical, do not change in differential voltage.

That is to say that this circuit also can irrespectively accurately be exported difference output with the common-mode voltage level.

According to the 13 embodiment, provide coupling as each transistor Q1 of output transistor negative feedback (NFB) to source potential with the driving target voltage values of Q4.So, even in drain potential, have under the situation of fluctuation, also export target electric current accurately.

Even when the grid voltage-drain current characteristics of MOS transistor (field-effect transistor) is not linear or when variant, can exports the differential signal with the common mode component that needs yet between PMOS and NMOS.

Have again, in the 13 embodiment, owing to, can correctly be sent to load by the strict waveform of adjusting with limiting bandwidth as the driving target voltage of input and the good linear between the output voltage.

In addition, the 13 embodiment is also advantageous in that, thus the ratio of load driving electric current and the current sinking of output stage can be provided with the very big excellent energy utilization rate that provides.

Have again, can irrespectively accurately be exported with the situation of load with the proportional electric current of target drives voltage.

Moreover difference output can accurately be exported, and does not rely on common mode output level and be adjusted or be out of shape.

The 14 embodiment

Figure 15 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fourteenth embodiment of the invention.

The driver 1K part that is different from the 13 embodiment according to the driver 1L of the 14 embodiment is that in the present embodiment, the driving of load is only to utilize as the pull-up circuit of first drive system to realize.

Particularly, each parts of the driver 1K of driver 1L among Figure 15 in using Figure 14, also use PMOS transistor Q1 and Q2, first and second circuit 21 and 22, resistor R 1 and R2 and differential amplifier 6, differential amplifier 51 and current mirroring circuit 52 to carry out the driving of load.

The drain electrode of PMOS transistor Q1 and Q2 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

Yet the drain electrode that it should be noted that the PMOS transistor QP51 of differential amplifier 51 is connected to reference potential VSS.

According to the 14 embodiment, provide the source potential and the negative feedback (NFB) that drive target voltage values of coupling as each the transistor Q1 and the Q2 of output transistor.Like this, even in drain potential, have under the situation of fluctuation, export target electric current accurately still.

Have, difference output can accurately be exported again, and does not rely on common mode output level and be adjusted or be out of shape.

The 15 embodiment

Figure 16 is the circuit diagram that shows according to the activation configuration that comprises differential drive circuit of fifteenth embodiment of the invention.

The driver 1K part that is different from the 13 embodiment according to the driver 1M of the 15 embodiment is that in the present embodiment, the driving of load is only to utilize as the pull-down circuit of second drive system to realize.

Particularly, each parts of the driver 1K of driver 1M among Figure 16 in using Figure 14, also use nmos pass transistor Q3 and Q4, third and fourth circuit 23 and 24, resistor R 3 and R4 and differential amplifier 7, differential amplifier 51 and current mirroring circuit 53 to carry out the driving of load.

The drain electrode of nmos pass transistor Q3 and Q4 is connected respectively to load resistance Rload1 and Rload2, and load resistance Rload1 and Rload2 are connected to the power supply 8 of bias voltage Vbias.

Yet the drain electrode that it should be noted that the PMOS transistor QP52 of differential amplifier 51 is connected to reference potential VSS.

Have, in current mirroring circuit 53, do not use nmos pass transistor QN54 and QN55 among Figure 14, the drain electrode of the PMOS transistor QP51 of differential amplifier 51 is connected to the drain electrode of current source I54 and PMOS transistor QP53.

According to the 15 embodiment, provide the source potential and the negative feedback (NFB) that drive target voltage values of coupling as each the transistor Q1 and the Q2 of output transistor.Like this, even in drain potential, have under the situation of fluctuation, export target electric current accurately still.

Have, difference output can accurately be exported again, and does not rely on common mode output level and be conditioned or be out of shape.

The 16 embodiment

Figure 17 has shown the circuit diagram according to the activation configuration that comprises differential drive circuit of sixteenth embodiment of the invention.

Following parts have been increased according to the 16 embodiment driver 1N beguine according to the structure of the driver 1I of the 12 embodiment.

Also promptly, driver 1N has PMOS transistor QA6l and the QA62 that is used for resistance adjustment, the load resistance RA1 of the differential amplifier 6 of this transistor AND gate first order and RA2 parallel connection.Each grid potential Vadj of PMOS transistor QA61 and QA62 is by gain adjusting circuit 60 control.

Driver 1N has a transconductance circuit in output stage, the output of this circuit with drive target current potential V1 and V2 is proportional and the electric current that is inversely proportional to resistance R 1 and R2.

The gain of supposing the differential amplifier 6 of the first order is Gamp, and the overall gain Gtot that exports [VoutP-VoutN] to the difference of differential drive circuit 2N from the difference input [Vinp-VinN] of first order differential amplifier 6 is expressed from the next so:

Equation 15

Gtot＝Gamp·(1/R)·Rload

Here, R represents definite combination resistance by resistor R 1, R2 and the R12 of differential drive circuit 2N.Because each resistor R all is placed in the integrated circuit, if load resistance Rload is placed on outside the integrated circuit, so, the ratio of R and Rload is not a constant.The gain of differential amplifier 6 also can change according to the apparatus characteristic or the temperature of integrated circuit.

Therefore, overall gain also is subjected to the big manufacturing variability of integrated circuit and the influence of temperature drift.

Therefore, circuit shown in Figure 17 has adopted said structure to guarantee that overall gain is that Gtot is constant.

Also promptly, in the circuit of Figure 17, the PMOS transistor QA61 and the QA62 that are used for resistance adjustment are in parallel with the load resistance RA1 and the RA2 of the differential amplifier 6 of the first order, thereby form amplifying stage (level shifter) 6A.

Circuit among Figure 17 constitutes like this, that is, make its grid potential Vadj by gain adjusting circuit 60 controls.

Figure 18 is the circuit diagram that shows first structure of the gain adjusting circuit 60 among Figure 17.

Gain adjusting circuit 60A among Figure 18 has duplicate circuit 61 on the amplifying stage 6A and reference voltage and offset voltage provides part (after this being called " voltage provides part ") 62.

Gain adjusting circuit 60A also have with a skew append to duplicate circuit 61 output skew adjunct circuit 63 and duplicate the feedback amplifier (error amplifier) 64 of output with the skew balance.

Duplicate circuit 61 has the structure identical with the duplicate circuit of amplifying stage 6A.

Also promptly, duplicate circuit 61 has nmos pass transistor QN61 and QN62, resistor R B1, RB2, RB61, current source IB61 and IB62 and PMOS transistor QP61 and QP62.

In duplicate circuit 61, the source electrode of nmos pass transistor QN61 is connected to current source IB61, and drain electrode is connected to the drain electrode of an end and the PMOS transistor QP61 of resistor R B1, and node ND61 is formed by their tie point.The source electrode of the other end of resistor R B1 and PMOS transistor QP61 is connected to power supply potential VDD.

The source electrode of nmos pass transistor QN62 is connected to current source IB62, and drain electrode is connected to the drain electrode of an end and the PMOS transistor QP62 of resistor R B2, and node ND62 is formed by their tie point.The source electrode of the other end of resistor R B2 and PMOS transistor QP62 is connected to power supply potential VDD.

Resistor R B61 is connected between the drain electrode of the drain electrode of nmos pass transistor QN61 and nmos pass transistor QN62.

The grid of nmos pass transistor QN61 and QN62 is connected to voltage provides the reference voltage of part 62 that part is provided.

The output of error amplifier 64 is fed back to the grid of PMOS transistor QP61 and QP62.

The output of error amplifier 64 is provided as each the PMOS crystal QA61 of amplifying stage 6A and the grid potential Vadj of QA62.

Voltage provides part 62 to have reference voltage source V61, monitoring resistor device Rpoly, reference resistor Rext and operational amplifier A 61 and A62.

Voltage provides part 62 to have PMOS transistor QP63 to QP66, nmos pass transistor QN63 and resistor R 62, R63 at the reference voltage outlet side.

The end of monitoring resistor device Rpoly is connected to the drain electrode of the non-inverting input (+) and the PMOS transistor QP63 of operational amplifier A 61, and the other end is connected to reference potential VSS (for example ground potential GND).

The source electrode of PMOS transistor QP63 is connected to power supply potential VDD, and grid is connected to the output of operational amplifier A 61.

The source electrode of PMOS transistor QP64 is connected to power supply potential VDD, and drain electrode is connected to an end of resistor R 62, and its connected node ND63 is connected to the grid of the NOMS transistor QN61 of duplicate circuit 61.

One end of resistor R 62 is connected to an end of resistor R 63, and its connected node ND64 is connected to the grid of the NOMS transistor QN62 of duplicate circuit 61.The other end of resistor R 63 is connected to reference potential VSS.

The inverting input (-) separately of operational amplifier A 61, A62 jointly is connected to reference voltage source V61.

The end of reference resistor Rext is connected to the drain electrode of the non-inverting input (+) and the PMOS transistor QP65 of operational amplifier A 62.The source electrode of PMOS transistor QP65 and QP66 is connected to power supply potential VDD, and its grid separately is connected to the output of operational amplifier A 62.

The drain electrode of PMOS transistor QP66 is connected to the drain and gate of nmos pass transistor QN63, and its connected node ND65 is connected to the importation of skew adjunct circuit 63.

Offset voltage increases part 63 and has PMOS transistor QP67 and QP68, NOMS transistor QN64 and QN65 and resistor R 64 and R65.

In skew adjunct circuit 63, the source electrode of PMOS transistor QP67 is connected to power supply potential VDD, and drain electrode is connected to an end of resistor R 64, and grid is connected to the node ND62 of the high outlet side (VH) of duplicate circuit 61.

The other end of resistor R 64 is connected to the drain electrode of nmos pass transistor QN64, and its connected node ND66 is connected to the inverting input (-) of error amplifier 64.NOMS transistor QN64 source electrode is connected to reference potential VSS.

The source electrode of PMOS transistor QP68 is connected to power supply potential VDD, and drain electrode is connected to an end of resistor R 65, and its connected node ND67 is connected to the non-inverting input (+) of error amplifier 64.

The grid of PMOS transistor QP68 is connected to the node ND61 of the low outlet side (VL) of duplicate circuit 61.

The other end of resistor R 65 is connected to the drain electrode of nmos pass transistor QN65, and the source electrode of nmos pass transistor QN64 is connected to reference potential VSS.

The grid of NOMS transistor QN64, QN65 is connected to the node ND65 that voltage provides the offset voltage outlet side of part 62 jointly.

Here, reference resistor Rext is the resistance outside the integrated circuit and keeps ratio with the load resistance accurately.Monitoring resistor device Rpoly is the resistance in the integrated circuit, and the accurate ratio of maintenance always and R.

In the circuit of Figure 18, reference potential Vref is provided to the state of monitoring resistor device Rpoly and is realized by negative feedback (NFB).

The electric current of monitoring resistor device Rploy of flowing through under the sort of state flows through the bias resistor R62 of input of the differential pair of duplicate circuit, and this is owing to comprise the current mirror of PMOS transistor QP64.The result is that the NOMS transistor QN61 of duplicate circuit 61, the input of the difference of the formed differential amplifier of QN62 become α * Vref.

Here, α is the ratio of monitoring resistor device Rpoly and bias resistor R62.If these resistors are fabricated onto in the same integrated circuit, then whenever α becomes the value of substantial constant.

Reference resistor Rext is in the state that has been provided reference voltage Vref, and the same current of the reference resistor of flowing through Rext also is sent to output offset resistor R 64 and R65.

By also output offset resistor R 64 being fabricated onto in the integrated circuit identical with monitoring resistor device Rpoly with R65, also can make the ratio beta between them is constant substantially.

Utilize such structure, output offset voltage is proportional to the ratio that reference voltage multiply by monitoring resistor device Rpoly and reference resistor Rext.

Provide the output of the differential amplifier of the duplicate circuit 61 that is offset to be imported into error amplifier 64 to it, used negative feedback so that the input of error amplifier 64 is balanced by the load regulation PMOS transistor QP61 of operation differential amplifier and the grid of QP62.

If set up this balance, this just means that the gain G amp of differential amplifier has done following adjusting.

Equation 16

Gamp＝(Vref＊β＊Rpoly/Rext)/(α*Vref)＝(1/α)＊β＊Rpoly/Rext

Because R also is the combined resistance of integrated circuit resistor, R keeps the constant ratio to monitoring resistor Rpoly.

Suppose R=Rpoly/ γ, rewrite the overall gain equation and then provide following equation.

Gtot＝(1/α)＊β＊γ＊Rload/Rext

Because each is the interior resistance ratio of identical as mentioned above integrated circuit for α, β and γ, therefore has steady state value basically, this steady state value is neither made variability influences also not temperature influence.

Suppose that Rload and Rext are the resistance outside the integrated circuit and have accurate absolute value and very little temperature characterisitic, then ratio R load/Rext also is constant.

Therefore, this equation shows that the circuit according to the 16 embodiment has provided stable overall gain, and variability is neither made in this gain influences also not temperature influence.

By switching the polarity of this gain adjusting circuit, can implement the gain-adjusted of drop-down drive circuit shown in Figure 13.

For the push-and-pull drive circuit according to second embodiment, these two carries out this adjusting can to utilize circuit shown in Figure 17 and its reversed polarity circuit.

Figure 19 is the circuit diagram that shows second structure of gain adjusting circuit 60 shown in Figure 17.

The difference of gain adjusting circuit 60B shown in Figure 19 and gain adjusting circuit 60A shown in Figure 180 is as follows.

Also promptly, make the current ratio controlled signal TRIM that the electric current of monitoring resistor device Rpoly flows in the current mirroring circuit of input bias resistor R62 of operational amplifier of duplicate circuit 61 that flows through slightly change.

Particularly, provide among the part 62A at voltage, PMOS transistor QP70 is in parallel with PMOS transistor QP64 to QP73, forms current mirroring circuit.

The drain electrode of PMOS transistor QP70 is connected to node ND63, and source electrode is connected to the drain electrode of PMOS transistor QP72, and the source electrode of PMOS transistor QP72 is connected to power supply potential VDD.

The drain electrode of PMOS transistor QP71 is connected to node ND63, and source electrode is connected to the drain electrode of PMOS transistor QP73, and the source electrode of PMOS transistor QP73 is connected to power supply potential VDD.

The grid of PMOS transistor QP70 and QP71 is connected to the output of operational amplifier A 61, is connected with the grid of PMOS transistor QP64 jointly.

The grid of PMOS transistor QP72 is connected to the power line of control signal TRIM1, and the grid of PMOS transistor QP73 is connected to the power line of control signal TRIM2.

Provide among the part 62A at voltage, the current ratio that is sent to input bias resistor R62 by current mirroring circuit by control signal TRIM1 and TRIM0 by this PMOS transistor QP72 of ON/OFF and QP73 and slight the change.

This is equivalent to the ratio cc of regulating between monitoring resistor device Rpoly and the bias resistor R62.The result is also can regulate overall gain.

Even resistivity α, β and γ in the integrated circuit are constant substantially, also have slight error owing to make variability.If make a large amount of integrated circuits, under few situation, have one and have big error.

Among the gain adjusting circuit 60B in Figure 19, can proofread and correct by control signal TRIM1 and TRIM0 by the overall gain that the resistance ratio error causes owing to make variability.

The polarity of circuit of counter-rotating Figure 19, and with the reversed polarity combination of circuits use make can be applied to shown in Figure 13 according to the circuit of the 14 embodiment and the circuit shown in second embodiment.

In aforementioned, provided another structure according to the driver 1A that comprises differential drive circuit of second embodiment of the invention.

20-23 explanation is as another structure according to the communication equipment of third embodiment of the invention of the 17 to the 20 embodiment below with reference to the accompanying drawings.

The 17 embodiment

Figure 20 is the schematic diagram of demonstration according to the structure of the communication equipment of seventeenth embodiment of the invention.

, except having structure, be provided with transmitter 160, be provided with receiver 170 and bias supply 180 according to the communication equipment 100A of the 17 embodiment in transmitter 130 sides in transmitter 120 sides according to the communication equipment 100 of the 3rd embodiment.

One end of difference transmission lines 110 is by near the single terminating resistor Rterm1 terminating the transmitter 120, and the output of transmitter 160 is connected to difference transmission lines 110 through two terminating resistor Rterm2.

The other end of difference transmission lines 110 is by near the single terminating resistor Rterm1 terminating the transmitter 130, and the output of transmitter 160 is connected to DC bias supply 180 through two terminating resistor Rterm2.

Receiver 170 is connected to the other end of difference transmission lines 110.

Transmitter 120 and 130 comprises for example above-mentioned differential drive circuit 2 or 2A according to first or second embodiment.

Whenever differential drive circuit (output circuit) according to this embodiment irrespectively all exports accurate difference current with output potential.Therefore,, in differential signal, do not have disturbance yet, and almost do not cause the leakage of following the common-mode signal that differential signal drives of the noise of common-mode signal even be added to differential signal to last when another signal of common mode current potential.

As mentioned above, in the communication equipment 100A according to the 17 embodiment, difference transmission lines 110 is by single resistor R term1 and the parallel terminating of two resistors in series Rterm2 (1 ,-2).The node of each resistor R term2 is applied in the Low ESR signal voltage in transmitter 120 sides, is biased with dc voltage in transmitter 130 sides.

As for the impedance when from difference transmission lines 110 side transmitters, in differential mode and common mode, see parallel resistance and two resistors in parallel Rterm2 of terminating resistor Rterm1 and Rterm2 respectively.

For example, suppose that terminating resistor Rterm1 is 1k Ω, terminating resistor Rterm2 is 56 Ω, this means difference transmission lines 110 in difference modes with about 100 Ω terminating, in common mode with 28 Ω terminating, so be implemented in the impedance of coupling 100 Ω in the differential mode, and the impedance of in common mode, mating 30 Ω, this paired transmission line to electromagnetic coupled is typical.

When common mode voltage signal when transmitter 160 sends to such transmission line, receiver 170 can receive the average voltage of a signal as differential pair.

The realization of this transmission not with from transmitter 120 to receiver 150 differential signal transmission and from transmitter 130 to receiver 140 differential signal transmission disturb.

The 18 embodiment

Figure 21 is the schematic diagram that shows according to the communication equipment structure of eighteenth embodiment of the invention.

In the communication equipment 100B according to the 18 embodiment, receiver 200 and transmitter 160 be parallel to be arranged on the distolateral of difference transmission lines 110, and transmitter 190 and transmitter 210 be parallel similarly to be connected that another is distolateral.

In communication equipment 100B, also realized the common-mode signal transmission, 210 with simultaneously parallel mutual interference does not mutually take place in 200 two-way communication from transmitter 190 to receiver from transmitter 160 to receiver.

The 19 embodiment

Figure 22 is the schematic diagram that shows according to the communication equipment structure of nineteenth embodiment of the invention.

Be with difference according to the communication equipment 100C of the 19 embodiment according to the communication equipment 100A of the 18 embodiment, in the present embodiment, also be applied to another of difference transmission lines 110 transmitter 120C on distolateral according to the driver 1D of the 6th embodiment or according to the driver 1K of the 13 embodiment.

Have, communication equipment 100C has bias supply 220 rather than transmitter 160 again, difference transmission lines 110 one distolateral through resistor R term2 biasing dc voltage.

The 20 embodiment

Figure 23 is the schematic diagram that shows according to the communication equipment structure of twentieth embodiment of the invention.

Be with difference according to the communication equipment 100D of the 20 embodiment according to the communication equipment 100C of the 19 embodiment, in the present embodiment, also be applied to another of difference transmission lines 110 transmitter 130D on distolateral according to the driver 1D of the 6th embodiment or according to the driver 1K of the 13 embodiment.

Receiver 230 is in parallel with transmitter 120C.

According to the 20 embodiment, transmitted in both directions when can utilize driver 1K according to the driver 1D of the 6th embodiment or the 13 embodiment to realize common-mode signal.

Those skilled in the art it will be appreciated that, can make various corrections, combination, sub-portfolio or replacement according to designing requirement and other factors in the appended claim scope or in the equivalent scope.

Claims (20)

1. differential drive circuit, comprise following system one of at least:

First drive system comprises:

First field-effect transistor of first conduction type,

Second field-effect transistor of first conduction type,

First resistor and second resistor,

First circuit, the source voltage of controlling first field-effect transistor make that it equals to be provided first drive target voltage and

Second circuit, its second driving target voltage that equals to be provided is provided the source voltage of controlling this second field-effect transistor,

The source electrode of first field-effect transistor is connected to the power supply potential source through first resistor, and drain electrode is connected to first output node,

The source electrode of second field-effect transistor is connected to the power supply potential source through second resistor, and drain electrode is connected to second output node; And

Second drive system comprises:

The 3rd field-effect transistor of second conduction type,

The 4th field-effect transistor of second conduction type,

The 3rd resistor and the 4th resistor,

Tertiary circuit, the source voltage of controlling the 3rd field-effect transistor make that it equals to be provided the 3rd drive target voltage and

The 4th circuit, the source voltage of controlling the 4th field-effect transistor makes it that 4 wheel driven moving-target voltage that is provided is provided,

The source electrode of the 3rd field-effect transistor is connected to source of reference potential through the 3rd resistor, and drain electrode is connected to first output node,

The source electrode of the 4th field-effect transistor is connected to source of reference potential through the 4th resistor, and drain electrode is connected to second output node,

Wherein this differential drive circuit drives common-mode voltage is striden load resistance with formation constant difference sub-signal.

2. according to the differential drive circuit of claim 1, wherein:

In first drive system, first drives target voltage and second drives that target voltage forms it and constant differential signal is right; And

In second drive system, the 3rd drives that target voltage and 4 wheel driven moving-target voltage form it and constant differential signal is right.

3. according to the differential drive circuit of claim 2, if wherein this differential drive circuit has first drive system and second drive system,

It is the signal with same waveform as of skew that the first driving target voltage and the 3rd drives target voltage, and

The second driving target voltage and 4 wheel driven moving-target voltage are the signals with same waveform as of skew.

4. according to the differential drive circuit of claim 2, wherein:

In first drive system, first average voltage that drives the target voltage and the second driving target voltage is biased and makes it be lower than steady state value of power supply potential; And

In second drive system, the 3rd average voltage that drives target voltage and 4 wheel driven moving-target voltage is biased and makes it be higher than steady state value of reference potential.

5. according to the differential drive circuit of claim 1, wherein:

First circuit comprises first operational amplifier, and this first operational amplifier has second input of the source electrode that is connected to first first input end that drives the power line of target voltage, is connected to first field-effect transistor and is connected to the output of the grid of first field-effect transistor;

Second circuit comprises second operational amplifier, and this second operational amplifier has the four-input terminal of the source electrode that is connected to second the 3rd input that drives the power line of target voltage, is connected to second field-effect transistor and is connected to the output of the grid of second field-effect transistor;

Tertiary circuit comprises the 3rd operational amplifier, and the 3rd operational amplifier has the 6th input of the source electrode that is connected to the 3rd the 5th input that drives the power line of target voltage, is connected to the 3rd field-effect transistor and is connected to the output of the grid of the 3rd field-effect transistor; And

The 4th circuit comprises four-operational amplifier, this four-operational amplifier have the power line that is connected to 4 wheel driven moving-target voltage the 7th input, be connected to the 4th field-effect transistor source electrode the 8th input and be connected to the output of the grid of the 4th field-effect transistor.

6. according to the differential drive circuit of claim 1, wherein:

First drive system also comprises the 5th resistor, is connected between the source electrode of the source electrode of first field-effect transistor and second field-effect transistor; And

Second drive system also comprises the 6th resistor, is connected between the source electrode of the source electrode of the 3rd field-effect transistor and the 4th field-effect transistor.

7. according to the differential drive circuit of claim 5, wherein:

First drive system also comprises the 5th resistor, is connected between the source electrode of the source electrode of first field-effect transistor and second field-effect transistor; And

Second drive system also comprises the 6th resistor, is connected between the source electrode of the source electrode of the 3rd field-effect transistor and the 4th field-effect transistor.

8. according to the differential drive circuit of claim 1, wherein:

First drive system also comprises digital-to-analog converter DAC, according to the numerical data generation first driving target voltage and the second driving target voltage of input; And

Second drive system also comprises digital-to-analog converter DAC, produces the 3rd according to the numerical data of importing and drives target voltage and the 4th target drives voltage.

9. differential drive circuit according to Claim 8, wherein:

The DAC of first drive system comprises:

The one DAC, from the first added/subtracted result of the numerical data of two inputs produce first drive target voltage and

The 2nd DAC produces second from the second added/subtracted result of the numerical data of two inputs and drives target voltage; And

The DAC of second drive system comprises:

The 3rd DAC, from the third phase of the numerical data of two inputs add/subtract each other the result produce the 3rd drive target voltage and

The 4th DAC produces 4 wheel driven moving-target voltage from the 4th added/subtracted result of the numerical data of two inputs.

10. according to the differential drive circuit of claim 9, wherein:

First drive system also comprises stabilizing circuit, is used for stablizing the output of a DAC and the 2nd DAC; And

Second drive system also comprises stabilizing circuit, is used for stablizing the output of the 3rd DAC and the 4th DAC.

11. differential drive circuit according to Claim 8, wherein:

First drive system also comprises multiplier, this multiplier multiply by the coefficient of appointment with specific input so that make the output of the DAC of first drive system become steady state value with respect to described specific input, and the input after the multiplying is input to the DAC of first drive system; And

Second drive system also comprises multiplier, this multiplier multiply by the coefficient of appointment with specific input so that make the output of the DAC of second drive system become steady state value with respect to described specific input, and the input after the multiplying is input to the DAC of second drive system.

12. according to the differential drive circuit of claim 1, wherein:

First drive system also comprises first differential amplifier, this first differential amplifier receives differential voltage and produces first and drives the target voltage and the second driving target voltage, the first driving target voltage that is produced is offered first circuit, and the second driving target voltage that is produced is offered second circuit;

This second drive system also comprises second differential amplifier, this second differential amplifier receives differential voltage and produces the 3rd and drives target voltage and 4 wheel driven moving-target voltage, the 3rd driving target voltage that is produced is offered tertiary circuit, and the 4 wheel driven moving-target voltage that is produced is offered the 4th circuit.

13. according to the differential drive circuit of claim 12, wherein:

First drive system also comprises the 5th resistor, is connected between the source electrode of the source electrode of this first field-effect transistor and second field-effect transistor; And

Second drive system also comprises the 6th resistor, is connected between the source electrode of the source electrode of the 3rd field-effect transistor and the 4th field-effect transistor.

14. according to the differential drive circuit of claim 12, wherein:

First drive system also comprises the skew adjunct circuit, and this circuit appends to a skew first each that drives in the target voltage and the second driving target voltage that is produced by first differential amplifier; And

Second drive system also comprises the skew adjunct circuit, and this circuit appends to a skew the 3rd each that drives in target voltage and the 4 wheel driven moving-target voltage that is produced by second differential amplifier.

15. according to the differential drive circuit of claim 12, wherein:

First drive system also comprises:

The first resistance adjustment field-effect transistor, in parallel with the load resistance of first differential amplifier and

Regulating circuit, the grid potential of regulating this first resistance adjustment field-effect transistor;

And

Second drive system also comprises:

The second resistance adjustment field-effect transistor, in parallel with the load resistance of second differential amplifier and

Regulating circuit, the grid potential of regulating this second resistance adjustment field-effect transistor.

16. according to the differential drive circuit of claim 5, wherein:

This differential drive circuit is connected with the common mode feedback circuit that absorbs the unnecessary electric current that is provided to load-side.

17. a communication equipment comprises the transmitter on the both end sides that is arranged on difference transmission lines, wherein:

This transmitter comprises differential drive circuit, and this differential drive circuit drives common-mode voltage is striden load resistance with formation constant difference sub-signal; And

This differential drive circuit comprises:

First field-effect transistor of first conduction type,

Second field-effect transistor of first conduction type,

The 3rd field-effect transistor of second conduction type,

The 4th field-effect transistor of second conduction type,

First output node and second output node,

First resistor, second resistor, the 3rd resistor and the 4th resistor,

The source electrode of this first field-effect transistor is connected to power supply potential through first resistor, and drain electrode is connected to first output node,

The source electrode of this second field-effect transistor is connected to power supply potential through this second resistor, and drain electrode is connected to second output node,

The source electrode of the 3rd field-effect transistor is connected to reference potential through the 3rd resistor, and drain electrode is connected to this first output node,

The source electrode of the 4th field-effect transistor is connected to reference potential through the 4th resistor, and drain electrode is connected to this second output node,

First circuit, control this first field-effect transistor source voltage so that its equal to be provided first drive target voltage,

Second circuit, control this second field-effect transistor source voltage so that its equal to be provided second drive target voltage,

Tertiary circuit, control the 3rd field-effect transistor source voltage so that its equal to be provided the 3rd drive target voltage and

The 4th circuit is controlled the source voltage of the 4th field-effect transistor so that the 4 wheel driven moving-target voltage that provided is provided for it.

18. according to the communication equipment of claim 17, wherein this differential drive circuit also comprises:

The 5th resistor is connected between the source electrode of the source electrode of first field-effect transistor and second field-effect transistor; With

The 6th resistor is connected between the source electrode of the source electrode of the 3rd field-effect transistor and the 4th field-effect transistor.

19. the communication equipment according to claim 17 also comprises:

First differential amplifier receives differential voltage and produces the first driving target voltage and the second driving target voltage, the first driving target voltage that is produced is provided to first circuit, and the second driving target voltage that is produced is provided to second circuit; And

Second differential amplifier receives this differential voltage and produces the 3rd driving target voltage and 4 wheel driven moving-target voltage, the 3rd driving target voltage that is produced is provided to tertiary circuit, and the 4 wheel driven moving-target voltage that is produced is provided to the 4th circuit.

20., also comprise with respect to this difference transmission lines and the parallel receiver that is provided with of transmitter according to the communication equipment of claim 17.

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