CN116938222B - Compensation calibration circuit, output driver and electronic equipment - Google Patents
Compensation calibration circuit, output driver and electronic equipment Download PDFInfo
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- CN116938222B CN116938222B CN202311194645.9A CN202311194645A CN116938222B CN 116938222 B CN116938222 B CN 116938222B CN 202311194645 A CN202311194645 A CN 202311194645A CN 116938222 B CN116938222 B CN 116938222B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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Abstract
The application discloses compensation calibration circuit, output driver and electronic equipment, this compensation calibration circuit includes: the first replica bias module is configured to generate a first differential voltage signal in response to a preset first input signal pair and output the first differential voltage signal to the operational amplifier; the second replica bias module is configured to generate a second differential voltage signal in response to a preset second input signal pair and output the second differential voltage signal to the operational amplifier; the operational amplifier is used for obtaining a current regulation signal according to the first differential voltage signal and the second differential voltage signal and outputting the current regulation signal to a main circuit of the output driver; the first differential voltage signal is the same as the second differential voltage signal. In the method, the first differential voltage signal is equal to the second differential voltage signal, and the current adjusting signal output to the main circuit by the operational amplifier can adjust the output linearity of the main circuit, so that the current proportion of two current branches of the main circuit meets the requirement, and the reliability of the output driver is ensured.
Description
Technical Field
The application relates to the technical field of communication, in particular to a compensation calibration circuit, an output driver and electronic equipment.
Background
The Current mode logic type output driver (Current-Model Logic type output driver, CML-type output driver) is a circuit structure commonly used for high-speed four-level pulse amplitude modulation transmitters (4-Level Pulse Amplitude Modulation Transmitter, PAM4 TX).
With the advanced technology adopting a lower supply voltage, the CML TX Driver is difficult to achieve higher output signal linearity under the condition of outputting high swing PAM4 voltage, and in order to solve this problem, a register is used in the related art to adjust the output signal linearity.
However, the use of registers to adjust the linearity of the output signal can result in relatively large differences in performance of the CML TX Driver when the process corner, voltage, and temperature (Process, voltage, temperature corners, PVT filters) of the transistors change, which can also result in poor linearity of the output signal.
Disclosure of Invention
In view of the above, the present application provides a compensation calibration circuit, an output driver and an electronic device, so as to solve the above technical problems.
In a first aspect, the present application provides a compensation calibration circuit, including an operational amplifier, and a first replica bias module and a second replica bias module respectively connected to the operational amplifier; the first copying bias module and the second copying bias module are copying circuits of a main circuit of the output driver;
A first replica bias module configured to generate a first differential voltage signal output to the operational amplifier in response to a preset first input signal pair;
a second replica bias module configured to generate a second differential voltage signal output to the operational amplifier in response to a preset second input signal pair;
the operational amplifier is used for obtaining a current adjusting signal according to the first differential voltage signal and the second differential voltage signal and outputting the current adjusting signal to a main circuit of the output driver so as to adjust the output linearity of the main circuit;
the preset first input signal pair is different from the preset second input signal pair, and the first differential voltage signal is the same as the second differential voltage signal.
In one possible implementation manner of the present application, the output end of the operational amplifier is further connected to the first replication bias module and the second replication bias module, respectively, and is configured to output a current adjustment signal to the first replication bias module and the second replication bias module, so as to adjust a current ratio of two current branches in the first replication bias module and a current ratio of two current branches in the second replication bias module.
In one possible implementation of the present application, the first replica bias module includes a first high-order current branch, a first low-order current branch, and a first resistor circuit; one end of the first resistor circuit is connected with the first high-order current branch, and the other end of the first resistor circuit is connected with the first low-order current branch;
The first high-order current branch is used for receiving a high-order signal in a preset first input signal pair and generating a first high-order current;
the first low-level current branch is used for receiving a low-level signal in a preset first input signal pair and generating a first low-level current;
the first resistor circuit is used for generating a first differential voltage signal according to the first high-order current and the first low-order current and outputting the first differential voltage signal to the operational amplifier.
In one possible implementation manner of the present application, the first high-order current branch includes a first load resistor, the first low-order current branch includes a second load resistor, the first resistor circuit includes a first termination resistor branch connected with the first load resistor and a second termination resistor branch connected with the second load resistor, and the first termination resistor branch is connected with the second termination resistor branch;
the resistance of the first load resistor, the resistance of the second load resistor, the total resistance of the first termination resistor branch and the total resistance of the second termination resistor branch are equal.
In one possible implementation manner of the present application, the first termination resistor branch includes a first resistor, a second resistor and a third resistor connected in series, the second termination resistor branch includes a fourth resistor, a fifth resistor and a sixth resistor connected in series, the first resistor is connected with a first load resistor, the sixth resistor is connected with a second load resistor, and the third resistor is connected with the fourth resistor;
The first connecting node of the second resistor and the third resistor is connected with the first non-inverting input end of the operational amplifier, and the second connecting node of the fourth resistor and the fifth resistor is connected with the first inverting input end of the operational amplifier.
In one possible implementation of the present application, the second replica bias module includes a second high-order current branch, a second low-order current branch, and a second resistor circuit; one end of the second resistor circuit is connected with the second high-order current branch, and the other end of the second resistor circuit is connected with the second low-order current branch;
the second high-order current branch is used for receiving a high-order signal in a preset second input signal pair and generating a second high-order current;
the second low-level current branch is used for receiving a low-level signal in a preset second input signal pair and generating a second low-level current;
the second resistor circuit is used for generating a second differential voltage signal according to a second high-order current and a second low-order current and outputting the second differential voltage signal to the operational amplifier.
In one possible implementation manner of the present application, the second high-level current branch includes a third load resistor, the second low-level current branch includes a fourth load resistor, the second resistor circuit includes a third terminal resistor branch connected to the third load resistor and a fourth terminal resistor branch connected to the fourth load resistor, and the third terminal resistor branch is connected to the fourth terminal resistor branch;
The resistance of the third load resistor, the resistance of the fourth load resistor, the total resistance of the third terminal resistor branch and the total resistance of the fourth terminal resistor branch are equal.
In one possible implementation manner of the present application, the third terminal resistor branch includes a seventh resistor, an eighth resistor and a ninth resistor connected in series, the fourth terminal resistor branch includes a tenth resistor, an eleventh resistor and a twelfth resistor connected in series, the seventh resistor is connected with a third load resistor, the twelfth resistor is connected with a fourth load resistor, and the ninth resistor is connected with the tenth resistor;
the third connecting node of the seventh resistor and the third load resistor is connected with the second non-inverting input end of the operational amplifier, and the fourth connecting node of the twelfth resistor and the fourth load resistor is connected with the second inverting input end of the operational amplifier.
In a second aspect, the present application further provides an output driver comprising the compensation calibration circuit described above.
In a third aspect, the present application further provides an electronic device, including a device body and the above-mentioned output driver or compensation calibration circuit provided in the device body.
According to the compensation calibration circuit, the first replication bias module and the second replication bias module are formed by replicating the main circuit of the output driver, the first replication bias module responds to the preset first input signal pair to generate the first differential voltage signal and output the first differential voltage signal to the operational amplifier, the second replication bias module responds to the preset second input signal pair to generate the second differential voltage signal and output the second differential voltage signal to the operational amplifier, the operational amplifier generates the current regulation signal according to the first differential voltage signal and the second differential voltage signal and outputs the current regulation signal to the main circuit of the output driver, and the first differential voltage signal is equal to the second differential voltage signal, so that the current regulation signal output by the operational amplifier to the main circuit can regulate the output linearity of the main circuit, the problem that the output signal linearity is poor when PVT (PVT) curers of transistors change in the mode of regulating the output signal linearity by adopting registers is avoided, the reliability of the output driver is improved.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a standard three-eye diagram of an output signal;
fig. 2 is a three-eye diagram of an output signal of a transmitter in the related art;
FIG. 3 is a block diagram of a compensation calibration circuit provided in an embodiment of the present application;
FIG. 4 is another block diagram of the compensation calibration circuit provided in an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a main circuit provided in an embodiment of the present application;
FIG. 6 is a schematic circuit diagram of a first replica bias module provided in an embodiment of the present application;
FIG. 7 is a schematic circuit diagram of a second replica bias module provided in an embodiment of the present application;
FIG. 8 is a schematic circuit diagram of a compensation calibration circuit provided in an embodiment of the present application;
FIG. 9 is a block diagram of an output driver provided in an embodiment of the present application;
fig. 10 is a schematic circuit diagram of an output driver according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In order to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the embodiment of the present application with reference to the accompanying drawings in the embodiment of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of embodiments of the present application, words such as "example" or "such as" are used to indicate exemplary, illustrative, or descriptive matter. Any embodiment or design described herein as "example" or "such as" is not necessarily to be construed as preferred or advantageous over another embodiment or design. The use of words such as "example" or "such as" is intended to present relative concepts in a clear manner.
In addition, the term "plurality" in the embodiments of the present application means two or more, and in view of this, the term "plurality" may be understood as "at least two" in the embodiments of the present application. "at least one" may be understood as one or more, for example as one, two or more. For example, including at least one means including one, two or more, and not limiting what is included, e.g., including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C, may be included.
It should be noted that in the embodiments of the present application, "connected" is understood to mean electrically connected, and two electrical components may be connected directly or indirectly between two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.
The first pole/first terminal of each transistor used in the embodiments herein is one of a source and a drain, and the second pole/second terminal of each transistor is the other of the source and the drain. Since the source and drain of a transistor may be symmetrical in structure, the source and drain may be indistinguishable in structure, that is, the first pole/first terminal and the second pole/second terminal of the transistor in embodiments of the present application may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole/first terminal of the transistor is the source and the second pole/second terminal is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole/first terminal of the transistor is the drain and the second pole/second terminal is the source.
In the circuit structure provided in the embodiments of the present application, the first node, the second node, and the like are not nodes representing actually existing components, but represent junction points of related coupling in the circuit diagram, that is, the nodes are equivalent nodes formed by the junction points of the related coupling in the circuit diagram.
Before describing the compensation calibration circuit, the output driver and the electronic device of the present application, the relevant background information of the embodiments of the present application is first described.
The Current mode logic type output driver (Current-Model Logic type output driver, CML-type output driver) is a circuit structure commonly used for high-speed four-level pulse amplitude modulation transmitters (4-Level Pulse Amplitude Modulation Transmitter, PAM4 TX).
In one protocol set forth by the institute of electrical and electronics engineers, the linearity RLM of the output signal of the Transmitter (Transmitter) should be greater than or equal to 0.95, as shown in fig. 1, and in a three-eye diagram of the output signal under such a requirement, the eye heights of each eye should be approximately equal, and the linearity RLM may be expressed as:
wherein,、/>、/>，/>、/>、/>and +.>Four signal levels corresponding to PAM4 respectively.
However, with the advanced technology adopting a lower supply voltage, the CML TX Driver is difficult to achieve higher output signal linearity under the condition of outputting high swing PAM4 voltage, and because RLM of the CML TX Driver is generally limited by distortion caused by the tail current source entering the linear region (triode region) or is a mismatch of current between the upper MSB and the lower LSB, in practical application, the CML PAM4 Driver can only obtain limited output signal linearity RLM, and cannot meet the protocol index (> =0.95). As shown in fig. 2, a PAM4 eye pattern with RLM < 0.95.
To solve this problem, a register is used in the related art to adjust the linearity of an output signal. However, when the process corner, voltage and temperature PVT filters of the transistors change, the performance difference of the CML TX Driver may be relatively large, which may also result in poor linearity of the output signal.
Based on this, the embodiment of the application provides a compensation calibration circuit, an output driver and an electronic device, which are respectively described in detail below.
Referring to fig. 3, fig. 3 is a schematic block diagram of a compensation calibration circuit provided in an embodiment of the present application, where the compensation calibration circuit 100 may include an operational amplifier 110, and a first replica bias module 120 and a second replica bias module 130 respectively connected to the operational amplifier 110; the first replica bias module 120 and the second replica bias module 130 are replica circuits of the main circuit 210 of the output driver 200.
Wherein the first replica bias module 120 may be configured to generate a first differential voltage signal output to the operational amplifier 110 in response to a preset first input signal pair. The second replica bias module 130 may be configured to generate a second differential voltage signal output to the operational amplifier 110 in response to a preset second input signal pair. The operational amplifier 110 may be configured to obtain a current adjustment signal according to the first differential voltage signal and the second differential voltage signal, and output the current adjustment signal to the main circuit 210 of the output driver, so as to adjust output linearity of the main circuit 210; the preset first input signal pair is different from the preset second input signal pair, and the first differential voltage signal is the same as the second differential voltage signal.
In the embodiment of the present application, the first replica bias module 120 and the second replica bias module 130 are replica circuits of the main circuit 210 of the output driver 200, and therefore, it can be known that the circuit structures of the first replica bias module 120 and the second replica bias module 130 are the same as the main circuit 210.
In some examples, the first replication bias module 120 and the second replication bias module 130 may replicate the main circuit 210 based on the same ratio, and it is understood that the ratio referred to herein refers to the ratio of the respective resistors and other parameters of the devices on the main circuit 210, and that the replication of the main circuit 210 based on the same ratio refers to the first replication bias module 120 and the second replication bias module 130 replicating the parameters such as the resistance value, the transistor area, etc. of the main circuit 210 according to the same ratio, for example, the first replication bias module 120 and the second replication bias module replicate the main circuit 210 based on a 5-fold ratio relationship.
In other examples, the first replication bias module 120 and the second replication bias module 130 may replicate the main circuit 210 based on different ratios, that is, the first replication bias module 120 and the second replication bias module 130 replicate the parameters such as the resistance value, the transistor area, etc. of the main circuit 210 according to different ratios, for example, the first replication bias module 120 replicates the main circuit 210 based on a 3-fold ratio, and the second replication bias module replicates the main circuit 210 based on a 2-fold ratio.
It will be appreciated that the same proportions, different proportions and specific proportions may be determined according to the actual application scenario, and are not limited herein.
In this embodiment, the first replica bias module 120 may be connected to an output end (not shown in the figure) of a preset first input signal pair, so that when the preset first input signal pair output by the output end is received, a first differential voltage signal may be generated in response to the preset first input signal pair and output to the operational amplifier 110.
Similarly, the second replica bias module 130 may be connected to an output end of a preset second input signal pair, so that when the preset second input signal pair output by the output end is received, a second differential voltage signal is generated in response to the preset second input signal pair and output to the operational amplifier 110, where the preset second input signal pair in the embodiment of the present application is a signal different from the preset first input signal pair, and the second differential voltage signal is the same signal as the first differential voltage signal.
For example, the first input signal pair is preset to be (1, 1), and the second input signal pair is preset to be (1, 0); presetting the first input signal pair as (0, 0), and presetting the second input signal pair as (0, 1); the first differential voltage signal (V1-V2) is equal to the second differential voltage signal (V3-V4).
Since the first differential voltage signal and the second differential voltage signal received by the operational amplifier 110 are the same, the current adjustment signal output by the operational amplifier 110 to the main circuit 210 can adjust the output linearity of the main circuit 210.
In this embodiment, the first replica bias module 120 and the second replica bias module 130 are formed by replicating the main circuit 210 of the output driver 200, the first replica bias module 120 generates the first differential voltage signal in response to the preset first input signal pair and outputs the first differential voltage signal to the operational amplifier 110, the second replica bias module 130 generates the second differential voltage signal in response to the preset second input signal pair and outputs the second differential voltage signal to the operational amplifier 110, and the operational amplifier 110 generates the current adjusting signal according to the first differential voltage signal and the second differential voltage signal and outputs the current adjusting signal to the main circuit 210 of the output driver 200.
Next, a detailed description of the modules shown in fig. 3 and the specific embodiments that may be employed in the practical application will be continued.
Referring to fig. 4, in some embodiments of the present application, the output end of the operational amplifier 110 may be further connected to the first replication bias module 120 and the second replication bias module 130, respectively, for outputting a current adjustment signal to the first replication bias module 120 and the second replication bias module 130, so as to adjust the current ratio of the two current branches in the first replication bias module 120 and the current ratio of the two current branches in the second replication bias module 130, so that the first differential voltage signal and the second differential voltage signal input to the operational amplifier 110 meet the requirement of equal ratio.
As shown in fig. 5, which is a schematic circuit structure of the main circuit provided in the embodiment of the present application, the main circuit 210 may include two current branches, and a terminating resistor branch connected between the two current branches, one of the two current branches may include a first main circuit load resistor ZRL1, a first main circuit transistor M1, a second main circuit transistor M2, and a first bias current source vbias_msb_i1, and the other of the two current branches may include a second main circuit load resistor ZRL2, a third main circuit transistor M3, a fourth main circuit transistor M4, and a second bias current source vbias_lsb_i2, and the terminating resistor branch may include a first main circuit terminating resistor RT1 and a second main circuit terminating resistor RT2 connected in series.
The resistances of the first main circuit load resistor ZRL1 and the second main circuit load resistor ZRL2 are equal, and the resistances of the first main circuit termination resistor RT1 and the second main circuit termination resistor RT2 are equal. The first main circuit transistor M1, the second main circuit transistor M2, the third main circuit transistor M3 and the fourth main circuit transistor M4 are all NMOS transistors, i.e., N-channel Metal-Oxide-semiconductor field effect transistors (MOSFETs), and it is understood that in other examples, the first main circuit transistor M1, the second main circuit transistor M2, the third main circuit transistor M3 and the fourth main circuit transistor M4 may be P-channel Metal-Oxide-semiconductor field effect transistors (MOSFETs), i.e., PMOS transistors, triodes, insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), etc., which are all controllable switching devices, and may be specifically determined according to practical application scenarios, and are not limited herein.
Specifically, the first end of the first main circuit load resistor ZRL1 and the first end of the second main circuit load resistor ZRL2 are respectively connected with the power supply terminal Vdd, the second end of the first main circuit load resistor ZRL1, the first end of the first main circuit terminating resistor RT1, the drain of the first main circuit transistor M1 and the drain of the third main circuit transistor M3 are interconnected, the second end of the second main circuit load resistor ZRL2, the second end of the second main circuit terminating resistor RT2, the drain of the second main circuit transistor M2 and the drain of the fourth main circuit transistor M4 are interconnected, the source of the first main circuit transistor M1 and the source of the second main circuit transistor M2 are connected with the first bias current source vbias_lj1 which is grounded, the source of the third main circuit transistor M3 and the source of the fourth main circuit transistor M4 are connected with the second bias current source vbias_l2 which is grounded, the gate of the first main circuit transistor M1 is connected with the first high-level signal output terminal msp for receiving the signal of the first high-level signal and the second low-level signal output terminal msp for receiving the signal of the second main circuit lsp, and the second main circuit output gate for receiving the signal of the second high-level signal output msp signal.
Since the first replica bias module 120 and the second replica bias module 130 are the replica circuits of the main circuit 210, two currents and terminating resistor branches exist in the first replica bias module 120 and the second replica bias module 130, and when the operational amplifier 110 outputs a current adjustment signal to adjust the output linearity of the main circuit 210, the current adjustment signal is also input to the first replica bias module 120 and the second replica bias module 130, respectively, so that the linearity of the first differential voltage signal and the second differential voltage signal can be adjusted as well, and the proportion of the first differential voltage signal and the second differential voltage signal is ensured to be equal.
As shown in fig. 6, in some embodiments of the present application, the first replica bias module 120 may include a first high-order current branch, a first low-order current branch, and a first resistor circuit; one end of the first resistor circuit is connected with the first high-order current branch, and the other end of the first resistor circuit is connected with the first low-order current branch; the first high-order current branch is used for receiving a high-order signal in a preset first input signal pair and generating a first high-order current; the first low-level current branch is used for receiving a low-level signal in a preset first input signal pair and generating a first low-level current; the first resistor circuit is used for generating a first differential voltage signal according to the first high-order current and the first low-order current and outputting the first differential voltage signal to the operational amplifier 110.
Specifically, the first high-order current branch includes a first load resistor RL1, a first transistor N1, a second transistor N2, and a first current source I MSB_1 The first low-order current branch comprises a second load resistor RL2, a third transistor N3, a fourth transistor N4 and a second current source I LSB_2 The first resistor circuit may include a first terminating resistor branch connected to the first load resistor RL1 and a second terminating resistor branch connected to the second load resistor RL2, and the first terminating resistor branch is connected to the second terminating resistor branch; and the resistance of the first load resistor RL1, the resistance of the second load resistor RL2, the total resistance of the first termination resistor branch and the total resistance of the second termination resistor branch are equal.
Specifically, referring to fig. 6, the first termination resistor branch may include a first resistor R1, a second resistor R2, and a third resistor R3 connected in series, the second termination resistor branch includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series, the first resistor R1 is connected to the first load resistor RL1, the sixth resistor R6 is connected to the second load resistor RL2, and the third resistor R3 is connected to the fourth resistor R4;
the first connection node of the second resistor R2 and the third resistor R3 is connected to the first non-inverting input terminal of the operational amplifier 110, and is used for outputting a positive phase signal v11_div_n of the first differential voltage signal, and the second connection node of the fourth resistor R4 and the fifth resistor R5 is connected to the first inverting input terminal of the operational amplifier 110, and is used for outputting an inverting signal v11_div_p of the first differential voltage signal. The fifth connection node of the first load resistor RL1 and the first resistor R1 is also connected with the drain of the first transistor N1 and the drain of the third transistor N3, the source of the first transistor N1 and the source of the second transistor N2 are connected with a grounded first current source I MSB_1 Connecting; the sixth connection node of the second load resistor RL2 and the sixth resistor R6 is also connected with the drain of the second transistor N2 and the drain of the fourth transistor N4, the source of the third transistor N3 and the source of the fourth transistor N4 are connected with a second current source I grounded LSB_2 And (5) connection.
The gate of the first transistor N1 is connected to a first output terminal of a high-level signal in a preset first input signal pair, and is configured to receive the first signal in the high-level signal, such as a high-level signal "1" shown in fig. 6; the gate of the second transistor N2 is connected to the second output terminal of the high-order signal in the preset first input signal pair, and is used for receiving the second signal in the high-order signal, such as the low-level signal "0" shown in fig. 6; the gate of the third transistor N3 is connected to the first output terminal of the low-level signal in the preset first input signal pair, and is configured to receive the first signal in the low-level signal, such as the high-level signal "1" shown in fig. 6; the gate of the fourth transistor N4 is connected to the second output terminal of the low-level signal in the preset first input signal pair, and is used for receiving the second signal in the low-level signal, such as the low-level signal "0" shown in fig. 6.
In this embodiment, the first transistor N1, the second transistor N2, the third transistor N3, and the fourth transistor N4 may be NMOS transistors, or may be any existing controllable switching device such as PMOS transistors, triodes, insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), etc., which may be specifically determined according to an actual application scenario, and are not limited herein.
As can be seen from fig. 6, assuming that the first input signal pair is preset to be (MSB, LSB) = (1, 1), assuming that r1+r2+r3=r4+r5+r6=rl 1=rl 2, the voltage relationship among the second connection node, the first connection node, the sixth connection node, and the fifth connection node can be expressed as:
V11_DIV_P-V11_DIV_N=1/3*(V11_P-V11_N)
the output of the operational amplifier 110 shown in FIG. 6 is coupled to a second current source I LSB_2 Is connected so that the current regulation signal can regulate the second current source I LSB_2 The current on the first low-order current branch is adjusted, so that the current proportion of the first high-order current branch and the first low-order current branch in the first replica bias module 120 is adjusted, that is, the linearity of the first differential voltage signal output by the first replica bias module 120 is adjusted.
It will be appreciated that in other examples, the output of the operational amplifier 110 may also be coupled to the first current source I MSB_1 Connected to regulate the first current source I by means of a current regulation signal MSB_1 The current on the first high-order current branch is located, so that the current proportion of the first high-order current branch and the first low-order current branch in the first replica bias module 120 is adjusted, namely the linearity of the first differential voltage signal output by the first replica bias module 120 is adjusted.
As shown in fig. 7, the second replica bias module 130 may include a second high-order current branch, a second low-order current branch, and a second resistor circuit; one end of the second resistor circuit is connected with the second high-order current branch, and the other end of the second resistor circuit is connected with the second low-order current branch; the second high-order current branch is used for receiving a high-order signal in a preset second input signal pair and generating a second high-order current; the second low-level current branch is used for receiving a low-level signal in a preset second input signal pair and generating a second low-level current; the second resistor circuit is used for generating a second differential voltage signal according to the second high-order current and the second low-order current and outputting the second differential voltage signal to the operational amplifier 110.
Specifically, the second high-order current branch includes a third load resistor RL3, a fifth transistor N5, a sixth transistor N6, and a third current source I MSB_3 The second low-order current branch comprises a fourth load resistor RL4, a seventh transistor N7, an eighth transistor N8 and a fourth current source I LSB_4 The second resistor circuit may include a third terminal resistor branch connected to the third load resistor RL3 and a fourth terminal resistor branch connected to the fourth load resistor RL4, where the third terminal resistor branch is connected to the fourth terminal resistor branch; the resistance of the third load resistor RL3, the resistance of the fourth load resistor RL4, the total resistance of the third terminal resistor branch and the total resistance of the fourth terminal resistor branch are equal.
Specifically, with continued reference to fig. 7, the third terminal resistor branch may include a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9 connected in series, the fourth terminal resistor branch includes a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12 connected in series, the seventh resistor R7 is connected to the third load resistor RL3, the twelfth resistor R12 is connected to the fourth load resistor RL4, and the ninth resistor R9 is connected to the tenth resistor R10;
the seventh resistor R7 is connected to the third connection node of the third load resistor RL3 and the second non-inverting input terminal of the operational amplifier 110, and is used for outputting the positive phase signal v10_n of the second differential voltage signal, and the twelfth resistor R12 is connected to the fourth connection node of the fourth load resistor RL4 and the second inverting input terminal of the operational amplifier 110, and is used for outputting the inverting signal v10_p of the second differential voltage signal.
The third connection node of the third load resistor RL3 and the seventh resistor R7 is also connected to the drain of the fifth transistor N5 and the drain of the seventh transistor N7, and the source of the fifth transistor N5 and the source of the sixth transistor N6 are connected to a third current source I connected to ground MSB_3 Connecting; the fourth connection node of the fourth load resistor RL4 and the twelfth resistor R12 is also connected to the drain of the sixth transistor N6 and the drain of the eighth transistor N8, the source of the seventh transistor N7 and the source of the eighth transistor N8 are connected to a fourth current source I connected to ground LSB_4 And (5) connection.
The gate of the fifth transistor N5 is connected to the first output terminal of the high-level signal in the preset second input signal pair, and is configured to receive the first signal in the high-level signal, such as the high-level signal "1" shown in fig. 7; the gate of the sixth transistor N6 is connected to the second output terminal of the high-level signal in the preset second input signal pair, and is configured to receive the second signal in the high-level signal, such as the low-level signal "0" shown in fig. 7; the gate of the seventh transistor N7 is connected to the first output terminal of the low-level signal in the preset second input signal pair, for receiving the first signal of the low-level signal, such as the low-level signal "0" shown in fig. 7; the gate of the eighth transistor N8 is connected to the second output terminal of the low-level signal in the preset second input signal pair, for receiving the second signal in the low-level signal, such as the high-level signal "1" shown in fig. 7.
In this embodiment, the fifth transistor N5, the sixth transistor N6, the seventh transistor N7, and the eighth transistor N8 may be NMOS transistors, or may be any existing controllable switching device such as PMOS transistors, triodes, insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), etc., which may be specifically determined according to practical application scenarios, and are not limited herein.
As can be seen from fig. 7, the second input signal pair is preset to be (MSB, LSB) = (1, 0). The output of the operational amplifier 110 and the fourth current source I shown in FIG. 7 LSB_4 Is connected so that the current regulation signal can regulate the fourth current source I LSB_4 The current magnitude on the second low-order current branch is adjusted, so that the current proportion of the second high-order current branch and the second low-order current branch in the second replica bias module 130 is adjusted, that is, the linearity of the second differential voltage signal output by the second replica bias module 130 is adjusted.
It will be appreciated that in other examples, the output of the operational amplifier 110 may also be coupled to a third current source I MSB_3 Connected to regulate the third current source I by means of a current regulation signal MSB_3 The magnitude of the current on the second higher current branch in which the second replica bias module 130 is located is thereby adjustedThe current ratio of the second low-order current branch and the second low-order current branch adjusts the linearity of the second differential voltage signal output by the second replica bias module 130.
Referring to fig. 6 and fig. 7, as shown in fig. 8, a schematic circuit structure of the compensation calibration circuit provided in the embodiment of the application is shown. In this embodiment of the present application, the preset first input signal pair may be (MSB, LSB) = (1, 1), and the preset second input signal pair may be (MSB, LSB) = (1, 0), which may be understood that in other examples, the preset first input signal pair may also be (MSB, LSB) = (0, 0), and the preset second input signal pair may also be (MSB, LSB) = (0, 1), which may be specifically selected according to an actual application scenario, and this is not limited herein.
The present embodiment is described taking the example of presetting the first input signal pair to be (MSB, LSB) = (1, 1) and presetting the second input signal pair to be (MSB, LSB) = (1, 0).
Since RL 1=rl 2=rl 3=rl 4=rl, there is r1+r2+r3=r4+r5+r6=rl, r7+r8+r9=r10+r11+r12=rl.
As can be seen from fig. 8, the first differential voltage signal (v11_div_p-v11_div_n) is equal to the second differential voltage signal (v10_p-v10_n), and thus, the operational amplifier 110 can ensure linearity of the PAM4 signal output by the output driver after outputting the current adjustment signal generated based on the first differential voltage signal (v11_div_p-v11_div_n) and the second differential voltage signal (v10_p-v10_n) to the main circuit 210.
In the present embodiment, the current adjustment signals outputted from the operational amplifier 110 are respectively applied to the two replica bias modules and the second current source I, which is the low-order current source of the main circuit 210 LSB_2 Fourth current source I LSB_4 And the second bias current source vbias_lsb_i2 performs current adjustment, so that v11_div_p-v11_div_n=1/3 (v11_p-v11_n) =v10_p-v10_n of the two circuit branches in the two replica bias modules and the main circuit 210, thereby improving linearity of the PAM4 signal output by the main circuit 210.
It should be noted that in other embodiments, the output of the operational amplifier 110 may be connected to the two replica bias modules and the high-order current source of the main circuit 210, i.e. the first current source I MSB_1 Third current source I MSB_3 And the first bias current source vbias_msb_i1 is connected, so that the output current adjusting signal can respectively perform current adjustment on the two replica bias modules and the high-order current source of the main circuit 210, so that the voltages of the two replica bias modules and the respective two current branches in the main circuit 210 meet the preset proportion, thereby improving the linearity of the output signal of the main circuit 210.
As shown in fig. 9, on the basis of the above embodiment, the present embodiment also provides an output driver 200, which may include a main circuit 210 and the compensation calibration circuit 100 as in any of the embodiments of fig. 3 to 8.
The output driver 200 may be, but is not limited to, a CML-type TX driver, a mixed-architecture TX driver, etc., where the mixed-architecture TX driver includes, but is not limited to, a source series termination and a current-mode logic type mixed-output driver (SST+ CML hybrid driver).
Referring to fig. 10, fig. 10 is a schematic circuit diagram of an output driver provided in this embodiment, in the circuit of the output driver 200, the resistance values of the first load resistor RL1, the second load circuit RL2, the third load circuit RL3, the fourth load resistor RL4, the first main circuit load circuit ZRL1 and the second main circuit load resistor ZRL2 are equal, the resistance values of the first main circuit terminating resistor RT1 and the second main circuit terminating resistor RT2 are equal, the sum of the resistance values of the first resistor R1, the second resistor R2 and the third resistor R3, the sum of the resistance values of the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6, the sum of the resistance values of the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9, and the sum of the resistance values of the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 are equal to the first load resistor RL 1.
First bias current source vbias_msb_i1, first current source I MSB_1 Third current source I MSB_3 All controlled by the high bias voltage signal Vbias_MSB to generate branch current, the second bias current source Vbias_LSB_I2 and the second current source I LSB_2 Fourth current source I LSB_4 All controlled by the current regulation signal Vbias_LSB_replica to generate the branch current, so thatThe voltages of the two replica bias modules and the two current branches in the main circuit 210 meet a preset ratio, so that the linearity of the PAM4 signal output by the output driver is improved.
The output driver 200 is provided with the compensation calibration circuit 100 according to the above embodiment, so that all the advantages of the compensation calibration circuit 100 according to any of the above embodiments are achieved, and will not be described herein.
The embodiment of the application also provides an electronic device, which may include a device body and the output driver 200 or the compensation calibration circuit 100 provided in the device body.
The electronic device is provided with the compensation calibration circuit 100 of the above embodiment, so that the electronic device has all the advantages of the compensation calibration circuit 100 of any one of the above embodiments, and will not be described herein.
The foregoing description is not intended to limit the preferred embodiments of the present application, but is not intended to limit the scope of the present application, and any such modifications, equivalents and adaptations of the embodiments described above in accordance with the principles of the present application should and are intended to be within the scope of the present application, as long as they do not depart from the scope of the present application.
Claims (8)
1. A compensation calibration circuit is applied to an output driver of a current mode logic type, and is characterized by comprising an operational amplifier, a first replication bias module and a second replication bias module, wherein the first replication bias module and the second replication bias module are respectively connected with the operational amplifier; the first replication bias module and the second replication bias module are replication circuits of a main circuit of the output driver;
the first replica bias module is configured to generate a first differential voltage signal to be output to the operational amplifier in response to a preset first input signal pair;
the second replica bias module is configured to generate a second differential voltage signal to be output to the operational amplifier in response to a preset second input signal pair;
the operational amplifier is used for obtaining a current adjusting signal according to the first differential voltage signal and the second differential voltage signal and outputting the current adjusting signal to a main circuit of the output driver so as to adjust the output linearity of the main circuit;
wherein the preset first input signal pair is different from the preset second input signal pair, and the first differential voltage signal is the same as the second differential voltage signal;
the first replication bias module comprises a first high-order current branch, a first low-order current branch and a first resistor circuit, wherein the first high-order current branch comprises a first load resistor, the first low-order current branch comprises a second load resistor, and the first resistor circuit comprises a first terminal resistor branch and a second terminal resistor branch;
The first termination resistor branch comprises a first resistor, a second resistor and a third resistor which are connected in series, the second termination resistor branch comprises a fourth resistor, a fifth resistor and a sixth resistor which are connected in series, the first resistor is connected with the first load resistor, the sixth resistor is connected with the second load resistor, and the third resistor is connected with the fourth resistor;
the first connecting node of the second resistor and the third resistor is connected with the first non-inverting input end of the operational amplifier, the second connecting node of the fourth resistor and the fifth resistor is connected with the first inverting input end of the operational amplifier, and the first differential voltage signal is a voltage difference signal between the second connecting node and the first connecting node;
the second replication bias module comprises a second high-order current branch, a second low-order current branch and a second resistance circuit, wherein the second high-order current branch comprises a third load resistor, the second low-order current branch comprises a fourth load resistor, and the second resistance circuit comprises a third terminal resistance branch and a fourth terminal resistance branch;
the third terminal resistor branch comprises a seventh resistor, an eighth resistor and a ninth resistor which are connected in series, the fourth terminal resistor branch comprises a tenth resistor, an eleventh resistor and a twelfth resistor which are connected in series, the seventh resistor is connected with the third load resistor, the twelfth resistor is connected with the fourth load resistor, and the ninth resistor is connected with the tenth resistor;
The third connecting node of the seventh resistor and the third load resistor is connected with the second non-inverting input end of the operational amplifier, the fourth connecting node of the twelfth resistor and the fourth load resistor is connected with the second inverting input end of the operational amplifier, and the second differential voltage signal is a voltage difference signal between the fourth connecting node and the third connecting node.
2. The compensation calibration circuit of claim 1, wherein the output of the operational amplifier is further coupled to the first replica bias block and the second replica bias block, respectively, for outputting the current adjustment signal to the first replica bias block and the second replica bias block to adjust the current ratio of the two current branches in the first replica bias block and the current ratio of the two current branches in the second replica bias block.
3. The compensation calibration circuit of claim 1, wherein one end of the first resistor circuit is connected to the first high-side current branch and the other end is connected to the first low-side current branch;
the first high-order current branch is used for receiving high-order signals in the preset first input signal pair and generating first high-order current;
The first low-level current branch is used for receiving low-level signals in the preset first input signal pair and generating first low-level current;
the first resistor circuit is used for generating the first differential voltage signal according to the first high-order current and the first low-order current and outputting the first differential voltage signal to the operational amplifier.
4. A compensation calibration circuit according to claim 3, wherein the first load resistor is connected to the first termination resistor branch, the second load resistor is connected to the second termination resistor branch, and the first termination resistor branch is connected to the second termination resistor branch;
the resistance of the first load resistor, the resistance of the second load resistor, the total resistance of the first termination resistor branch and the total resistance of the second termination resistor branch are equal.
5. The compensation calibration circuit of claim 1, wherein one end of the second resistor circuit is connected to the second high-side current branch and the other end is connected to the second low-side current branch;
the second high-order current branch is used for receiving the high-order signals in the preset second input signal pair and generating second high-order current;
The second low-level current branch is used for receiving low-level signals in the preset second input signal pair and generating second low-level current;
the second resistor circuit is used for generating the second differential voltage signal according to the second high-order current and the second low-order current and outputting the second differential voltage signal to the operational amplifier.
6. The compensation calibration circuit of claim 5, wherein the third load resistor is connected to the third terminal resistor branch, the fourth load resistor is connected to the fourth terminal resistor branch, and the third terminal resistor branch is connected to the fourth terminal resistor branch;
the resistance of the third load resistor, the resistance of the fourth load resistor, the total resistance of the third terminal resistor branch and the total resistance of the fourth terminal resistor branch are equal.
7. An output driver comprising a compensation calibration circuit according to any one of claims 1-6.
8. An electronic device comprising a device body and the output driver of claim 7 or the compensation calibration circuit of any one of claims 1-6 provided to the device body.
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