CN112398466A - Low-voltage high-speed driving circuit - Google Patents
Low-voltage high-speed driving circuit Download PDFInfo
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- CN112398466A CN112398466A CN201910751280.2A CN201910751280A CN112398466A CN 112398466 A CN112398466 A CN 112398466A CN 201910751280 A CN201910751280 A CN 201910751280A CN 112398466 A CN112398466 A CN 112398466A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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Abstract
The invention discloses a low-voltage high-speed driving circuit, and relates to the technical field of integrated circuits. The circuit comprises a high-speed differential data output sub-circuit, a first-stage buffer input sub-circuit and a second-stage buffer input sub-circuit connected with the first-stage buffer input sub-circuit, wherein the first-stage buffer input sub-circuit comprises a first field effect tube connected to a first differential signal input end, a second field effect tube connected to a second differential signal input end, and a first resistor and a second resistor which are respectively connected to the first field effect tube and the second field effect tube; the second-stage buffer input sub-circuit is connected with the high-speed differential data output sub-circuit, and the high-speed differential data output sub-circuit is also connected with the third field effect transistor. According to the technical scheme, the input low-voltage data information is subjected to differential input amplification, so that the problem that the low-voltage data information cannot reach the threshold voltage of a high-voltage device is solved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a low-voltage high-speed driving circuit.
Background
Universal Serial Bus (USB) 2.0 supports High Speed (480M), Full Speed (12M), and Low Speed (1.5M) data transfers. The high-speed differential data transmission circuit is used for high-speed data transmission, wherein an input buffer stage B and an output stage C form a core circuit of the high-speed drive circuit, and input high-speed differential data pass through the input buffer stage B, then reach the output stage C, and then pass through an output load circuit E to output the high-speed differential data. In the prior art, the power supply voltage of the USB drive is generally 3.3V, and if the power supply voltage of the input data is low (for example, 0.81V), the low voltage may not drive the high voltage tube in the USB drive of 3.3V. Meanwhile, since the data transmission rate in the circuit is as high as 480MHz, it is impossible to convert an input signal of a low voltage (e.g., 0.81V) into a high voltage signal of 3.3V using level conversion. Moreover, replacing the original high voltage tube in the circuit increases circuit cost and design difficulty.
Disclosure of Invention
The invention mainly aims to provide a low-voltage high-speed driving circuit, which aims to drive a high-voltage high-speed universal serial bus when low-voltage data information is input.
In order to achieve the above object, the present invention provides a low-voltage high-speed driving circuit, which comprises a high-speed differential data output sub-circuit, a first-stage buffer input sub-circuit and a second-stage buffer input sub-circuit connected to the first-stage buffer input sub-circuit;
the first-stage buffer input sub-circuit comprises a first field effect transistor connected to a first differential signal input end, a second field effect transistor connected to a second differential signal input end, and a first resistor and a second resistor which are respectively connected to the first field effect transistor and the second field effect transistor, wherein the first field effect transistor and the second field effect transistor are also connected with a third field effect transistor, and the third field effect transistor is connected to a first enabling signal input end; the second-stage buffer input sub-circuit is connected to the high-speed differential data output sub-circuit;
the first differential signal input end and the second differential signal input end input low-voltage data information to the first-stage buffer input sub-circuit for amplification, the amplified data information is sent to the second-stage buffer input sub-circuit for amplification again, the data information amplified again is sent to the high-speed differential data output sub-circuit, and the high-speed differential data output sub-circuit outputs the amplified data information through the load sub-circuit.
Preferably, the gate of the first field effect transistor is connected to the first differential signal input terminal, the source thereof is connected to the first bias current, the drain thereof is connected to one end of the first resistor, and the other end of the first resistor is grounded;
the grid electrode of the second field effect transistor is connected to the second differential signal input end, the source electrode of the second field effect transistor is connected to the first bias current, the drain electrode of the second field effect transistor is connected to one end of the second resistor, and the other end of the second resistor is grounded;
the grid electrode of the third field effect transistor is connected to the first enable signal input end, the source electrode of the third field effect transistor is connected to a power supply, and the drain electrode of the third field effect transistor is connected to the first bias current.
Preferably, the second-stage buffer input sub-circuit comprises a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the fourth field effect transistor is connected to the first field effect transistor and the sixth field effect transistor, the fifth field effect transistor is connected to the second field effect transistor and the seventh field effect transistor, and the eighth field effect transistor is connected to the sixth field effect transistor and the seventh field effect transistor; the sixth field effect transistor is further connected with a third resistor, and the seventh field effect transistor is further connected with a fourth resistor.
Preferably, the gate of the fourth field effect transistor is connected to the drain of the first field effect transistor and the gate of the sixth field effect transistor, the source thereof is connected to the second bias current, and the drain thereof is connected to the drain of the sixth field effect transistor;
the grid electrode of the fifth field effect transistor is connected with the drain electrode of the second field effect transistor and the grid electrode of the seventh field effect transistor, the source electrode of the fifth field effect transistor is connected with the second bias current, and the drain electrode of the fifth field effect transistor is connected with the drain electrode of the seventh field effect transistor;
the drain electrode of the sixth field effect transistor is connected to one end of the third resistor, and the source electrode of the sixth field effect transistor is connected to the other end of the third resistor and the drain electrode of the eighth field effect transistor;
the drain electrode of the seventh field effect transistor is connected to one end of the fourth resistor, and the source electrode of the seventh field effect transistor is connected to the other end of the fourth resistor and the drain electrode of the eighth field effect transistor;
and the grid electrode of the eighth field effect transistor is connected to the second enabling signal input end, and the source electrode of the eighth field effect transistor is grounded.
Preferably, the high-speed differential data output sub-circuit includes a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor and a twelfth field-effect transistor, the ninth field-effect transistor is connected to the second enable signal input terminal and the fourth field-effect transistor, the tenth field-effect transistor is connected to the second enable signal input terminal and the fifth field-effect transistor, the eleventh field-effect transistor is connected to the fourth field-effect transistor, and the twelfth field-effect transistor is connected to the fifth field-effect transistor.
Preferably, the gate of the ninth fet is connected to the second enable signal input terminal, the source thereof is connected to the power supply, and the drain thereof is connected to the drain of the fourth fet;
the grid electrode of the tenth field effect transistor is connected to the second enabling signal input end, the source electrode of the tenth field effect transistor is connected to the power supply, and the drain electrode of the tenth field effect transistor is connected to the drain electrode of the fifth field effect transistor;
the grid electrode of the eleventh field effect transistor is connected to the drain electrode of the fourth field effect transistor, the source electrode of the eleventh field effect transistor is connected to the third bias current, and the drain electrode of the eleventh field effect transistor is connected to the first differential signal output end;
and the grid electrode of the twelfth field effect transistor is connected to the drain electrode of the fifth field effect transistor, the source electrode of the twelfth field effect transistor is connected to the third bias current, and the drain electrode of the twelfth field effect transistor is connected to the second differential signal output end.
Preferably, the first bias current is less than the second bias current; the second bias current is less than the third bias current.
According to the technical scheme, the first-stage buffer input sub-circuit is added in front of the second-stage buffer input sub-circuit, so that input low-voltage data information is subjected to differential input amplification, and when the data transmission rate in the circuit is up to 480MHz, the voltage range enough for driving a high-voltage device is achieved, and the problem that the low-voltage data information cannot reach the threshold voltage of the high-voltage device is solved.
Drawings
Fig. 1 is a schematic circuit diagram of a low-voltage high-speed driving circuit according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
A low-voltage high-speed driving circuit, as shown in FIG. 1, comprises a high-speed differential data output sub-circuit, a first-stage buffer input sub-circuit and a second-stage buffer input sub-circuit connected with the first-stage buffer input sub-circuit;
the first-stage buffer input sub-circuit comprises a first field effect transistor M1 connected to a first differential signal input end DP _ in, a second field effect transistor M2 connected to a second differential signal input end DM _ in, and a first resistor R1 and a second resistor R2 which are respectively connected to the first field effect transistor M1 and the second field effect transistor M2, wherein the first field effect transistor M1 and the second field effect transistor M2 are also connected with a third field effect transistor M3, and the third field effect transistor M3 is connected to a first enable signal input end HS _ ENN 1; the second-stage buffer input sub-circuit is connected to the high-speed differential data output sub-circuit;
the first differential signal input end DP _ in and the second differential signal input end DM _ in input low-voltage data information to the first-stage buffer input sub-circuit for amplification, the amplified data information is sent to the second-stage buffer input sub-circuit for amplification again, the data information amplified again is sent to the high-speed differential data output sub-circuit, and the high-speed differential data output sub-circuit outputs the amplified data information through the load sub-circuit.
Preferably, the gate of the first field effect transistor M1 is connected to the first differential signal input terminal DP _ in, the source thereof is connected to the first bias current I1, the drain thereof is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to GND;
the gate of the second field effect transistor M2 is connected to the second differential signal input terminal DM _ in, the source thereof is connected to the first bias current I1, the drain thereof is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded GND;
the gate of the third fet M3 is connected to the first enable signal input HS _ ENN1, the source thereof is connected to the power source VCC, and the drain thereof is connected to the first bias current I1.
Preferably, the second stage buffer input sub-circuit comprises a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7 and an eighth field effect transistor M8; the fourth fet M4 is connected to the first fet M1 and the sixth fet M6, the fifth fet M5 is connected to the second fet M2 and the seventh fet M7, and the eighth fet M8 is connected to the sixth fet M6 and the seventh fet M7; the sixth field effect transistor M6 is further connected with a third resistor R3, and the seventh field effect transistor M7 is further connected with a fourth resistor R4.
Preferably, the gate of the fourth fet M4 is connected to the drain of the first fet M1 and the gate of the sixth fet M6, the source thereof is connected to the second bias current I2, and the drain thereof is connected to the drain of the sixth fet M6; the gate of the fifth fet M5 is connected to the drain of the second fet M2 and the gate of the seventh fet M7, the source thereof is connected to the second bias current I2, and the drain thereof is connected to the drain of the seventh fet M7; the drain of the sixth field effect transistor M6 is connected to one end of the third resistor R3, and the source thereof is connected to the other end of the third resistor R3 and the drain of the eighth field effect transistor M8; the drain of the seventh field effect transistor M7 is connected to one end of the fourth resistor R4, and the source thereof is connected to the other end of the fourth resistor R4 and the drain of the eighth field effect transistor M8; the gate of the eighth fet M8 is connected to the second enable signal input terminal HS _ EN1, and the source thereof is grounded to GND.
Preferably, the high-speed differential data output sub-circuit includes a ninth fet M9, a tenth fet M10, an eleventh fet M11 and a twelfth fet M12, the ninth fet M9 is connected to the second enable signal input terminal HS _ EN1 and the fourth fet M4, the tenth fet M10 is connected to the second enable signal input terminal HS _ EN1 and the fifth fet M5, the eleventh fet M11 is connected to the fourth fet M4, and the twelfth fet M12 is connected to the fifth fet M5.
Preferably, the gate of the ninth fet M9 is connected to the second enable signal input terminal HS _ EN1, the source thereof is connected to the power source VCC, and the drain thereof is connected to the drain of the fourth fet M4; the gate of the tenth fet M10 is connected to the second enable signal input terminal HS _ EN1, the source thereof is connected to the power source VCC, and the drain thereof is connected to the drain of the fifth fet M5; the gate of the eleventh fet M11 is connected to the drain of the fourth fet M4, the source thereof is connected to the third bias current I3, and the drain thereof is connected to the first differential signal output terminal DP _ out; the gate of the twelfth fet M12 is connected to the drain of the fifth fet M5, the source thereof is connected to the third bias current I3, and the drain thereof is connected to the second differential signal output terminal DM _ out.
In a specific embodiment, the first fet M1, the second fet M2, the third fet M3, the fourth fet M4, the fifth fet M5, the ninth fet M9, the tenth fet M10, the eleventh fet M11, and the twelfth fet M12 are PMOS fets, and the sixth fet M6, the seventh fet M7, and the eighth fet M8 are NMOS fets.
Preferably, the first bias current I1 is smaller than the second bias current I2; the second bias current I2 is less than the third bias current I3.
As shown in fig. 1, the working principle of the embodiment of the present invention is as follows:
before enabling, enabling signals input by a first enabling signal terminal HS _ ENN1 are high, enabling signals input by a second enabling signal terminal HS _ EN1 are low, a third field effect transistor M3 in a first-stage buffer input sub-circuit is disconnected, the first-stage buffer input sub-circuit does not work, meanwhile, an eighth field effect transistor M8 in a second-stage buffer input sub-circuit is disconnected, and the second-stage buffer input sub-circuit does not work; the input of the high-speed differential data output sub-circuit is pulled up to the power supply by the ninth fet M9 and the tenth fet M10, i.e. at this time, the eleventh fet M11 and the twelfth fet M12 are turned off, and at this time, no data is output, i.e. the outputs of the first differential signal output terminal DP _ out and the second differential signal output terminal DM _ out are low.
After the enabling, the enabling signal input by the first enabling signal terminal HS _ ENN1 is low, the enabling signal input by the second enabling signal terminal HS _ EN1 is high, the third field effect transistor M3 in the first-stage buffer input sub-circuit is conducted, the eighth field effect transistor M8 in the second-stage buffer input sub-circuit is conducted, and the first-stage buffer input sub-circuit and the second-stage buffer input sub-circuit can work normally; the ninth fet M9 and the tenth fet M10 are turned off, and the output data of the second stage buffer input sub-circuit can be normally input to the high-speed differential data output sub-circuit and then output through the first differential signal output terminal DP _ out and the second differential signal output terminal DM _ out of the load circuit.
Specifically, when data information with low voltage (for example, 0.81V) is input, the first differential signal input end DP _ in is high (0.81V), the second differential signal input end DM _ in is low (0V), the first bias current I1 flows through the second fet M2 and the second resistor R2, and a voltage Vn1 capable of turning on the seventh fet M7 in the second-stage buffer input sub-circuit is generated, so that the seventh fet M7 is turned on, wherein the voltage at the point Vn2 is pulled down to 0V, and the twelfth fet M12 in the high-speed differential data output sub-circuit is driven, so that the twelfth fet M12 is turned on;
when the second differential signal input terminal DM _ in is high (0.81V) and the first differential signal input terminal DP _ in is low (0V), the first bias current I1 flows through the first fet M1 and the first resistor R1, so as to generate a voltage Vp1 that can turn on the sixth fet M6 in the second stage buffer input sub-circuit, thereby turning on the sixth fet M6, and pulling down the voltage Vp2 to 0V, so as to drive the eleventh fet M11 in the high-speed differential data output sub-circuit, and turn on the eleventh fet M11, thereby completing the entire differential driving process.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (7)
1. A low-voltage high-speed driving circuit comprises a high-speed differential data output sub-circuit, and is characterized in that the circuit also comprises a first-stage buffer input sub-circuit and a second-stage buffer input sub-circuit connected with the first-stage buffer input sub-circuit;
the first-stage buffer input sub-circuit comprises a first field effect transistor connected to a first differential signal input end, a second field effect transistor connected to a second differential signal input end, and a first resistor and a second resistor which are respectively connected to the first field effect transistor and the second field effect transistor, wherein the first field effect transistor and the second field effect transistor are also connected with a third field effect transistor, and the third field effect transistor is connected to a first enabling signal input end; the second-stage buffer input sub-circuit is connected to the high-speed differential data output sub-circuit;
the first differential signal input end and the second differential signal input end input low-voltage data information to the first-stage buffer input sub-circuit for amplification, the amplified data information is sent to the second-stage buffer input sub-circuit for amplification again, the data information amplified again is sent to the high-speed differential data output sub-circuit, and the high-speed differential data output sub-circuit outputs the amplified data information through the load sub-circuit.
2. The low-voltage high-speed driving circuit according to claim 1, wherein the gate of the first fet is connected to the first differential signal input terminal, the source thereof is connected to a first bias current, the drain thereof is connected to one end of the first resistor, and the other end of the first resistor is grounded;
the grid electrode of the second field effect transistor is connected to the second differential signal input end, the source electrode of the second field effect transistor is connected to the first bias current, the drain electrode of the second field effect transistor is connected to one end of the second resistor, and the other end of the second resistor is grounded;
the grid electrode of the third field effect transistor is connected to the first enable signal input end, the source electrode of the third field effect transistor is connected to a power supply, and the drain electrode of the third field effect transistor is connected to the first bias current.
3. The low voltage high speed drive circuit according to claim 2, wherein the second stage buffer input sub-circuit comprises a fourth fet, a fifth fet, a sixth fet, a seventh fet, and an eighth fet; the fourth field effect transistor is connected to the first field effect transistor and the sixth field effect transistor, the fifth field effect transistor is connected to the second field effect transistor and the seventh field effect transistor, and the eighth field effect transistor is connected to the sixth field effect transistor and the seventh field effect transistor; the sixth field effect transistor is further connected with a third resistor, and the seventh field effect transistor is further connected with a fourth resistor.
4. The low-voltage high-speed driving circuit according to claim 3, wherein a gate of the fourth FET is connected to a drain of the first FET and a gate of the sixth FET, a source thereof is connected to the second bias current, and a drain thereof is connected to a drain of the sixth FET;
the grid electrode of the fifth field effect transistor is connected with the drain electrode of the second field effect transistor and the grid electrode of the seventh field effect transistor, the source electrode of the fifth field effect transistor is connected with the second bias current, and the drain electrode of the fifth field effect transistor is connected with the drain electrode of the seventh field effect transistor;
the drain electrode of the sixth field effect transistor is connected to one end of the third resistor, and the source electrode of the sixth field effect transistor is connected to the other end of the third resistor and the drain electrode of the eighth field effect transistor;
the drain electrode of the seventh field effect transistor is connected to one end of the fourth resistor, and the source electrode of the seventh field effect transistor is connected to the other end of the fourth resistor and the drain electrode of the eighth field effect transistor;
and the grid electrode of the eighth field effect transistor is connected to the second enabling signal input end, and the source electrode of the eighth field effect transistor is grounded.
5. The low-voltage high-speed driving circuit according to claim 4, wherein the high-speed differential data output sub-circuit comprises a ninth fet, a tenth fet, an eleventh fet and a twelfth fet, the ninth fet is connected to the second enable signal input terminal and the fourth fet, the tenth fet is connected to the second enable signal input terminal and the fifth fet, the eleventh fet is connected to the fourth fet, and the twelfth fet is connected to the fifth fet.
6. The low-voltage high-speed driving circuit according to claim 5, wherein the gate of the ninth fet is connected to the second enable signal input terminal, the source thereof is connected to the power supply, and the drain thereof is connected to the drain of the fourth fet;
the grid electrode of the tenth field effect transistor is connected to the second enabling signal input end, the source electrode of the tenth field effect transistor is connected to the power supply, and the drain electrode of the tenth field effect transistor is connected to the drain electrode of the fifth field effect transistor;
the grid electrode of the eleventh field effect transistor is connected to the drain electrode of the fourth field effect transistor, the source electrode of the eleventh field effect transistor is connected to the third bias current, and the drain electrode of the eleventh field effect transistor is connected to the first differential signal output end;
and the grid electrode of the twelfth field effect transistor is connected to the drain electrode of the fifth field effect transistor, the source electrode of the twelfth field effect transistor is connected to the third bias current, and the drain electrode of the twelfth field effect transistor is connected to the second differential signal output end.
7. The low voltage high speed drive circuit of claim 6, wherein the first bias current is less than the second bias current; the second bias current is less than the third bias current.
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| CN201910751280.2A CN112398466A (en) | 2019-08-15 | 2019-08-15 | Low-voltage high-speed driving circuit |
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| CN201910751280.2A CN112398466A (en) | 2019-08-15 | 2019-08-15 | Low-voltage high-speed driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI844127B (en) * | 2022-03-25 | 2024-06-01 | 大陸商長鑫存儲技術有限公司 | Control circuit and semiconductor memory |
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| CN109962705A (en) * | 2019-04-19 | 2019-07-02 | 成都锐成芯微科技股份有限公司 | A kind of universal serial bus high-speed driving circuit |
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| US20010040466A1 (en) * | 1998-07-10 | 2001-11-15 | Satoshi Ide | High speed low voltage differential signal driver having reduced pulse width distortion |
| US6366126B1 (en) * | 1998-12-11 | 2002-04-02 | Nec Corporation | Input circuit, output circuit, and input/output circuit and signal transmission system using the same input/output circuit |
| CN101868914A (en) * | 2007-09-27 | 2010-10-20 | 美商豪威科技股份有限公司 | Reduced voltage differential receiver |
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